Metal/ferroelectric/silicon Structure Research Articles

Fabrication and characterization of Sr0.8Bi2.2Ta2O9 /Al2O3 gate stack for ferroelectric field effect transistors

We analyze and report the structural, electrical and ferroelectric properties of Sr0.8Bi2.2Ta2O9/Al2O3/silicon gate stack for ferroelectric field effect transistors (FETs). RF sputtering and plasma-enhanced atomic layer deposition (PEALD) have been used for the deposition of Sr0.8Bi2.2Ta2O9 (SBT) and Al2O3 film, respectively. Different deposition and process parameters of the SBT and Al2O3 films were optimized by obtaining the structural properties of the deposited film, and electrical properties of metal/ferroelectric/silicon (MFeS), metal/insulator/silicon (MIS), and metal/ferroelectric/metal (MFeM) structures. X-ray diffraction analysis reveals the polycrystalline perovskite structure of the SBT film having a dominant intensity peak along direction at different annealing temperatures. Crystalline film morphology with a maximum grain size of 45 nm was confirmed at the annealing temperature of 500 °C by the field emission scanning electron microscopy. Ellipsometric analysis of the SBT film reveals the maximum refractive index of 3.46 at the annealing temperature of 500 °C. Introduction of a 10 nm buffer layer between ferroelectric and silicon substrate shows the improved memory window of 6.07 V in metal/ferroelectric/insulator/silicon (MFeIS) structure as compared to the 3.07 V in the MFeS structure. MFeI(10 nm)S structure also shows improved leakage current characteristics as compared to MFeS structures and endurance greater than 1013 read/write cycles with the data retention time of higher than 10 years.

Lanthanum-doped BiFeO3/ZrO2 gate stack for ferroelectric field effect transistors

A metal–ferroelectric–insulator–semiconductor (MFIS) structure was fabricated with lanthanum (La)-doped BiFeO3 as ferroelectric and ZrO2 as the high-k insulator layer. The BiFeO3 film with 5 M doped La was prepared with sol–gel and ZrO2 film was physically deposited with rf sputtering. Films structural characteristics were obtained using X-ray diffraction and scanning electron microscopy (SEM). The ferroelectric film shows the perovskite structure with orientation (110)/(104) when annealed in the range from 400 to 700 °C. The dielectric film shows an amorphous structure for the same range of annealing temperature. Electrical and ferroelectric properties were obtained by fabricating and characterizing metal/ferroelectric/silicon (MFS), metal/ferroelectric/metal (MFM), metal/insulator/silicon (MIS), metal/ferroelectric/insulator/metal (MFIM) and metal/ferroelectric/insulator/silicon (MFIS) capacitor structures with ferroelectric film of 200 nm thickness and dielectric film of various thicknesses. MFS structure shows a maximum memory window of 3.5 V and leakage current density of 1.4 × 10–8 A/cm2 with ferroelectric film annealed at 500 °C. The memory window was further improved to 6.62 V and leakage current to the order 10–10 A/cm2 with the introduction of 9 nm insulator layer between ferroelectric and silicon. The same device shows an excellent endurance property tested for 1012 cycles and data retention tested for 5.56 h. The device shows a breakdown of 43 V, which is 9 V higher than the MFS structure. To the best of author’s knowledge, this is the first report to integrate La-doped BiFeO3 on ZrO2 (high-k) dielectric for non-volatile memory applications.

Integration of perovskite Pb[Zr0.35Ti0.65]O3/HfO2 ferroelectric-dielectric composite film on Si substrate

PurposeThe purpose of this paper is to investigate the effect of high-k material HfO2 as a buffer layer for the fabrication of metal-ferroelectric-insulator-silicon (MFeIS) structures on Si (100) substrate.Design/methodology/approachRF-sputtered Pb[Zr0.35Ti0.65]O3 or (PZT) and plasma-enhanced atomic layer deposited HfO2 films were selected as the ferroelectric and high-k buffer layer, respectively, for the fabrication of metal-ferroelectric-insulator-silicon (MFeIS) structures on Si (100) substrate. Multiple angle ellipsometry and X-ray diffraction analysis was carried out to obtain the crystal orientation, refractive index and absorption coefficient parameters of the deposited/annealed films. In the different range of annealing temperature, the refractive index was observed in the range of 2.9 to 2 and 1.86 to 2.64 for the PZT and HfO2 films, respectivelyFindingsElectrical and ferroelectric properties of the dielectric and ferroelectric films and their stacks were obtained by fabricating the metal/ferroelectric/silicon (MFeS), metal/ferroelectric/metal, metal/insulator/silicon and MFeIS capacitor structures. A closed hysteresis loop with remnant polarization of 4.6 µC/cm2 and coercive voltage of 2.1 V was observed in the PZT film annealed at 5000 C. Introduction of HfO2 buffer layer (10 nm) improves the memory window from 5.12 V in MFeS to 6.4 V in MFeIS structure with one order reduction in the leakage current density. The same MFeS device was found having excellent fatigue resistance property for greater than 1010 read/write cycles and data retention time more than 3 h.Originality/valueThe MFeIS structure has been fabricated with constant PZT thickness and varied buffer layer (HfO2) thickness. Electrical characteristics shows the improved leakage current and memory window in the MFeIS structures as compared to the MFeS structures. Optimized MFeIS structure with 10-nm buffer layer shows the excellent ferroelectric properties with endurance greater than E10 read/write cycles and data retention time higher than 3 h. The above properties indicate the MFe(100 nm)I(10 nm)S gate stack as a potential candidate for the FeFET-based nonvolatile memory applications.

Impact of HfO2 buffer layer on the electrical characteristics of ferroelectric/high-k gate stack for nonvolatile memory applications

For the proposed work, the electrical properties of metal–ferroelectric–insulator–silicon (MFeIS) capacitors with Sr0.8Bi2.2Ta2O9 (SBT) ferroelectric film deposited on HfO2/Si substrate have been investigated. The SBT film was deposited by RF sputtering and HfO2 film by plasma-enhanced atomic layer deposition (PEALD). The structural characteristic of the deposited ferroelectric and dielectric films was obtained using X-ray diffraction and multiple angle ellipsometric analysis. XRD results indicate the polycrystalline and perovskite structure of the SBT film and amorphous structure of the HfO2 film annealed at different temperatures. SBT film deposited on the silicon substrate and annealed at 500 °C shows the maximum refractive index of 3.46 with the maximum grain size of 32 nm. Metal/ferroelectric/silicon (MFeS), metal/ferroelectric/metal (MFeM), metal/insulator/silicon (MIS) and metal/ferroelectric/insulator/silicon (MFeIS) structures were fabricated to obtain the electrical and ferroelectric properties. MFeIS structure with 10 nm buffer layer shows the improved memory window of 5 V as compared to the 3.07 V in the MFeS structures. MFeI(10 nm)S structure even shows endurance higher than 1012 read/write cycles and data retention for more than 8 h.

Integration of Sr0.8Bi2.2Ta2O9/HfO2 ferroelectric/dielectric composite film on Si substrate for nonvolatile memory applications

Sr0.8Bi2.2Ta2O9 (SBT) ferroelectric and HfO2 dielectric layers were successively deposited onto the p-type (100) Si substrate via RF sputtering. Metal-Ferroelectric-Insulator-Silicon (MFIS) capacitors were fabricated with 200 nm SBT and 10 nm HfO2 film shows the improved memory window of 1.811 V as compared to the 1.27 V in Metal-Ferroelectric-Silicon (MFS) structures. Improvement in leakage current and breakdown voltage was also observed in the MFIS structures as compared to the MFS structures. Degradation of ferroelectric polarization was not pronounced even after applying 8 × 1012 bipolar cycles in MF(200nm)I(10nm)S structures and the device shows significant data retention time of more than 2.5 hours.

Comparative study of structural electrical dielectric and ferroelectric properties of HfO2 deposited by plasma-enhanced atomic layer deposition and radio frequency sputtering technique for the application in 1-T FeFET

For this proposed work, the comparison of structural, electrical, dielectric, and ferroelectric properties of HfO2 film deposited by plasma-enhanced atomic layer deposition (PEALD) and radio frequency (RF) sputtering technique. Various characteristics has been obtained by fabricating the metal-ferroelectric-silicon (MFeS) and metal-ferroelectric-metal (MFeM) capacitors with different thickness of HfO2 (5, 10, 15, 20 nm) as a ferroelectric layer deposited on silicon and TiN/Silicon. The structural properties such as crystallographic phase, grain size with composition and refractive index of the deposited film were measured by X-ray diffraction, Field emission scanning electron microscopy with energy dispersive spectroscopy (FESEM-EDS) and multiple angle ellipsometry with the variation in annealing temperature. MFeS and MFeM structure were fabricated to obtain electrical and ferroelectric properties such as memory window, leakage current density, closed loop hysteresis, remnant polarization, charge, coercive field voltage, data retention time, endurance, and breakdown voltage of the deposited film. MFeS structure shows the memory window and flat band voltage shift of 4 V and 1.72 V, respectively for 10 nm PEALD-deposited HfO2 layer. For the sputtered 15 nm film, maximum memory window of 4.32 V and leakage current density of 1.2 × 108 A/cm2 has been observed at the annealing temperature of 800 °C. Remnant polarization of 4 and 1.2 μC/cm2 obtained for PEALD and sputtered HfO2 film. The fabricated structure shows data retention for greater than 10 years and fatigue resistance for higher than 1012 read/write cycles. The reliability of the thin film was investigated by measuring the breakdown voltages of MFeS structure for different film thickness.

Integration of ferroelectric BIT and dielectric HfO2 on silicon substrate with high data retention and endurance for ferroelectric FET applications

For this proposed work, the electrical and ferroelectric properties of metal–ferroelectric–insulator–silicon (MFeIS) and metal–ferroelectric–insulator–metal (MFeIM) capacitors with Bi4Ti3O12 (BIT) ferroelectric film deposited on HfO2/Si substrate were investigated. Physical vapor deposition technique (RF sputtering) was carried out for the deposition of 100 nm ferroelectric and high-k dielectric film of 5, 10 and 15 nm thickness. The structural properties such as crystallographic phase, grain size with composition and refractive index of the deposited films were measured by X-ray diffraction, field emission scanning electron microscopy with energy dispersive spectroscopy (FESEM-EDS) and multiple angle ellipsometry. Metal/ferroelectric/silicon (MFeS), metal/ferroelectric/metal (MFeM), metal/insulator/silicon (MIS), MFeIS and MFeIM structures were fabricated to obtain the electrical and ferroelectric properties. Investigation shows that the MFeIS structure with 10 nm buffer layer demonstrates improved memory window of 8.81 V as compared to the 3.3 V in the MFeS structure. MFeIM with 10 nm HfO2 buffer layer shows maximum remnant polarization of 4.05 μC/cm2. MFeI (10 nm) S structure even shows endurance higher than 1013 read/write cycles and data retention for more than 10 years. The reliability of the ferroelectric and ferroelectric/dielectric stack was obtained by measuring the breakdown voltage characteristics.

Impact of plasma enhanced atomic layer deposited HfO2 buffer layer on the structural, electrical and ferroelectric properties of metal/ferroelectric/insulator/semiconductor gate stack for non-volatile memory applications

For the proposed work, electrical and ferroelectric characteristics of metal–ferroelectric–insulator–silicon (MFeIS) and metal–ferroelectric–insulator–metal (MFeIM) capacitor structures with Bi4Ti3O12 (BIT) as the ferroelectric film deposited on HfO2/Si substrate has been investigated. RF sputtering has been used for the deposition of BIT layer on the plasma enhanced atomic layer deposited (PEALD) HfO2/Si substrate. The structural properties like crystallographic phase, grain size with composition and refractive index of the deposited films has been measured using X-ray diffraction, Field emission scanning electron microscopy with energy dispersive spectroscopy (FESEM-EDS) and multiple angle ellipsometry. The electrical and ferroelectric properties has been obtained by fabricating metal/ferroelectric/silicon (MFeS), metal/ferroelectric/metal (MFeM), metal/insulator/silicon (MIS), metal/ferroelectric/insulator/silicon (MFeIS) and metal–ferroelectric–insulator–metal (MFeIM) structures and characterizing using keithley 4200 SCS and Precision Premier II ferroelectric tester. Results indicate the improved memory window from 3.3 V in MFeS structure to 6.3 V in MFeIS structure with 10 nm buffer. The MFeIM structure with 10 nm buffer layer shows the maximum remnant polarization of 4.11 μC/cm2 with endurance higher than 1012 read/write cycles and data retention time greater than 10 years.

Structural and electrical properties of ferroelectric BiFeO3/HfO2gate stack for nonvolatile memory applications

Difficulties in the fabrication of direct interface of ferroelectric BiFeO3on the gate of ferroelectric field effect transistor (FeFET) is well known. This paper reports the optimization and fabrication of ferroelectric/dielectric (BiFeO3/HfO[Formula: see text] gate stack for the FeFET applications. RF magnetron sputtering has been used for the deposition of BiFeO3, HfO2films and their stack. X-Ray diffraction (XRD) analysis of BiFeO3shows the dominant perovskite phase of (104), (110) orientation at 2[Formula: see text] at the annealing temperature of 500[Formula: see text]C. XRD analysis also confirms the amorphous nature of the HfO2film at annealing temperature of 400[Formula: see text]C, 500[Formula: see text]C and 600[Formula: see text]C. Multiple angle analysis shows the variation ion the refractive index between 2.98–3.0214 for BiFeO3and 2.74–2.9 for the HfO2film with the annealing temperature. Metal/Ferroelectric/Silicon (MFS), Metal/Ferroelectric/Metal (MFM), Metal/Insulator/Silicon (MIS), and Metal/Ferroelectric/Insulator/Silicon (MFIS) structures have been fabricated to obtain the electric characteristic of the ferroelectric, dielectric and their stacks. Electrical characteristics of the MFIS structure show the memory improvement from 2.7[Formula: see text]V for MFS structure to 4.65[Formula: see text]V for MFIS structure with 8[Formula: see text]nm of buffer dielectric layer. This structure also shows the breakdown voltage of 40[Formula: see text]V with data retention capacity greater than [Formula: see text] iteration cycles.

On the structural and electrical properties of metal–ferroelectric–high k dielectric–silicon structure for non-volatile memory applications

In this article, we report the structural and electrical properties of metal–ferroelectric–high k dielectric–silicon (MFeIS) gate stack for non-volatile memory applications. Thin film of sputtered \(\hbox {SrBi}_{2}\hbox {Nb}_{2}\hbox {O}_{9}\) (SBN) was used as ferroelectric material on 5–15 nm thick high-k dielectric (\(\hbox {Al}_{2}\hbox {O}_{3}\)) buffer layer deposited using plasma-enhanced atomic layer deposition (PEALD). The effect of annealing on structural and electrical properties of SBN and \(\hbox {Al}_{2}\hbox {O}_{3}\) films was investigated in the temperature range of 350–\(1000^{{\circ }}\hbox {C}\). X-ray diffraction results of the SBN and \(\hbox {Al}_{2}\hbox {O}_{3}\) show multiple phase changes with an increase in the annealing temperature. Multiple angle ellipsometry data show the change in the refractive index (n) of SBN film from 2.0941 to 2.1804 for non-annealed to samples annealed at \(600^{{\circ }}\hbox {C}\). For \(\hbox {Al}_{2}\hbox {O}_{3}\) film, \(n < 1.7\) in the case of PEALD and \(n > 1.7\) for sputtered film was observed. The leakage current density in MFeIS structure was observed to two orders of magnitude lower than metal/ferroelectric/silicon (MFeS) structures. Capacitance–voltage (C–V) characteristics for the voltage sweep of −10 to 10 V in dual mode show the maximum memory window of 1.977 V in MFeS structure, 2.88 V with sputtered \(\hbox {Al}_{2}\hbox {O}_{3}\) and 2.957 V with PEALD \(\hbox {Al}_{2}\hbox {O}_{3}\) in the MFeIS structures at the annealing temperature of \(500^{{\circ }}\hbox {C}\).

Memory improvement in lead-free BiFeO3 ferroelectric with high-k Al2O3 buffer layer for non-volatile memory applications

We report the deposition of ferroelectric lead-free BiFeO3 perovskite film on Si (100) substrate by RF magnetron sputtering using Al2O3 as buffer layer. X-ray diffraction and multiple-angle ellipsometric analysis show the pure ferroelectric phase and maximum refractive index of the BiFeO3 film at the annealing temperature of 500 °C. For different annealing temperature of Al2O3 film, amorphous film structure and refractive index in the range 1.7–1.77 has been observed. Metal–ferroelectric–metal (MFeM), metal–ferroelectric–silicon (MFeS), metal–insulator–silicon (MIS) and metal–ferroelectric–insulator–silicon (MFIS) structure have been fabricated with BiFeO3 ferroelectric and Al2O3 insulator layer to investigate the electrical characteristics. Improvement in the memory window from 2.3 V in MFeS structure to 4.8 V in MFeIS structure has been observed with 10 nm buffer layer at the annealing temperature of 500 °C. The MFe(100 nm)I(10 nm)S structure annealed at 500 °C shows the breakdown voltage of 38 V and no degradation in the polarization charge upto the read-write cycles of 108.

Improvement of metal–ferroelectric–silicon structures without buffer layers between Si and ferroelectric films

Si-based metal–ferroelectric–semiconductor (MFS) structures without buffer layers between Si and ferroelectric films have been developed by depositing SrBi2Ta2O9 (SBT) directly on n-type (100)-oriented Si. Some effective processes are adopted to improve the electrical properties of these MFS structures. Contrary to the conventional MFS structures with top electrodes directly on ferroelectrics, our MFS structures have been developed with thin dense SiO2 films deposited between ferroelectric films and top electrodes. Due to the SiO2 films, the leakage current densities of MFS structures are reduced to 2×10-8 A/cm2 under the bias of 5 V. The C-V electrical properties of the MFS structures are greatly improved after annealing at 400 °C in N2 ambient for 1 h. The C-V memory windows are increased to 3 V, which probably results from the decrease of the interface trap density at the Si/SBT interface.

Direct wafer bonding and layer transfer for ferroelectric thin film integration

A novel fabrication process of ferroelectric-semiconductor heterostructures based on direct wafer bonding (DWB) and layer transfer is proposed. Metal-ferroelectric-silicon (MFS) structures were fabricated by both layer transfer process and direct deposition of ferroelectric films onto Si. Detailed transmission electron microscope (TEM) investigations revealed that a direct wafer bonding and layer transfer process yields good quality ferroelectric/Si interfaces. Interface trap measurements show a large difference for MFS structures fabricated by bonding or by direct deposition, respectively. The trap density values were ranging from 2×1012 cm−2eV−1 for SBT/Si directly deposited to 4×1011 cm−2eV−1 for SBT/Si bonded interfaces.

Pb(Zr,Ti)O3-silicon heterostructures fabricated by direct wafer bonding

Pb(Zr, Ti)O3(PZT)-Silicon heterostructures were fabricated by employing the direct wafer bonding method. PZT thin films were deposited on 3 in. Pt-coated Si wafers by chemical solution deposition (CSD). The PZT films were crystallized by a rapid thermal annealing at 700°C for 60 s and characterized by measuring their ferroelectric properties. The thin films were polished by chemical-mechanical polishing (CMP) and then bonded to plain silicon wafers using a micro-cleanroom setup. The room temperature bonded wafers were annealed for 12 hours at temperatures ranging from 200°C to 450°C. The bonding energy increases from 100 mJ/cm2 after room temperature bonding to 1.4 J/cm2 after a 450°C annealing. Metal-ferroelectric-silicon (MFS) structures were obtained by thinning down and etching away the Pt-coated Si wafer. The MFS structures were electrically characterized by capacitance-voltage and current-voltage characteristic measurements.

Direct Wafer Bonding and Layer Transfer: An Innovative way for the Integration of Ferroelectric Oxides into Silicon Technology

ABSTRACTAn innovative fabrication process of ferroelectric-semiconductor heterostructures based on direct wafer bonding has been demonstrated. Ferroelectric thin films of Bi4Ti3O12 (BiT) and Pb(Zr,Ti)O3 (PZT) were deposited on 3” Si wafers using chemical solution deposition (CSD) and subsequently crystallized by conventional and rapid thermal annealing. The films were then polished in order to reach a roughness and waviness suitable for bonding. They were then directly bonded to silicon wafers in a micro-cleanroom and annealed in air at temperatures ranging from 200°C to 500°C. Bonding energies up to 1.5 J/m2 have been achieved which is almost high enough to consider the two bonded wafers as a single body. Metal-Ferroelectric-Silicon (MFS) structures containing the ferroelectric-Si bonded interface were accomplished by polishing down and etching the handling wafer. The MFS structures were electrically characterized by capacitance-voltage (C-V) and charge-voltage (Q-V) measurements.