Metal-ferroelectric-insulator-silicon Research Articles

An Optimized Device Structure with a Highly Stable Process Using Ferroelectric Memory in 3D NAND Flash Memory Applications

In this paper, we propose an optimized device structure with a highly stable process that addresses threshold voltage shift issues in the String-Select-Line (SSL) and Ground-Select-Line (GSL) gates using ferroelectric memory in 3D NAND flash memory applications. The proposed device utilizes nickel (Ni) instead of tungsten (W) for the GSL and SSL gates, enabling optimized polarization properties during the annealing process and leveraging the disparity in thermal expansion coefficients. Notably, the difference in thermal expansion coefficient from tungsten (W), employed in other Word Line (WL) gates, allows effective control over polarization properties. To validate the proposed structure, we fabricated and measured a Metal–Ferroelectric–Insulator–Silicon (MFIS) capacitor utilizing Hafnium–Zirconium Oxide (HZO) material. The measurement results indicate that a change in the upper metal layer results in a more than fivefold increase in the variance of polarization characteristics between the WL gates (responsible for the memory function) and the SSL and GSL gates dedicated to channel control. In addition, process simulation was conducted using the same device structure, confirming the application of tensile stress to the HZO thin film in the case of a W electrode and compressive stress in the case of a Ni electrode. Furthermore, applying this controlled polarization characteristic parameter to the 3D NAND flash memory structure revealed a reduction in the threshold voltage shift of the control gate from a previous change of 2.6 V or more to 0.05 V, facilitating stable control.

Compact Modeling of Multidomain Ferroelectric FETs: Charge Trapping, Channel Percolation, and Nucleation-Growth Domain Dynamics

The (doped-)hafnia-based' ferroelectric FET (FeFET) is a promising candidate for low-power nonvolatile memories and shows potential use as a steep-slope low-power logic device. This requires accurate modeling of the metal-ferroelectric-insulator-silicon (MFIS) gate stack electrostatics. Here, we present a hardware-validated FeFET compact model that resolves three key aspects in the MFIS electrostatics pertaining to a multidomain ferroelectric (FE) layer: 1) the nonradiative multiphonon process-based charge trapping; 2) the source-to-drain channel percolation due to spatial nonuniformity of FE domain switching; and 3) the nucleation-growth domain reversal dynamics using a phenomenological formalism. The polarization charge is calculated by discretized domain switching in transient under distributed coercive fields. Based on the comparison of the model versus experimental data on Hf <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> Zr <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> n-FeFET hardware, we prove that the onset of FE V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> lowering starts with the source-to-drain percolation path formation when enough FE domains have been flipped up by the gate bias. We further demonstrate that the field-independent domain growth is the fundamental origin of the measured steep subthreshold slope during the downward I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> - V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> sweep. The model ultimately aims to lay down the groundwork for a unified FeFET compact model for both memory- and logic-oriented applications.

Fabrication and characterization of Sr0.8Bi2.2Ta2O9 /Al2O3 gate stack for ferroelectric field effect transistors

We analyze and report the structural, electrical and ferroelectric properties of Sr0.8Bi2.2Ta2O9/Al2O3/silicon gate stack for ferroelectric field effect transistors (FETs). RF sputtering and plasma-enhanced atomic layer deposition (PEALD) have been used for the deposition of Sr0.8Bi2.2Ta2O9 (SBT) and Al2O3 film, respectively. Different deposition and process parameters of the SBT and Al2O3 films were optimized by obtaining the structural properties of the deposited film, and electrical properties of metal/ferroelectric/silicon (MFeS), metal/insulator/silicon (MIS), and metal/ferroelectric/metal (MFeM) structures. X-ray diffraction analysis reveals the polycrystalline perovskite structure of the SBT film having a dominant intensity peak along direction at different annealing temperatures. Crystalline film morphology with a maximum grain size of 45 nm was confirmed at the annealing temperature of 500 °C by the field emission scanning electron microscopy. Ellipsometric analysis of the SBT film reveals the maximum refractive index of 3.46 at the annealing temperature of 500 °C. Introduction of a 10 nm buffer layer between ferroelectric and silicon substrate shows the improved memory window of 6.07 V in metal/ferroelectric/insulator/silicon (MFeIS) structure as compared to the 3.07 V in the MFeS structure. MFeI(10 nm)S structure also shows improved leakage current characteristics as compared to MFeS structures and endurance greater than 1013 read/write cycles with the data retention time of higher than 10 years.

Investigation of ferroelectric field-effect transistors using a replacement metal gate process

The negative-capacitance field-effect transistor (NCFET) is an emerging steep switching device that utilizes the negative capacitance of the ferroelectric layer to induce voltage amplification in the gate stack. In this study, an NCFET was fabricated by using a replacement metal gate process, which can avoid the influence of high temperature processes on ferroelectric film. The different sub-threshold slope (SS) characteristics of forward gate voltage sweep and reverse gate voltage sweep were investigated. The results show that the different SS characteristics may originate from asymmetrical polarization–voltage (P–V) hysteresis loops of metal–ferroelectric–insulator–silicon capacitance in the NCFET. Moreover, the influences of Hf/Zr ratio, annealing temperature and capacitance size on ferroelectric characteristics were investigated. The experimental results show that there is an optimal Hf/Zr ratio and annealing temperature that maximizes the residual polarization (P r). For ferroelectric field-effect transistor (FeFET) memory design, the largest P r should be chosen to increase retention time. For ferroelectric NCFET logic design, the negative capacitance can be adjusted by changing the Hf/Zr ratio and annealing temperature to achieve better capacitance matching between positive capacitance and negative capacitance. It is expected that experimental results may provide some guidance for the design and performance enhancement of FeFETs and NCFETs.

Development of highly reliable BiFeO3/HfO2/Silicon gate stacks for ferroelectric non-volatile memories in IoT applications

We have investigated the structural, electrical, and ferroelectric properties of metal–ferroelectric-high-k-silicon capacitors with BiFeO3 ferroelectric films deposited on the HfO2/Si substrate. BiFeO3, HfO2 films, and their stack were deposited on the silicon substrate using RF magnetron sputtering and plasma-enhanced atomic layer deposition (PEALD). Film crystal orientation, refractive index, and absorption constant parameters were extracted from X-ray diffraction and ellipsometric analysis. Electrical characterization of metal/ferroelectric/metal (MFM), metal/ferroelectric/silicon (MFS), metal/dielectric/silicon (MIS), and metal/ferroelectric/insulator/silicon (MFIS) capacitor structures provide memory window, leakage current density, hysteresis, fatigue, and data retention time. The metal/ferroelectric/silicon structure exhibits clockwise capacitance–voltage characteristics with the memory window of 5.04 V for the bias voltage of ± 10 V. The electrical and ferroelectric characteristics of MFIS structures were studied for different thicknesses of HfO2 layer, which shows that the introduction of high-k dielectric film between ferroelectric and silicon improves the interface quality. The memory window of the MFIS structure was found to significantly increase to 9.65 V with the introduction of a 10 nm HfO2 layer between the ferroelectric layer and the silicon substrate. Two-order reduction in the leakage current density was also observed in the MF(200 nm)I(10 nm)S structure as compared to the MF(200 nm)S structure. The fabricated MF(200 nm)I(10 nm)S gate stack shows fatigue resistance for read/write operations greater than 1012 cycles and data retention time for greater than 104 s. To the best of author’s knowledge, this is the first investigation to integrate pure BiFeO3 on PEALD-HfO2 dielectric for the gate stack of ferroelectric field effect transistors.

Structural and electrical properties of Al/BiFeO3/ZrO2/n-Si structure for non-volatile memory application

In this communication, the structural and electrical properties of metal–ferroelectric–insulator–silicon (MFIS) capacitor structure have been reported for non-volatile memory applications. Sol–gel with spin coating and rf sputtering process have been used for depositing BiFeO3 (BFO) and ZrO2 films, respectively. It has been observed that BFO film shows pure ferroelectric phase, uniform grain size and maximum refractive index at annealing temperature of 500 °C. Thermo-gravimetric analyzer and differential scanning calorimetry analysis indicate good agreement with X-ray diffraction of BFO film. In ZrO2 thin film, it has been observed that ZrO2 is in amorphous state at all annealing temperatures and the maximum refractive index has been found at annealing temperature of 400 °C. Al/ZrO2/n-Si (MIS), Al/BiFeO3/n-Si (MFS) and Al/BiFeO3/ZrO2/n-Si (MFIS) structures have been fabricated to investigate the electrical characteristics. The memory window has been observed by capacitance–voltage (C–V) characteristics and it improves from 1.9 V in MFS structure to 5.4 V in MFIS structure with 8 nm dielectric layer. Leakage current density has been observed by current density–gate voltage (J–V) characteristics and it is order of 10−5 A/cm2 in MF150 nmI8 nmS structure. No charge value degrades up to 1012 iteration cycles in MF150 nmI8 nmS structure.

Integration of perovskite Pb[Zr0.35Ti0.65]O3/HfO2 ferroelectric-dielectric composite film on Si substrate

PurposeThe purpose of this paper is to investigate the effect of high-k material HfO2 as a buffer layer for the fabrication of metal-ferroelectric-insulator-silicon (MFeIS) structures on Si (100) substrate.Design/methodology/approachRF-sputtered Pb[Zr0.35Ti0.65]O3 or (PZT) and plasma-enhanced atomic layer deposited HfO2 films were selected as the ferroelectric and high-k buffer layer, respectively, for the fabrication of metal-ferroelectric-insulator-silicon (MFeIS) structures on Si (100) substrate. Multiple angle ellipsometry and X-ray diffraction analysis was carried out to obtain the crystal orientation, refractive index and absorption coefficient parameters of the deposited/annealed films. In the different range of annealing temperature, the refractive index was observed in the range of 2.9 to 2 and 1.86 to 2.64 for the PZT and HfO2 films, respectivelyFindingsElectrical and ferroelectric properties of the dielectric and ferroelectric films and their stacks were obtained by fabricating the metal/ferroelectric/silicon (MFeS), metal/ferroelectric/metal, metal/insulator/silicon and MFeIS capacitor structures. A closed hysteresis loop with remnant polarization of 4.6 µC/cm2 and coercive voltage of 2.1 V was observed in the PZT film annealed at 5000 C. Introduction of HfO2 buffer layer (10 nm) improves the memory window from 5.12 V in MFeS to 6.4 V in MFeIS structure with one order reduction in the leakage current density. The same MFeS device was found having excellent fatigue resistance property for greater than 1010 read/write cycles and data retention time more than 3 h.Originality/valueThe MFeIS structure has been fabricated with constant PZT thickness and varied buffer layer (HfO2) thickness. Electrical characteristics shows the improved leakage current and memory window in the MFeIS structures as compared to the MFeS structures. Optimized MFeIS structure with 10-nm buffer layer shows the excellent ferroelectric properties with endurance greater than E10 read/write cycles and data retention time higher than 3 h. The above properties indicate the MFe(100 nm)I(10 nm)S gate stack as a potential candidate for the FeFET-based nonvolatile memory applications.

Impact of HfO2 buffer layer on the electrical characteristics of ferroelectric/high-k gate stack for nonvolatile memory applications

For the proposed work, the electrical properties of metal–ferroelectric–insulator–silicon (MFeIS) capacitors with Sr0.8Bi2.2Ta2O9 (SBT) ferroelectric film deposited on HfO2/Si substrate have been investigated. The SBT film was deposited by RF sputtering and HfO2 film by plasma-enhanced atomic layer deposition (PEALD). The structural characteristic of the deposited ferroelectric and dielectric films was obtained using X-ray diffraction and multiple angle ellipsometric analysis. XRD results indicate the polycrystalline and perovskite structure of the SBT film and amorphous structure of the HfO2 film annealed at different temperatures. SBT film deposited on the silicon substrate and annealed at 500 °C shows the maximum refractive index of 3.46 with the maximum grain size of 32 nm. Metal/ferroelectric/silicon (MFeS), metal/ferroelectric/metal (MFeM), metal/insulator/silicon (MIS) and metal/ferroelectric/insulator/silicon (MFeIS) structures were fabricated to obtain the electrical and ferroelectric properties. MFeIS structure with 10 nm buffer layer shows the improved memory window of 5 V as compared to the 3.07 V in the MFeS structures. MFeI(10 nm)S structure even shows endurance higher than 1012 read/write cycles and data retention for more than 8 h.

Integration of Sr0.8Bi2.2Ta2O9/HfO2 ferroelectric/dielectric composite film on Si substrate for nonvolatile memory applications

Sr0.8Bi2.2Ta2O9 (SBT) ferroelectric and HfO2 dielectric layers were successively deposited onto the p-type (100) Si substrate via RF sputtering. Metal-Ferroelectric-Insulator-Silicon (MFIS) capacitors were fabricated with 200 nm SBT and 10 nm HfO2 film shows the improved memory window of 1.811 V as compared to the 1.27 V in Metal-Ferroelectric-Silicon (MFS) structures. Improvement in leakage current and breakdown voltage was also observed in the MFIS structures as compared to the MFS structures. Degradation of ferroelectric polarization was not pronounced even after applying 8 × 1012 bipolar cycles in MF(200nm)I(10nm)S structures and the device shows significant data retention time of more than 2.5 hours.

Integration of ferroelectric BIT and dielectric HfO2 on silicon substrate with high data retention and endurance for ferroelectric FET applications

For this proposed work, the electrical and ferroelectric properties of metal–ferroelectric–insulator–silicon (MFeIS) and metal–ferroelectric–insulator–metal (MFeIM) capacitors with Bi4Ti3O12 (BIT) ferroelectric film deposited on HfO2/Si substrate were investigated. Physical vapor deposition technique (RF sputtering) was carried out for the deposition of 100 nm ferroelectric and high-k dielectric film of 5, 10 and 15 nm thickness. The structural properties such as crystallographic phase, grain size with composition and refractive index of the deposited films were measured by X-ray diffraction, field emission scanning electron microscopy with energy dispersive spectroscopy (FESEM-EDS) and multiple angle ellipsometry. Metal/ferroelectric/silicon (MFeS), metal/ferroelectric/metal (MFeM), metal/insulator/silicon (MIS), MFeIS and MFeIM structures were fabricated to obtain the electrical and ferroelectric properties. Investigation shows that the MFeIS structure with 10 nm buffer layer demonstrates improved memory window of 8.81 V as compared to the 3.3 V in the MFeS structure. MFeIM with 10 nm HfO2 buffer layer shows maximum remnant polarization of 4.05 μC/cm2. MFeI (10 nm) S structure even shows endurance higher than 1013 read/write cycles and data retention for more than 10 years. The reliability of the ferroelectric and ferroelectric/dielectric stack was obtained by measuring the breakdown voltage characteristics.

Impact of plasma enhanced atomic layer deposited HfO2 buffer layer on the structural, electrical and ferroelectric properties of metal/ferroelectric/insulator/semiconductor gate stack for non-volatile memory applications

For the proposed work, electrical and ferroelectric characteristics of metal–ferroelectric–insulator–silicon (MFeIS) and metal–ferroelectric–insulator–metal (MFeIM) capacitor structures with Bi4Ti3O12 (BIT) as the ferroelectric film deposited on HfO2/Si substrate has been investigated. RF sputtering has been used for the deposition of BIT layer on the plasma enhanced atomic layer deposited (PEALD) HfO2/Si substrate. The structural properties like crystallographic phase, grain size with composition and refractive index of the deposited films has been measured using X-ray diffraction, Field emission scanning electron microscopy with energy dispersive spectroscopy (FESEM-EDS) and multiple angle ellipsometry. The electrical and ferroelectric properties has been obtained by fabricating metal/ferroelectric/silicon (MFeS), metal/ferroelectric/metal (MFeM), metal/insulator/silicon (MIS), metal/ferroelectric/insulator/silicon (MFeIS) and metal–ferroelectric–insulator–metal (MFeIM) structures and characterizing using keithley 4200 SCS and Precision Premier II ferroelectric tester. Results indicate the improved memory window from 3.3 V in MFeS structure to 6.3 V in MFeIS structure with 10 nm buffer. The MFeIM structure with 10 nm buffer layer shows the maximum remnant polarization of 4.11 μC/cm2 with endurance higher than 1012 read/write cycles and data retention time greater than 10 years.

Structural and electrical properties of ferroelectric BiFeO3/HfO2gate stack for nonvolatile memory applications

Difficulties in the fabrication of direct interface of ferroelectric BiFeO3on the gate of ferroelectric field effect transistor (FeFET) is well known. This paper reports the optimization and fabrication of ferroelectric/dielectric (BiFeO3/HfO[Formula: see text] gate stack for the FeFET applications. RF magnetron sputtering has been used for the deposition of BiFeO3, HfO2films and their stack. X-Ray diffraction (XRD) analysis of BiFeO3shows the dominant perovskite phase of (104), (110) orientation at 2[Formula: see text] at the annealing temperature of 500[Formula: see text]C. XRD analysis also confirms the amorphous nature of the HfO2film at annealing temperature of 400[Formula: see text]C, 500[Formula: see text]C and 600[Formula: see text]C. Multiple angle analysis shows the variation ion the refractive index between 2.98–3.0214 for BiFeO3and 2.74–2.9 for the HfO2film with the annealing temperature. Metal/Ferroelectric/Silicon (MFS), Metal/Ferroelectric/Metal (MFM), Metal/Insulator/Silicon (MIS), and Metal/Ferroelectric/Insulator/Silicon (MFIS) structures have been fabricated to obtain the electric characteristic of the ferroelectric, dielectric and their stacks. Electrical characteristics of the MFIS structure show the memory improvement from 2.7[Formula: see text]V for MFS structure to 4.65[Formula: see text]V for MFIS structure with 8[Formula: see text]nm of buffer dielectric layer. This structure also shows the breakdown voltage of 40[Formula: see text]V with data retention capacity greater than [Formula: see text] iteration cycles.

Memory improvement in lead-free BiFeO3 ferroelectric with high-k Al2O3 buffer layer for non-volatile memory applications

We report the deposition of ferroelectric lead-free BiFeO3 perovskite film on Si (100) substrate by RF magnetron sputtering using Al2O3 as buffer layer. X-ray diffraction and multiple-angle ellipsometric analysis show the pure ferroelectric phase and maximum refractive index of the BiFeO3 film at the annealing temperature of 500 °C. For different annealing temperature of Al2O3 film, amorphous film structure and refractive index in the range 1.7–1.77 has been observed. Metal–ferroelectric–metal (MFeM), metal–ferroelectric–silicon (MFeS), metal–insulator–silicon (MIS) and metal–ferroelectric–insulator–silicon (MFIS) structure have been fabricated with BiFeO3 ferroelectric and Al2O3 insulator layer to investigate the electrical characteristics. Improvement in the memory window from 2.3 V in MFeS structure to 4.8 V in MFeIS structure has been observed with 10 nm buffer layer at the annealing temperature of 500 °C. The MFe(100 nm)I(10 nm)S structure annealed at 500 °C shows the breakdown voltage of 38 V and no degradation in the polarization charge upto the read-write cycles of 108.

Impact of process parameters on the structural and electrical properties of metal/PZT/Al2O3/silicon gate stack for non-volatile memory applications

In this paper, we present the structural and electrical properties of the Al2O3 buffer layer on non-volatile memory behavior using Metal/PZT/Al2O3/Silicon structures. Metal/PZT/Silicon and Metal/Al2O3/Silicon structures were also fabricated and characterized to obtain capacitance and leakage current parameters. Lead zirconate titanate (PZT::35:65) and Al2O3 films were deposited by sputtering on the silicon substrate. Memory window, PUND, endurance, breakdown voltage, effective charges, flat-band voltage and leakage current density parameters were measured and the effects of process parameters on the structural and electrical characteristics were investigated. X-ray data show dominant (110) tetragonal phase of the PZT film, which crystallizes at 500 °C. The sputtered Al2O3 film annealed at different temperatures show dominant (312) orientation and amorphous nature at 425 °C. Multiple angle laser ellipsometric analysis reveals the temperature dependence of PZT film refractive index and extinction coefficient. Electrical characterization shows the maximum memory window of 3.9 V and breakdown voltage of 25 V for the Metal/Ferroelectric/Silicon (MFeS) structures annealed at 500 °C. With 10 nm Al2O3 layer in the Metal/Ferroelectric/Insulator/Silicon (MFeIS) structure, the memory window and breakdown voltage was improved to 7.21 and 35 V, respectively. Such structures show high endurance with no significant reduction polarization charge for upto 2.2 × 109 iteration cycles.

Analytic model for the electrical properties of negative capacitance metal-ferroelectric insulator silicon (MFIS) capacitor

ABSTRACTIn this paper, we present an analytical model for the voltages across the Metal-Ferroelectric-Insulator-Silicon(MFIS) capacitor and show how the surface potential is amplified due to the negative capacitance property of ferroelectric materials. Our model is based on the Landau-Khalatnikov equation coupled with the charge based MOS capacitor model. It is also used to analyse the effect on the total capacitance of the MFIS capacitor. Furthermore, we analyse the impact of ferroelectric and gate oxide thicknesses on the amplified surface potential and also on the threshold voltage of the capacitor.

Notice of Removal: A Novel Metal-Ferroelectric-Insulator-Silicon FET With Selectively Nucleated Lateral Crystallized Pb(Zr,Ti)O3 and ZrTiO4 Buffer for Long Retention and Good Fatigue

Removed.

Large memory window and good retention characteristics of ferroelectric-gate field-effect transistor with Pt/Bi3.4Ce0.6Ti3O12/CeO2/Si structure

Bi4−xCexTi3 O12(x = 0.0, 0.4, 0.6 and 1.0) ferroelectric-thin films were fabricated by chemical solution deposition. Among these thin film samples, Bi3.4Ce0.6Ti3O12 (BCT) exhibits the best ferroelectric property. An n-channel metal–ferroelectric–insulator–silicon (MFIS) ferroelectric-gate field-effect transistor (FeFET) with Pt/BCT/CeO2/Si structure was fabricated and characterized. Due to the relatively good interface properties between the insulator layer (CeO2) and ferroelectric-gate layer (BCT), the device shows a nearly unchanged memory window of about 3.2 V after a 24 h retention test and a field-effect mobility of approximately 24.6 cm2 V−1 s−1. These results suggest that the Pt/BCT/CeO2/Si FeFET is suitable for high-performance ferroelectric memory application.

Modeling of flexoelectric effect on capacitor-voltage and memory window of metal-ferroelectric-insulator-silicon capacitor

The flexoelectric effect on electrical behaviors of metal-ferroelectric-insulator-silicon (MFIS) capacitor was investigated by considering stress gradient in Landau–Khalatnikov theory. In the presence of flexoelectric coupling, the compressive stress shifts capacitor-voltage (C-V) loop of MFIS capacitor to the negative voltage axis and enlarges memory window, however, the tensile stress shifts C-V loop to the positive voltage axis and compresses memory window. The magnitudes of stress, flexoelectric coefficient, and characteristic length of stress distribution have a significant influence on C-V characteristic and memory window of MFIS capacitor. The results show stress gradient should be avoided to prevent failure of MFIS capacitor.

Effect of processing temperature on characteristics of metal-ferroelectric (BiFeO 3)-insulator (HfLaO)-silicon capacitors

The effect of temperature in rapid thermal annealing (RTA) process on the physical and electrical properties of bismuth ferrite ceramic thin films on HfLaO/p-Si substrates has been investigated. In metal-ferroelectric–insulator–silicon (MFIS) capacitors, the high-k HfLaO dielectric layer was prepared as the insulator layer. On HfLaO/Si substrates the bismuth ferrite thin film was fabricated via sputtering process with a BiFeO 3 (BFO) target at room temperature followed by RTA. The RTA temperature ranged from 500 to 700 °C. It is found that the root mean square roughness of ceramic films increases for high-temperature process. The maximum ferroelectric memory window is 1.6 V obtained from a sweep voltage of ± 4 V at the lowest RTA temperature of 500 °C. This good ferroelectric memory performance can be attributed to the low leakage current as a result of smooth surface of nanocrystalline ferroelectric BFO and Bi 2Fe 4O 9 thin films.

Evaluation of capacitance-voltage characteristic and memory window of metal-ferroelectric-insulator-silicon capacitors

It is recognized that the conventional model for metal-ferroelectric-insulator-silicon (MFIS) capacitor is always not consistent with the experimental observation very well due to negligence of the history-dependent electric field effect. In this letter, combining the switching physics of ferroelectric with silicon physics, an improved model is proposed to investigate the capacitance-voltage (C-V) characteristic and memory window. For two MFIS capacitors with SrBi2Ta2O9 and Bi3.25La0.75Ti3O12 ferroelectric layers, C-V characteristic and memory window were evaluated, and the results are more consistent with the previous experiments than that of the Lue model. The improved model could be extendedly applied to MFIS structure devices.