Mesh-connected Processor Array Research Articles

Self-restructuring Mesh-connected Processor Arrays through Spares on Moved Diagonals, Direct Replacement and Built-in Circuits

Self-restructuring Mesh-connected Processor Arrays through Spares on Moved Diagonals, Direct Replacement and Built-in Circuits

Reconfiguration algorithms for synchronous communication on switch based degradable arrays

Synchronous communication is one of the most important issues in high performance architectures for large scale of parallel computing, such as matrix computing, image processing, etc. Mesh-connected processor array is characteristic of synchronous communication due to the same length of the interconnects between the neighboring processing elements (PEs) in rows/columns. But long interconnects caused by faulty PEs clearly impact the synchronous communication between the adjacent rows/columns. If long interconnects exist between two adjacent rows, we say that a synchronous communication delay is caused. This paper contributes algorithms to construct logical arrays with synchronous communication in a given host array. Specifically, an algorithm for synchronous communication array (ASCA) is firstly presented, to construct a maximum logical array with synchronous communication. When all of the long interconnects are independent each other, the proposed algorithm is proved to be optimal. After that, two heuristic algorithms are also proposed, to construct a logical array with given size, by integrating the proposed ASCA and two exclusion schemes. The proposed two exclusion schemes are based on strategies of divide-and-conquer and the longest logical column first, respectively. In addition, the lower bound of synchronous communication delay for a logical array is calculated by an algorithm also developed in this paper, in order to evaluate the synchronous performance of reconfiguration algorithms. Simulation results show that, the proposed two heuristic algorithms have their own advantages for different cases. The synchronous communication delay of the logical arrays is significantly reduced, and it is very close to the lower bound for the cases of small fault density and larger exclusion rate. For 32 × 32 physical arrays with exclusion rates that are larger than 15%, the synchronous communication delay of logical array is reduced from 11.09 to 6.97, which is more closer to the lower bound 4.43, for different fault densities on average.

A mathematical programming method for constructing the shortest interconnection VLSI arrays

Mesh-connected processor array is an extensively investigated architecture in parallel processing. Massive studies have addressed the problem of using reconfiguration algorithms to solve the fault tolerance of faulty mesh-connected processor arrays. However, the subarrays generated by the previous studies still contain large interconnection length, which will lead to the increase of capacitance, power dissipation and dynamic communication cost. First, a mathematical model is established for the array reconfiguration. Then, the proposed method treats the interconnections between each PEs as a function with different integer variables, which can be solved by using effective integer programming techniques. Finally, an effective solver is called to find the optimal solution. Simulation results show that the proposed method can reduce the interconnection length of the array in the row and column directions simultaneously, thereby generating a subarray with the shortest interconnection length. On a 32 × 32 host array with fault density of 30%, the total interconnection length of the subarray can be reduced by 8.36% compared with state-of-the-art, and the average interconnection length can be reduced by 39.30%, which is more closer to the lower bound.

A Mathematical Model for Reconfiguring VLSI Subarrays Under Row and Column Rerouting

Increasing the size of target arrays is beneficial to reuse fault-free processing elements (PEs) for reconfiguring 2-D mesh-connected processor arrays with faults. In this paper, we discuss the reconfiguration problem under the row and column rerouting constraint. We present a novel approach, making use of the idea of integer programming, for constructing larger size target arrays. Meanwhile, we propose a new method to deal with the fault-free processing elements in the physical row that is selected for exclusion. Compared with the state-of-arts algorithms, our method can make the fault-free PEs used as much as possible, which means the size of the target array can be significantly improved. Experimental results show that, compared with previous studies, the proposed algorithm achieves better results in terms of the usage rate of fault-free PEs in the host array.

Optimal Reconfiguration of High-Performance VLSI Subarrays with Network Flow

A two-dimensional mesh-connected processor array is an extensively investigated architecture used in parallel processing. Massive studies have addressed the use of reconfiguration algorithms for the processor arrays with faults. However, the subarray generated by previous algorithms contains a large number of long interconnects, which in turn leads to more communication costs, capacitance and dynamic power dissipation. In this paper, we propose novel techniques, making use of the idea of network flow, to construct the high-performance subarray, which has the minimum number of long interconnects. First, we construct a network flow model according to the host array under a specific constraint. Second, we show that the reconfiguration problem of high-performance subarray can be optimally solved in polynomial time by using efficient minimum-cost flow algorithms. Finally, we prove that the geometric properties of the resulted subarray meet the system requirements. Simulations based on several random and clustered fault scenarios clearly reveal the advantage of the proposed technique for reducing the number of long interconnects. It is shown that, for a host array of size $512 \times 512$ , the number of long interconnects in the subarray can be reduced by up to 70.05 percent for clustered faults and by up to 55.28 percent for random faults with density of 1 percent as compared to the-state-of-the-art.

Parallel reconfiguration algorithms for mesh-connected processor arrays

Effective fault tolerance techniques are essential for improving the reliability of multiprocessor systems. At the same time, fault tolerance must be achieved at high speed to meet the real-time constraints of embedded systems. While parallelism has often been exploited to increase performance, to the best of our knowledge, there has been no previously reported work on parallel reconfiguration of mesh-connected processor arrays with faults. This paper presents two parallel algorithms to accelerate reconfiguration of the processor arrays. The first algorithm reconfigures a host array in parallel in a multithreading manner. The threads in the parallel algorithm execute independently within a safe rerouting distance. The second algorithm is based on a divide-and-conquer approach to first generate the leftmost segments in parallel and then merge the segments in parallel. When compared to the conventional algorithm, simulation results from a large number of instances confirm that the proposed algorithms significantly accelerate the reconfiguration without loss of harvest.

Effective Partitioning of Static Global Buses for Small Processor Arrays

Abstract —This paper shows an effective partitioning of static global row/column buses for tightly coupled 2D mesh-connected small processor arrays (“mesh”, for short). With additional O( n/m ( n/m + log m )) time slowdown, it enables the mesh of size m×m with static row/column buses to simulate the mesh of the larger size n×n with reconfigurable row/column buses ( m ≤ n ). This means that if a problem can be solved in O(T) time by the mesh of size n×n with reconfigurable buses, then the same problem can be solved in O ( T n/m ( n/m + log m )) time on the mesh of a smaller size m×m without a reconfigurable function. This time-cost is optimal when the relation n ≥ m log m holds (e.g., m = n 1-e for e > 0). Keywords —Processor Array, Dynamically Reconfigurable Bus, Statically Partitioned Bus, Scaling-Simulation, Polylogarithmic Time Simulation 1. I NTRODUCTION The mesh-connected processor array (“mesh”, for short) is one of fundamental parallel com-putational models. Its architecture is suitable for VLSI implementation and allows for a high degree of integration. However, the mesh has a crucial drawback in that its communication di-ameter is quite large due to the lack of a broadcasting mechanism. To overcome this problem, many researchers have considered adding broadcasting buses to the mesh [1-6]. Consider a linear processor array of

A linear-time algorithm for computing collision-free path on reconfigurable mesh

The reconfigurable mesh (RMESH) is an array of mesh-connected processors equipped with a reconfigurable bus system, which can dynamically connect the processors in various patterns. A 2D reconfigurable mesh can be used to solve motion planning problems in robotics research, in which the 2D image of robot and obstacles are digitized and represented one pixel per processor. In this paper, we present an algorithm to compute a collision-free path between two points in an environment containing obstacles. The time complexity of the algorithm is O ( k ) for each pair of source/destination points, with O ( log 2 N ) preprocessing time, where k is the number of obstacles in the working environment, and N is the size of the reconfigurable mesh.

Parallel ART for image reconstruction in CT using processor arrays

Algebraic Reconstruction Technique (ART) is a widely-used iterative method for solving sparse systems of linear equations. This method (originally due to Kaczmarz) is inherently sequential according to its mathematical definition since, at each step, the current iterate is projected toward one of the hyperplanes defined by the equations. The main advantages of ART are its robustness, its cyclic convergence on inconsistent systems, and its relatively good initial convergence. ART is widely used as an iterative solution to the problem of image reconstruction from projections in computerized tomography (CT), where its implementation with a small relaxation parameter produces excellent results. It is shown that for this particular problem, ART can be implemented in parallel on a linear processor array. Reconstructing an image of n pixels from Θ(n) equations can be done on a linear array of processors with optimal efficiency (linear speedup) and O(n/p) memory for each processor. The parallel technique can be applied to various geometric models of image reconstruction, as well as to 3D reconstruction with spherically symmetric volume elements, using a 2D rectangular mesh-connected array of processors.

A Self-Reconfigurable Hardware Architecture for Mesh Arrays Using Single/Double Vertical Track Switches

This paper deals with the issue of reconfiguring mesh-connected processor arrays (mesh arrays) in the presence of faulty processors. For massively parallel systems, it has become necessary to develop built-in self-reconfigurable systems that can automatically reconfigure partially faulty systems. Many reconfiguration methods have been proposed to date; however, most of them are not suitable for self-reconfiguration. In this paper, we propose a self-reconfiguration method based on simple column bypass and south directional rerouting schemes. This proposal offers the combined advantages of high probability of successful reconfiguration, low hardware overhead, and simplicity of implementation. A switching mechanism, which can determine the desired switch functions automatically using the states of neighboring processors, makes the implementation of our method easier. Simulated results show that the proposed method achieves a higher system yield than that of previous methods with half the number of redundant switches and interconnections. The prototype system of self-reconfigurable mesh arrays is implemented using a field-programmable gate array (FPGA) and the hardware overhead is discussed.

Chain grouping: a method for partitioning loops onto mesh-connected processor arrays

This paper presents Chain Grouping, a new low complexity method for the problem of partitioning the loop iteration space into groups with little intercommunication requirements, for mapping onto mesh-connected architectures. First, the iterations are scheduled in time, according to the hyperplane method, taking into consideration the minimum time displacement. Then, the iteration space is divided into discrete groups of related iterations, which are assigned to different processors, while preserving the optimal completion time. Chain Grouping is based on clustering together neighboring uniform chains of iterations, formed by a particular dependence vector. This vector will be proven as the best among all to reduce the total communication requirements. Inside every group, the optimal hyperplane scheduling is preserved and references to intragroup iterations are considerably increased. The partitioned groups are afterward assigned to meshes of processors. The resulting space mapping maximizes processor utilization and cuts down overall communication delays while preserving the optimal hyperplane time schedule.

Fault-tolerant processor arrays based on the 1 1/2 -track switches with flexible spare distributions

A mesh-connected processor array consists of many similar processing elements (PEs) which can be executed in both parallel and pipeline processing. For the implementation of an array of large numbers of processors, some fault-tolerant issues are necessary to enhance the (fabrication-time) yield and the (run-time) reliability. In this paper, we propose a fault-tolerant reconfigurable processor array using single-track switches like Kung et al.'s model. The reconfiguration process in our model is executed based on the concept of the "compensation path" like Kung et al.'s method, too. In our model, spare PEs are not necessarily put around the array, but are more flexibly put in the array by changing connections between spare PEs and nonspare PEs while retaining the connections among nonspare PEs in the same manner in Kung et al.'s model. The proposed model has such a desirable property that physical distances between logically adjacent PEs in the reconfigured array are within a constant, that is, independent of sizes of arrays. We show that the hardware overhead of the proposed model is a little greater than that of Kung et al.'s model, while the yield of the proposed model is much better than that of Kung et al.'s model.

Euclidean distance transform for binary images on reconfigurable mesh-connected computers

The distance calculation in an image is a basic operation in computer vision, pattern recognition, and robotics. Several parallel algorithms have been proposed for calculating the Euclidean distance transform (EDT). Recently, Chen and Chuang proposed a parallel algorithm for computing the EDT on mesh-connected SIMD computers (1995). For an nxn image, their algorithm runs in O(n) time on a two-dimensional (2-D) nxn mesh-connected processor array. In this paper, we propose a more efficient parallel algorithm for computing the EDT on a reconfigurable mesh model. For the same problem, our algorithm runs in O(log(2)n) time on a 2-D nxn reconfigurable mesh. Since a reconfigurable mesh uses the same amount of VLSI area as a plain mesh of the same size does when implemented in VLSI, our algorithm improves the result in [3] significantly.

A robust and parallel relaxation method based on algebraic splittings

We propose and analyze a new relaxation scheme for the iterative solution of the linear system arising from the finite difference discretization of convection–diffusion problems. For problems that are convection dominated, the (nondimensionalized) diffusion parameter ϵ is usually several orders of magnitude smaller than computationally feasible mesh widths. Thus, it is of practical importance that approximation methods not degrade for small ϵ. We give a relaxation procedure that is proven to converge uniformly in ϵ to the solution of the linear algebraic system (i.e., “robustly”). The procedure requires, at each step, the solution of one 4 × 4 linear system per mesh cell. Each 4 × 4 system can be independently solved, and the result communicated to the neighboring mesh cells. Thus, on a mesh connected processor array, the communication requirements are four local communications per iteration per mesh cell. An example is given, which illustrates the robustness of the new relaxation scheme. © 1999 John Wiley & Sons, Inc. Numer Methods Partial Differential Eq 15: 91–110, 1999

Parallelizable approximate solvers for recursions arising in preconditioning

For the recursions used in the modified incomplete LU preconditioner, namely, the construction of incomplete decomposition, the forward elimination, and the back substitution, parallelizable approximate solvers are introduced. The analysis shows that the solutions of the recursions depend only weakly on their initial conditions, which may be interpreted to indicate that the inexact solution is close, in some sense, to the exact one. The method is based on a domain decomposition approach, suitable for parallel implementations on message-passing architectures. It requires a small number of communication steps per preconditioned iteration, independent of the number of subdomains and the size of the problem. The overlapping subdomains are either squares (suitable for mesh-connected arrays of processors) or defined by the data-flow rule of the recursions (suitable for line-connected arrays of SIMD or vector processors). Numerical examples show that, in both cases, the overhead in the number of preconditioned iterations required for convergence is small in comparison with the speedup gained.

Routing on Meshes with Buses

We consider the problem of routing packets on an \(n\times\cdots\times n\) MIMD mesh-connected array of processors augmented with row and column buses. We give lower bounds and randomized algorithms for the problem of routing k-permutations (where each processor is the source and destination of exactly k packets) on a d-dimensional mesh with buses, which we call the (k,d)-routing problem.

An optimal time multiplication free algorithm for edge detection on a mesh

This paper demonstrates an optimal time, fully systolic algorithm for edge detection on a mesh connected processor array. It uses only inexpensive addition and comparison operations which makes it ideal for fine grained parallelism in VLSI. Given anN xN image in the form of a two-dimensional array of pixels, our algorithm computes the Sobel and Laplacian operators for skimming lines in the image and then generates the Hough array using thresholding. The Hough transforms forM different angles of projection are obtained in a fully systolic manner inO(M+N) time, which is asymptotically optimal. In comparison, a previously published multiplication free algorithm has a time complexity ofO(NM). An implementation of our algorithm on a mesh connected finegrained processor array is discussed, which computes at the rate of approximately 170,000 Hough transforms per second using a 50 MHz clock.

Parallel B-Spline Surface Fitting on Mesh-Connected Computers

The solution of uniform bicubic B-spline curve/surface fitting problem is considered. Based on the matrix perturbation method, this paper first presents a novel approximateO(n/p)-time parallel B-spline curve fitting algorithm for finding the correspondingncontrol points that interpolate thosendata points on a linear array processor withpprocessors, wherep≤n. Givenm×ndata points, we then present anO(mn/(p1p2))-time parallel algorithm for solving the uniform bicubic B-spline surface fitting problem on ap1×p2mesh-connected computer, wherep1≤mandp2≤n. The relative error analyses of our two stable and cost-optimal parallel solvers are also given. When settingp1=mandp2=n, a constant-time parallel solver for B-spline surface fitting can be derived; this time- and cost-optimal result is a direct method, in contrast to the parallel iterative method of Chenget al.(Parallel B-spline surface interpolation on a mesh-connected processor array,J. Parallel Distrib. Comput.24, 2 (1995), 224–229).

Fast deterministic selection on mesh-connected processor arrays

We present a deterministic algorithm for selecting the element of rankk amongN=n2 elements, 1≤k≤N, on ann×n mesh-connected processor array in 1.45n parallel computation steps, using constant-sized queues (for large enoughn). This is a considerable improvement over the best previous deterministic algorithm, which was based upon sorting and requires2n+o(n) steps. Our algorithm can be generalized to solve the problem of selection on higher-dimensional meshes. In particular, we present an algorithm for the three-dimensional mesh which achieves a time bound better than any of the previously known deterministic results.

Fast Deterministic Selection on Mesh-Connected Processor Arrays

Fast Deterministic Selection on Mesh-Connected Processor Arrays