Mesh-based Networks Research Articles

Dynamic multiple multicasts routing and wavelength assignment for realizing modified artificial fish model in mesh-based ONoC

Dynamic multiple multicasts widely exist in several applications of optical network-on-chip. However, there is no good solution for routing and wavelength assignment for multiple multicasts in the mesh-based network. This paper proposes a new routing strategy based on a modified artificial fish swarm algorithm. The modified artificial fish model can support unicast and multicast in the mesh-based network. The routing and wavelength assignment for multiple multicasts can be solved based on this model. Then, we design a layer-based algorithm to assign wavelength for multiple multicasts, which can utilize wavelength and area resources more effectively. Simulation results show that our scheme works better than the other tree-based schemes regarding average communication latency and power consumption. In general, our modified artificial fish swarm algorithm provides a universal platform to study different aspects of routing and wavelength assignment in mesh-based ONoC.

An improved non-local awareness of congestion and load balanced algorithm for the communication of on chip 2D mesh-based network

Due to advancements in multi-core design technology, IC (Integrated Circuits) designers have expanded the single chip multi-core design. A privileged way of communication effectively between these multi-cores is a Network on-chip (NoC). Design of an effective routing algorithm capable of routing data to non-congested paths is the most notable research challenge in NoC, by retrieving congestion information of non-local nodes. This research proposed an improved congestion-aware load balancing routing algorithm. Non-local or distant links congestion awareness is done by propagating congestion information via data packets. By counting number of hops from the source node, in the quadrant of the destination node, an intermediate node has been defined, and after the calculation of the least congested route to the intermediate node, this route is also stored in the data packet for source routing. Furthermore, for load balancing network is partitioned into two areas called high congested area (HCA) and low congested area (LCA). For load balancing, from HCA a node in LCA is selected as output for data packets. Comparison of the proposed algorithm is done in the form of average latency, average throughput, power consumption, and scalability analysis under synthetic traffic patterns. Under simulation experiments, it is shown improvement in an average latency and throughput of the proposed algorithm is 31.28% and 5.28% respectively, than existing.

D3AdvM: A direct 3D adversarial sample attack inside mesh data

Deep learning and neural networks are being extended to geometric design and computation. Recent studies show that deep neural networks are vulnerable to adversarial samples. However, for 3D mesh adversarial samples, the most related studies actually attack the 2D victim networks, in which they have to project 3D objects to 2D images. In this paper, we present D3AdvM (Direct 3D adversary for mesh) to directly generate adversarial samples inside mesh data. Specifically, we propose two adversary generation approaches: vertex-based and edge-based. The first one, 3DVP (3D Vertex-based Perturbation), skillfully searches the optimized vertices positions based on opposite gradient fitness. The second one, KES (Key Edge-based Selection), carefully collapses the key feature edges according to importance of edge feature. Thus, our approaches avoid 3D/2D projections and approximation errors. Also, our approach can reduce the computation overhead. In addition, the proposed D3AdvM can control the number of perturbed vertices for real-world engineering designs and applications. Extensive experiments show that the generated 3D meshes are effective to attack classification networks. Furthermore, we evaluate the transferability, in which D3AdvM can attack both mesh-based networks and point cloud-based networks as victim networks. Our findings could benefit 3D geometry design based on the new generation of artificial intelligence and big data.

UAV-Assisted Multi-path Parallel Routing for mmWave-Based Wireless Networks

The Millimeter Wave (mmWave) spectrum band, with its high bandwidth, will significantly satisfy the need for high data-demand of the next-generation communication networks. However, transmission over the mmWave band suffers from a short communication range due to its high frequency. Such short-range communication can dramatically affect the network connectivity in mesh-based networks, leading to excessive packet loss. To improve the network connectivity and thus the throughput, Unmanned Aerial Vehicles (UAVs)/drones can be utilized as relays. Along with UAVs, multi-path routing is needed to ensure better network reliability through different routes. In this paper, we propose maximizing mmWave-based mesh network connectivity via optimally deploying a number of UAVs/drones and enabling multiple parallel paths at the upper network layers. We model the optimization problem for minimizing end-to-end delay with a minimum number of drones, we further perform a delay analysis for the received queues and obtain the link layer end-to-end delay. The evaluation is first performed through MATLAB and then verified using a realistic scenario in the NS-3 simulator by assuming an IEEE 802.11ad-based wireless mesh network. The results show that the proposed UAV-assisted schemes achieve higher throughput and shorter delay compared to baselines scenario with no deployment of UAVs or single transmissions.

Reliable Weighted Globally Congestion Aware Routing for Network on Chip

With the ability to incorporate hundreds of communicating cores on a single chip, thanks to the continuous shrinkage in sizes, communication became of the utmost importance. Consequently, the reduction of transmission delays became unavoidably necessary. All of which is achieved by means of routing algorithms, responsible for selecting the most appropriate routes for data packets, by avoiding congested regions in the network between any pair of source and destination nodes. In this article, two moderately distinct versions in terms of weight distribution of a minimal, fully adaptive, congestion-aware routing scheme in mesh-based network on chip and its accompanying congestion propagation network, are presented. The algorithm does not rely solely on local congestion information nor on irrelevant global information, and provides somewhat a compromise between locally and globally aware routing. The experimental results showcase the proposed scheme's superiority over state of the art NoC routing algorithms.

Agrinex: A low-cost wireless mesh-based smart irrigation system

Abstract Wireless Sensor Networks in precision agriculture utilize natural resources more efficiently by collecting real-time data on farms to assist agriculture farmers to make intelligent decisions. Using this technology, farmers can effectively use the information to achieve greater yields and earn higher profits. This work presents an alternative to existing monitoring methods in the agricultural lands whilst providing an irrigation mechanism to help in resource conservation efforts by the use of a Wireless Sensor and Actuator Network (WSAN). Agrinex system features a mesh-like configuration of in-field nodes that act both as the sensor for soil moisture, temperature and humidity and actuator on a valve that regulates drip irrigation. The mesh-based network is dynamically design to allow self-reorganization of sensor nodes when changes happen in the network. The resulting Agrinex system is a promising start for a WSAN framework of various applications particularly in agriculture.

Optimization of the Load Balancing Policy for Tiled Many-Core Processors

Tiled many-core processors (i.e., KNL and the TILE-Gx72 processor), on which processing cores are fitted onto a single chip and cores are interconnected via mesh-based networks, are different from the traditional many-core systems. Their operating system (OS) should be optimized to take into account the unique characteristics (for instance, cores are integrated into a single chip) of tiled many-core processors. This is because these characteristics were not taken into consideration when OSes designed for the traditional multicore (many-core) systems were deployed on tiled many-core processors. In this paper, we propose an optimized load balancing policy to improve the performance of multi-threaded applications. Making a thread select an appropriate idle (lightweight) tile (processing core) across all tiles on the single chip rather than a portion of tiles is able to reduce the overhead triggered by the load balancing policy, the penalty of cache misses because of the scheduling and more threads sharing the same tile (processing core), and the contention for memory controllers due to cache misses. The experimental results demonstrate that the optimized load balancing policy can provide up to 2.7× performance improvement on KNL and mitigate the performance degradation to separate extents on the TILE-Gx72 processor.

Analysis of Memory System of Tiled Many-Core Processors

Tiled many-core processors are designed to integrate simple cores onto a single chip to take advantage of software-level parallelism, and these cores are interconnected via mesh-based networks to mitigate overheads such as limited throughput derived from traditional interconnects. As these processors become more prevalent, one unnoticed problem is that it is more likely for operating system (OS) designers to believe that these processors, which have multiple on-chip memory controllers, belong to the non-uniform memory access (NUMA) system. In this paper, we define novel models regarding the differentiation between uniform memory access and NUMA on tiled many-core processors from the perspective of the cache system to facilitate OS designers and application programmers in fully understanding the underlying hardware. Whether or not a tiled many-core processor belongs to the NUMA system, is determined by the cache system rather than how many memory controllers it has. The experimental results together with the novel models are able to explain why the (non-)significant performance difference can be observed on KNL and TILE-Gx72.

Row/Column-First: A Path-based Multicast Algorithm for 2D Mesh-based Network on Chips

Row/Column-First: A Path-based Multicast Algorithm for 2D Mesh-based Network on Chips

An energy-efficient fault-aware core mapping in mesh-based network on chip systems

A fault aware core mapping on Network on Chip (NoC) requires an understanding the calculation of the functional metrics. The functional metrics are Node Average Distance (NAD), Placing unmapped Vertices Region (PVR) and Weighted Communication Energy(WCE). The traditional method of calculating functional metrics are using unmapped cores, distance and weight. However finding the exact values of the functional metrics is not always easy, particularly when busy cores and failed cores are mapped in the middle of available cores. This paper proposes an energy efficient fault aware core mapping algorithm that maps the cores onto the NoC under communication rate constraints to minimize the total communication energy using functional metrics. The simulation results show that proposed mapping algorithm has higher performance over BMAP, PMAP and NMAP algorithm present in literature by 25%, 42%, and 65% under single fault, 30%, 40%, and 60% under two faults and 40%, 44%, and 55% under four faults respectively.

Lattice Graphs for High-Scale Interconnection Topologies

Torus networks of moderate degree have been widely used in the supercomputer industry. Tori are superb when used for executing applications that require near-neighbor communications. Nevertheless, they are not so good when dealing with global communications. Hence, typical 3D implementations have evolved to 5D networks, among other reasons, to reduce network distances. Most of these big systems are mixed-radix tori, which are not the best option for minimizing distances and efficiently using network resources. This paper is focused on improving the topological properties of this kind of networks. By using integral matrices to deal with Cayley graphs over Abelian groups, we have been able to propose and analyze a family of high-dimensional mesh-based interconnection networks. As they are built over $n$ -dimensional grids that induce a regular tiling of space, these topologies have been denoted lattice graphs . Higher dimensional networks can be composed over these graphs by means of a lift operation, which is also introduced in the paper. Easy network partitioning and minimal routing algorithm are also provided for these topologies based on this new network operation. Later we focus on cubic crystal lattices for modeling symmetric 3D networks and to show how lattice graphs can help in the design of twisted interconnection networks. In all cases, the networks obtained are better, in topological terms, than their standard tori counterparts. Finally, some practical issues such as implementability and preliminary performance evaluations have been addressed at the end of this work.

FT-Z-OE: A Fault Tolerant and Low Overhead Routing Algorithm on TSV-based 3D Network on Chip Links

dimensional Network-On-Chips (3D NOC) are the most efficient communication structures for complex multi-processor System-On-Chips (SOC). Such structures utilize short vertical interconnects in 3D ICs together with scalability of NOC to improve performance of communications in SOCs. By scaling trends in 3D integration, probability of fault occurrence increases that leads to low yield of links, especially TSV-based vertical links in 3D NOCs. In this paper, FT-Z-OE (Fault Tolerant Z Odd-Even) routing, a distributed routing to tolerate permanent faults on vertical links of 3D NOCs is proposed. FT-Z-OE is designed to have low overhead because of no need to any routing table or global information of faults in the network. The proposed routing is evaluated using a cycle-accurate network simulator and compared to planar-adaptive routing for a 3D mesh-based network. It is shown that FT-Z-OE significantly outperforms planar-adaptive in the terms of latency and throughput under synthetic traffic patterns.

Accelerating Unpopular Channel through Federation

Nowadays, peer-to-peer technology has provided users with cheap and powerful communicating facilities. However, P2P streaming system faces two challenges. Firstly, how to improve the poor Quality-of-Experience (QoE) in unpopular channel? Secondly, how to select peers to contribute their resources for assisting the unpopular channel in order to balance channel resources? This paper presents a cross-channel federation model to address these problems. The key idea is to identify a set of stable nodes in popular channel to assist the unpopular channel. These stable nodes, together with nodes in unpopular channel, are organized as mesh-based network, which facilitates the unpopular channel to enlarge the channel group and promote peer stability. This cross-channel federation model is evaluated through simulations. The results demonstrate its efficiency.

Dynamic characteristics of mesh–based network control system under optimal resource circumstances

Network control system (NCS) has been presenting significance in industry and automation by supporting usability and convenience. However, for insufficiency for diversity of infrastructure and scalability, it has limitations in the field of flexibility for network architecture compared to the wireless mobile network. Hence, there shows the pressing need for tackling the existing network control system with control flow by wireless mesh network (WMN) with strong flexibility effectively. Consequently, for each control system, its stability is one of the prerequisites and criteria. In this paper, a novel optimization model was developed for planning the optimal resource utilization of wireless mesh network (WMN), and then the dynamic characteristics of mesh-based network control system are analyzed and discussed.

Contribution-Guided Peer Selection for Reliable Peer-to-Peer Video Streaming Over Mesh Networks

This paper proposes a sender-driven peer selection scheme, including estimation of packet loss propagation, evaluation of peers' contributions, and peer selection based on child-peers' contributions, for mesh-based peer-to-peer (P2P) video streaming systems. The proposed packet loss propagation model takes into account the link packet drop rate, peer dynamics, and forward error correction protection to capture the heterogeneous packet loss behavior of individual substreams transmitted over a mesh network. The evaluation of candidate peers' contributions is modeled through Markov random fields to significantly reduce complexity. Simulation results demonstrate that our peer selection scheme significantly mitigates packet loss in a mesh-based P2P network, compared to other state-of-the-art schemes.

HACS: A novel cost aware paradigm promising fault tolerance on mesh-based network on chip architecture

As the integration of transistors on today’s embedded systems scales, so does the shrinking size of chips, thus making the on-chip communication a challenging issue on the VLSI designs. However, network on chips have emerged as a promising technology to tackle the on-chip communication constraints. Likewise, the reliability issues have become the salient problem, since regarding to the inaccessible failures of on-chip elements, there must be some levels of embedded fault tolerance techniques. In this paper, an innovated technique is revealed providing fault tolerance in the on-chip networks over single and multiple permanent switch failures. The experimental results achieved by the system simulation in SystemC TLM environment are validated with the mathematical analysis modeled for system reliability that we extend in this paper, which demonstrate the extensive reliability enhancement of this paradigm. Along with the system improvement, silicon area overhead is calculated utilizing VHDL low level simulation and Orion synthesis.

Performance-Aware Hybrid Algorithm for Mapping IPs onto Mesh-Based Network on Chip

Network on Chip (NoC) is proposed as a new intra-chip communication infrastructure. In current NoC design, one related problem is mapping IP cores onto NoC architectures. In this paper, we propose a performance-aware hybrid algorithm (PHA) for mesh-based NoC to optimize performance indexes such as latency, energy consumption and maximal link bandwidth. The PHA is a hybrid algorithm, which integrates the advantages of Greedy Algorithm, Genetic Algorithm and Simulated Annealing Algorithm. In the PHA, there are three features. First, it generates a fine initial population efficiently in a greedy swap way. Second, effective global parallel search is implemented by genetic operations such as crossover and mutation, which are implemented with adaptive probabilities according to the diversity of population. Third, probabilistic acceptance of a worse solution using simulated annealing method greatly improves the performance of local search. Compared with several previous mapping algorithms such as MOGA and TGA, simulation results show that our algorithm enhances the performance by 30.7%, 23.1% and 25.2% in energy consumption, latency and maximal link bandwidth respectively. Moreover, simulation results demonstrate that our PHA approach has the highest convergence speed among the three algorithms. These results show that our proposed mapping algorithm is more effective and efficient.

A Dual-Port Access Structure of 3D Mesh-Based NoC

Since the length of wires between different layers, even between the top and bottom layers, is acceptably small in 3D mesh-based NoC (three-Dimensional mesh-based Network on Chip), a structure in which an IP (Intelligence Property) core in a certain layer directly connected to a proper router in another layer may efficiently decrease the average latency of messages and increase the maximum throughput. With this idea, in the paper, we introduce a dual-port access structure, in which each IP core except that in the bottom layer is connected to two routers in two adjacent layers, and, in particular, the IP core in the bottom layer can be directly connected to the proper router in the top layer. Furthermore, we derive the close form expression of the average number of hops of messages and also give the quantitative analysis of the performance when the dual-port access structure is used. All the analytical results reveal that the average number of hops is reduced and the system performance is improved, including a decrease of average latency and an increase of maximum throughput. Finally, the simulation results confirm our theoretical analysis and show the advantage of the proposed dual-port access structure with a relatively small increment of area overhead.

Two-level evolutionary approach to the survivable mesh-based transport network topological design

The complete topology design problem of survivable mesh-based transport networks is to address simultaneously design of network topology, working path routing, and spare capacity allocation based on span-restoration. Each constituent problem in the complete design problem could be formulated as an Integer Programming (IP) and is proved to be $\mathcal{NP}$ -hard. Due to a large amount of decision variables and constraints involved in the IP formulation, to solve the problem directly by exact algorithms (e.g. branch-and-bound) would be impractical if not impossible. In this paper, we present a two-level evolutionary approach to address the complete topology design problem. In the low-level, two parameterized greedy heuristics are developed to jointly construct feasible solutions (i.e., closed graph topologies satisfying all the mesh-based network survivable constraints) of the complete problem. Unlike existing "zoom-in"-based heuristics in which subsets of the constraints are considered, the proposed heuristics take all constraints into account. An estimation of distribution algorithm works on the top of the heuristics to tune the control parameters. As a result, optimal solution to the considered problem is more likely to be constructed from the heuristics with the optimal control parameters. The proposed algorithm is evaluated experimentally in comparison with the latest heuristics based on the IP software CPLEX, and the "zoom-in"-based approach on 28 test networks problems. The experimental results demonstrate that the proposed algorithm is more effective in finding high-quality topologies than the IP-based heuristic algorithm in 21 out of 28 test instances with much less computational costs, and performs significantly better than the "zoom-in"-based approach in 19 instances with the same computational costs.

S-Mesh: a Mesh-based on-chip network with separation of control and transmission

The current network-on-chip (NoC) topology cannot predict subsequent switch node status promptly. Switch nodes have to perform various functions such as routing decision, data forwarding, packet buffering, congestion control and properties of an NoC system. Therefore, these make switch architecture far more complex. This article puts forward a separating on-chip network architecture based on Mesh (S-Mesh). S-Mesh is an on-chip network that separates routing decision flow from the switches. It consists of two types of networks: datapath network (DN) and control network (CN). The CN establishes data paths for data transferring in DN. Meanwhile, the CN also transfers instructions between different resources. This property makes switch architecture simple, and eliminates conflicts in network interface units between the resource and switch. Compared with 2D-Mesh, Torus Mesh, Fat-tree and Butterfly, the average packet latency in S-Mesh is the shortest when the packet length is more than 53 B. Compared with 2D-Mesh, the areas savings of S-Mesh is about 3%–7%, and the power dissipation is decreased by approximate 2%.