Parallel Memristor Research Articles

Flame intensity sensor based on the resistive and memory properties of spintronic memristor

A flame intensity sensor based on the resistive and memory properties of spintronic memristor is proposed. The sensor circuit mainly consists of the infrared radiation conversion module, the spintronic memristor array module, the amplifier and current limiting resistor. In order to verify the designed sensor, experiments were conducted under no flame, constant and gradually increasing flame combustion temperature, and the effects of the number of parallel memristor arrays, current limiting resistors, measurement distance and radiation wavelength on the sensor were analyzed. The experiments results demonstrate that the designed flame intensity sensor based on the resistive and memory properties of spintronic memristor can quantitatively measure the flame intensity. When the temperature change rate of flame combustion is 1℃/s, the sensor measurement range is 0–3.1 mW/cm2, and the sensitivity is 4.516kΩ/(mW/cm2). The rate of change in the resistance of the spintronic memristor array may be affected by the changes in flame intensity, but this does not affect the measurement range of the sensor.

BETTER: Bayesian-Based Training and Lightweight Transfer Architecture for Reliable and High-Speed Memristor Neural Network Deployment

Deep learning models implemented using memristors show high scalability and high energy efficiency, promising a compact and efficient computing architecture for resourceconstrained edge computing applications. These technologies integrate both data storage and computation simultaneously in a highly parallel memristor crossbar array architecture. However, the significant variations arising from the inherent physical randomness of memristors lead to a large performance degradation of deep learning models. The challenges of extensive energy costs and transfer time for deployment to maintain performance are faced. In this paper, for the first time, we propose a unified architecture that consists of a Bayesian-based training method and a lightweight transfer scheme. The proposed architecture can tackle the robustness, energy and time consumption issues caused by memristor variations. Our experimental results show that our architecture can double the speed and energy efficiency of deploying deep learning models.

Memristive Fast-Canny Operation for Edge Detection

Memristor-based in- memory computing paradigm is a promising path for edge detection in image preprocessing on end devices that reduces the computational pressure on data centers. However, the implementation of the well-performing Canny operator for edge detection faces challenges in terms of computational time and area overhead when mapped to memristor arrays. In this work, we proposed an efficient memristive one-step implementation of a fast-Canny operator. Exploiting the associative property of multiplication, the conventional Canny operator consisting of Gaussian and Sobel operators is converted into a fast-Canny operator and mapped to an array of nine parallel memristors. Then, the output currents are the final pixels of the edge image. To verify the feasibility of the method, successful edge detection with high accuracy (OIS = 0.73) is achieved in device-aware simulation under device variation (<50%) and image noise ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sigma $ </tex-math></inline-formula> = 6%). Additionally, the implementation of the fast-Canny operator on memristor arrays can reduce the processing time by half and save the area of buffer compared to the prior two-convolution Canny operation. Our work suggests that the memristive fast-Canny operator could be a promising and efficient hardware solution for edge detection at the network edge.

Parallel bi-memristor hyperchaotic map with extreme multistability

Discrete memristors can be used to construct chaotic and hyperchaotic mapping models by self-feedback or coupling method, but these constructed maps do not have multistability or extreme multistability. Towards this end, by connecting two identical discrete memristors in parallel, this paper presents a novel parallel bi-memristor hyperchaotic map using the self-feedback method. This map has a plane fixed point set and its stability is entirely determined by memristor initial states. The control parameters-reliant hyperchaotic behaviors and the initial states-reliant coexisting behaviors are disclosed using several numerical methods. Complex dynamical behaviors closely relative to memristor and non-memristor initial states are demonstrated, indicating the occurrence of extreme multistability. Besides, a digital hardware platform is developed and the experimental results are captured to well validate the numerical ones. Consequently, the presented parallel bi-memristor map can display hyperchaotic dynamics and it is flexible to show extreme multistability.

Understanding composite negative differential resistance in niobium oxide memristors

Volatile memristors, or threshold switching devices, exhibit a diverse range of negative differential resistance (NDR) characteristics under current-controlled operation and understanding the origin of these responses is of great importance for exploring their potential as nano-scale oscillators for neuromorphic computing. Here we use a previously developed two-zone, parallel memristor model to undertake a systematic analysis of NDR modes in two-terminal metal-oxide-metal devices. The model assumes that the non-uniform current distribution associated with filamentary conduction can be represented by a high current density core and a lower current-density shell where the core is assumed to have a memristive response due to Poole-Frenkel conduction and the shell is represented by either a fixed resistor or a second memristive region. A detailed analysis of the electrical circuits is undertaken using a lumped-element thermal model of the core-shell structure, and is shown to reproduce continuous and discontinuous NDR responses, as well as more complex compound behaviour. Finally, an interesting double-window oscillation behaviour is predicted and experimentally verified for a device with compound NDR behaviour. These results clearly identify the origin of different NDR responses and provide a strong basis for designing devices with complex NDR characteristics.

Efficient Parallel Multi‐Bit Logic‐in‐Memory Based on a Ultrafast Ferroelectric Tunnel Junction Memristor

AbstractMemristive logic‐in‐memory (LIM) is an attractive candidate for in‐memory computing and thus would overcome some of the issues concerning the von Neumann bottleneck, which has been intensively investigated. Here, a multi‐bit and functionally complete LIM strategy is designed to efficiently perform multi logical functions in parallel. This strategy is experimentally demonstrated by a multi‐bit ferroelectric tunnel junction (FTJ) memristor with a sub‐nanosecond operation speed which is nearly two orders of magnitude faster than the previous memristive LIM. Using the four resistance states (2‐bit) of only a single FTJ memristor cell, two logical computations are successfully performed in parallel, and the 16 complete Boolean logic functions are implemented within only two steps. In addition, the multi‐encoding schemes are proposed to further improve the efficiency and flexibility of parallel logical computations. Accordingly, the 1‐bit binary full adder can be implemented using as less as three parallel memristors by only performing five steps, and on this basis the N‐bit full adder can also be realized. These results provide a highly efficient LIM approach, which could be a promising candidate for future computing architecture.

Memristive Circuit Design of Five-Person Voter Based on Memristor Ratioed Logic

Conventional CMOS-based logic circuits are approaching their limits when it comes to speed and energy consumption, so the development of new electronic components becomes critical. Memristor is a nano-structured special electronic device with the advantages of simple structure, low power consumption and easy integration. This invention supplys a new method for developing complex logic circuits. This article mainly presents the design of a five-person voter circuit. The OR/AND logic can be accomplished by varying the polarity of two parallel memristors. On the basis of the two logic circuits, adder and comparator are constructed. Further, based on the adder and comparator, a five-person voter is implemented. The correctness and rationality of the five-person voter based on MRL are confirmed via logistical analysis and simulation. Compared with the traditional logic circuits, the logic circuit designed in this paper has advantages in area cost. The realization of the five-person voter circuit further proves that the logic circuit based on memristor can be cascaded. The research results are expected to build more complex circuits, which may provide a reference for the design of other practical circuits.

Memory analysis for memristors and memristive recurrent neural networks

Traditional recurrent neural networks are composed of capacitors, inductors, resistors, and operational amplifiers. Memristive neural networks are constructed by replacing resistors with memristors. This paper focuses on the memory analysis, i.e., the initial value computation, of memristors. Firstly, we present the memory analysis for a single memristor based on memristors&#x02BC mathematical models with linear and nonlinear drift. Secondly, we present the memory analysis for two memristors in series and parallel. Thirdly, we point out the difference between traditional neural networks and those that are memristive. Based on the current and voltage relationship of memristors, we use mathematical analysis and SPICE simulations to demonstrate the validity of our methods.

Memristor Based Quantization Circuit Design for ADCs

As the fourth fundamental circuit element, memristor will introduce great change to the conventional electronic circuits. Quantization circuit of ADC (Analog to Digital Converter) is one of the promising circuits applications that can be improved by memristors. In this manuscript, a parallel memristors quantization circuit design is proposed. The circuit with such implementation scheme is able to achieve high rate and high precision quantization conversion. Compared with other memristor based quantization circuit, it shows good performance in power dissipation and circuit size.

Single‐Cell Stateful Logic Using a Dual‐Bit Memristor

By combining the functions of Boolean gates and non‐volatile memory, stateful logic may enable significant savings in time and energy for computational processes that can be performed directly in main memory and for data analyses in edge environments. A simple reduction to practice this concept is demonstrated by Borghetti et al. in 2010 via a material implication logic gate comprising two parallel memristors and a conditional write operation. Here, a single physical dual‐bit memristor, possessing both bipolar and unipolar resistance switching characteristics and utilizing their operations, is demonstrated. This device responds to a conditional write to perform not only implication but multiple other logic functions when configured with a series resistor and addressed with a specific voltage pulse. The simple circuit structure of this dual‐bit memristor allows compact sequential logic cascading along the time dimension without a concern of multiple cell accessing related issues. The sequence of implementing a full‐adder is also discussed.

Learning mechanisms in memristor networks based on GaN nanomembranes

We demonstrate experimentally that single crystalline GaN nanomembranes arranged in simple networks exhibit learning mechanisms such as habituation and dishabituation followed by storage of the response to a certain electrical stimulus. These artificial learning mechanisms are analogous to non-associative learning processes which are identical in simple animals and human beings. We found that the learning time depends on the number of GaN membranes in parallel, and this parameter decreases by 30% when three memristors are connected in parallel compared to the learning time of a single memristor. Moreover, an increased number of parallel memristors reduces the eventual asymmetry in the temporal response of the circuit at positive and negative step voltages.

Multiple coexisting attractors of the serial–parallel memristor-based chaotic system and its adaptive generalized synchronization

The nonlinear circuit with serial–parallel memristors shows special internal characteristics and external performance, which indicates that the serial–parallel memristors can greatly change the dynamic characteristics of the nonlinear system. Mathematical model of the system is established to analyze the influence of the serial–parallel memristors on the dynamical behaviors with the change of system parameters, and then the basin of attraction is used to exhibit the coexisting multiple attractors with different initial conditions and the serial–parallel memristors, which can reveal that the serial–parallel flux-controlled or charge-controlled memristors have different effects on the generation of chaos and multistability phenomenon. Moreover, the hardware description of memristor-based system through FPGA is realized by Verilog language and the experimental results are observed from digital oscilloscope. Finally, based on the Lyapunov stability theory and adaptive control law, a nonlinear controller is designed to achieve the adaptive generalized synchronization between five memristor-based chaotic systems, and numerical results of the adaptive generalized synchronization are presented to prove the correctness and effectiveness of the proposed method.

A simple inductor-free memristive circuit with three line equilibria

In this work, a novel inductor-free fourth-order two-memristor-based chaotic circuit is proposed. This new circuit is developed from a current feedback op amp-based sinusoidal oscillator through replacing a linear resistor with a memristor and adding another different parallel memristor to the cascaded memristor–capacitor net. The proposed circuit can perform chaotic, fixed point, and period behaviors. The most striking feature is that this system has three line equilibria and exhibits the extreme multistability phenomenon of the coexisting infinitely many attractors. Specially, amplitude death behavior and transient transition behavior can also be found in the proposed system. By using standard nonlinear analysis tools including system dissipation, equilibrium point stability, phase portrait, Lyapunov exponent spectrum, and bifurcation diagram, the fundamental dynamical characteristics of the circuit are investigated in detail. Moreover, a MULTISIM circuit is designed to verify the numerical simulations.

Simplest memristive system

Many potential applications are developed towards the new memristive systems. However, these systems are too complicated to produce the real elements, the simplifications of memristive systems are interesting to our future applications. The simplest memristive system is modeled to make the real elements more practical in the electric circuit, which may confirm three fingerprints of memristor. These results verified by Matlab and Multisim simulations indicate that the proposed memristive system produces a pinched hysteresis loop for a periodic input. The voltage-current relation-ships are investigated for two parallel memristor circuits-a parallel memristor and capacitor circuit, and a parallel memristor and inductor circuit. It may be convenient and useful for our future application in the circuit.

Coexisting infinitely many attractors in active band-pass filter-based memristive circuit

This paper presents an inductor-free memristive circuit, which is implemented by linearly coupling an active band-pass filter (BPF) with a parallel memristor and capacitor filter. Mathematical model is established, and numerical simulations are performed. The results verified by hardware experiments show that the active BPF-based memristive circuit exhibits the dynamical behaviors of point, period, chaos, and period-doubling bifurcation route. Most important of all, the newly proposed memristive circuit has a line equilibrium and its stability closely relies on memristor initial condition, which results in the emergence of extreme multistability. Stability distribution related to memristor initial condition is numerically estimated and the coexistence of infinitely many attractors is intuitively captured by numerical simulations and PSIM circuit simulations.

Multi Memristors in Series, Parallel and Series-Parallel Connection

Multi Memristors in Series, Parallel and Series-Parallel Connection

Leveraging Stochastic Memristor Devices in Neuromorphic Hardware Systems

As the fourth basic circuit element, memristor has a unique synapse-alike feature which demonstrates great potentials in neuromorphic circuit design. However, a large gap exists between the theoretical memristor characteristics and the actual device behavior. For example, though the continuous changing in resistance state is expected in neuromorphic circuit design, it is difficult to maintain arbitrary intermediate state. In addition, the stochastic switching behaviors have been widely observed in nano-scale memristor devices. In this work, we first developed a stochastic behavior model in order to facilitate the investigation on memristor-based hardware implementation. Our modeling was based on the statistical analysis of experimental data of ${\rm TiO }_{2}$ device. By leveraging the stochastic behavior of memristors, a random number generator was proposed. We also presented a macro cell design composed of multiple parallel connecting memristors which can be successfully used in implementing the weight storage unit and the stochastic neuron. The designs of these fundamental components provide a feasible solution in memristor-based hardware implementation of neural networks.

Memristive behaviour of high‐impedance faults

In this reported work, the analogy between parallel electrical arcs and memristors is extended to high-impedance faults such as carbonised paths and circuit openings. First, it is demonstrated that the conductance from the high-impedance Mayr model behaves like a particular memductance sensitive to the integral of the squared current. Then, the current–voltage plot confirms the memristive behaviour of high-impedance faults, both by simulation and with experimental results.

Improving Tolerance to Variations in Memristor-Based Applications Using Parallel Memristors

Memristors are being explored for a wide variety of applications such as neuromorphic computing, memory and digital logic. However, they suffer from process variations like any other nanodevice, which in turn impacts their applicability. The effect of process variations, specifically variation in thickness, is highly non-linear on memristors; the effect is greater near the lower memristance region (near M <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$_{\rm on}$</tex><mathgraphic fileref="rajendran-ieq1-2308189.gif" graphicformat="GIF"/></formula> ) than in the higher memristance region (near M <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$_{\rm off}$</tex> <mathgraphic fileref="rajendran-ieq2-2308189.gif" graphicformat="GIF"/></formula> ). Due to this non-linear effect, many applications do not use the lower memristance values. Consequently, the application's functionality and performance is affected. In this work, we propose a technique called parallel memristors. In this technique, instead of using a single memristor, the application uses several memristors connected in parallel. Each memristor in this parallel structure is programmed to a higher memristance value to tolerate variations. Since many memristors are connected in parallel, the effective memristance value can be near the M <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$_{\rm on}$ </tex><mathgraphic fileref="rajendran-ieq3-2308189.gif" graphicformat="GIF"/></formula> value, thereby achieving high-speed operation. We evaluate the parallel memristor technique in two different applications—memristor-based threshold logic and memristor-based memory. We also perform various optimizations to tradeoff between variation tolerance, power, delay, and area.

A compound memristive synapse model for statistical learning through STDP in spiking neural networks.

Memristors have recently emerged as promising circuit elements to mimic the function of biological synapses in neuromorphic computing. The fabrication of reliable nanoscale memristive synapses, that feature continuous conductance changes based on the timing of pre- and postsynaptic spikes, has however turned out to be challenging. In this article, we propose an alternative approach, the compound memristive synapse, that circumvents this problem by the use of memristors with binary memristive states. A compound memristive synapse employs multiple bistable memristors in parallel to jointly form one synapse, thereby providing a spectrum of synaptic efficacies. We investigate the computational implications of synaptic plasticity in the compound synapse by integrating the recently observed phenomenon of stochastic filament formation into an abstract model of stochastic switching. Using this abstract model, we first show how standard pulsing schemes give rise to spike-timing dependent plasticity (STDP) with a stabilizing weight dependence in compound synapses. In a next step, we study unsupervised learning with compound synapses in networks of spiking neurons organized in a winner-take-all architecture. Our theoretical analysis reveals that compound-synapse STDP implements generalized Expectation-Maximization in the spiking network. Specifically, the emergent synapse configuration represents the most salient features of the input distribution in a Mixture-of-Gaussians generative model. Furthermore, the network's spike response to spiking input streams approximates a well-defined Bayesian posterior distribution. We show in computer simulations how such networks learn to represent high-dimensional distributions over images of handwritten digits with high fidelity even in presence of substantial device variations and under severe noise conditions. Therefore, the compound memristive synapse may provide a synaptic design principle for future neuromorphic architectures.