Memristor Emulator Research Articles

A High-Quality and Space-Efficient Design for Memristor Emulation

The paper presents a new design for a compact memristor emulator that uses a single active component and a grounded capacitor. This design incorporates a current backward transconductance amplifier as the active element, enabling the emulation of both grounded and floating memristors in incremental and decremental modes. The paper provides an in-depth analysis of the circuit, covering ideal, non-ideal, and parasitic factors. The theoretical performance of the memristor emulator is confirmed through post-layout simulations with 180 nm generic process design kit (gpdk) technology, demonstrating its capability to operate at low voltages (±1 V) with minimal power consumption. Additionally, the emulator shows strong performance under variations in process, voltage, and temperature (PVT) and functions effectively at a frequency of 2 MHz. Experimental validation using commercially available integrated circuits further supports the proposed design.

A fully floating memristor emulator with long-term memory

In this paper, we proposed a fully floating memristor emulator with long-term memory characteristics. The circuit comprises operational amplifiers and an analog switch. Switching between incremental and decremental modes is easily achieved by changing the polarity of the input signal. The key feature of the emulator is its long-term memory, made possible by the switch and voltage follower. The correctness of the derived formula is verified using Matlab, and the emulator's pinched hysteresis loop and non-volatility are assessed using LTspice. Additionally, an experimental platform was constructed for physical testing, with the physical results showing consistency with the simulations. Finally, the proposed emulator was applied to a simple read-write circuit, demonstrating its practical applicability.

Second generation current conveyor based capacitorless floating memristor emulator

Second generation current conveyor based capacitorless floating memristor emulator

Grounded and floating memristor emulator employing ICCTA: decremental or incremental operation

ABSTRACT This article describes floating and grounded memristor emulator built with an Inverting Current Conveyor Transconductance Amplifier (ICCTA). One ICCTA, one capacitor, and three resistors are used to implement the charge controlled floating memristor emulator. In contrast, a flux controlled grounded memristor emulator consists of one ICCTA, one resistor, and one capacitor. Both presented circuits do not incorporate complex circuits such as analog multiplier circuits, passive inductors, and analog to digital converter circuits in their implementation, which is advantageous in terms of circuit realisation. The designed circuits may be operated in incremental as well as decremental configurations by appropriate setting of MOS switches. In addition, PVT (process, voltage, and temperature) analysis of the proposed memristor is also included. Furthermore, the non-ideal explanation of the proposed circuits is mathematically examined. The proposed emulators are simulated in SPICE simulator using 180 nm technology. Meminductor circuit and memristor-based low pass filter are used to validate the effectiveness of the designed circuits.

A novel resistorless memristor emulator circuit and its implementation of chaotic Jerk system

This work presents a novel resistorless memristor emulator circuit designed in both grounded and floating configurations. The grounded memristor consists of a Current-Controlled Current Conveyor Transconductance Amplifier (CC-CCTA) and a capacitor. On the other hand, a floating memristor includes a CC-CCTA and a capacitor, along with an additional Operational Transconductance Amplifier (OTA). These proposed emulators are electronically controllable owing to the internal structures of active elements. Theoretical analysis and simulation results have been obtained for the proposed designs. Simulation results have been conducted utilizing the LTspice program and TSMC 180 nm technology has been used for internal structures. In these results, the effects of the changing capacitor values, different frequencies, electronic tunability, reactions to temperature change, and pulse response have been investigated. Subsequently, a chaotic Jerk circuit has been implemented incorporating the proposed memristor emulator. The chaotic behavior of the floating memristor has been investigated using the LTspice simulation software.

A Memristor Emulator Consisting of One MOSFET and Two Diodes

A Memristor Emulator Consisting of One MOSFET and Two Diodes

Floating/grounded charged controlled memristor emulator using DVCCTA

Floating/grounded charged controlled memristor emulator using DVCCTA

Efficient and lightweight in-memory computing architecture for hardware security

This paper introduces an innovative solution for improving the efficiency and speed of the Advanced Encryption Standard (AES) based cryptographic algorithm. The approach leverages in-memory computing (IMC) and is versatile for application across a broad spectrum of IoT applications, including robotic autonomous vehicles and various other scenarios. To achieve this goal, memristor (MR) designs are proposed to emulate the arithmetic operations required for different phases of the AES algorithm, enabling efficient in-memory processing. The key contributions of this work include; 1) The development of a 4 bit-MR state element for implementing different arithmetic operations in an AES hardware prototype; 2) The creation of a pipeline AES design for massive parallelism and MR integration compatibility; and 3) The hardware implementation of the AES-IMC based architecture using the MR emulator. The results show that AES-IMC performs better than existing architectures in terms of higher throughput and energy efficiency. Compared to conventional AES hardware, AES-IMC achieves a 30% power enhancement with comparable throughput. Additionally, when compared to state-of-the-art AES-based NVM engines, AES-IMC demonstrates comparable power dissipation and a 62% increase in throughput. The IMC architecture enables cost-effective real-time deployment of AES, leading to high-performance computing. By leveraging the power of in-memory computing, this system is able to provide improved computational efficiency and faster processing speeds, making it a promising solution for a wide range of applications in the field of autonomous driving and robotics. The potential benefits of this system include improved safety and security of unmanned devices, as well as enhanced performance and cost-effectiveness in a variety of computing environments.

A simple passive floating memristor emulator circuit

In this research article, we propose a passive two-terminal floating memristor emulator circuit (MEC). The proposed MEC consists of two NMOS transistors, one PMOS transistor and one capacitor. The MEC has a simple circuit topology structure and is more advantageous for integration, which has a chip area of only 218.04 μm2. The circuit can operate without additional bias and performs well in the high frequency environment at 50 MHz. Some of the memristor’s characteristics, such as pinched hysteresis loop and non-volatility, are verified using the Cadence Virtuoso environment with 0.18 μm SMIC technology. The MEC has also been successfully proven to be effective and reliable through the temperature variation, process corner variation and Monte Carlo analysis. In addition, we built a circuit for experimental testing by using the CD4007s to verify the theoretical and simulated results. Finally, the proposed memristor emulator circuit is applied to logic circuits.

A new CMOS-memristor based D-latch with fewer components

In order to study the function of memristor in new devices, a new D-latch is proposed in this paper, which is composed of threshold-type memristor, transistor, resistor and NOT gate. The proposed D-latch uses fewer components than previous. The transistor controls the on-off of the signal, and NOT gate changes the resistance state of memristor. The voltage divider circuit composed of memristor and resistor realizes the latching function. To verify the D-latch, a modified threshold-type memristor emulator circuit (MEC) is proposed. The proposed MEC is composed of operational amplifier, multiplier and second-generation current conveyor. The MEC is a voltage-controlled memristor that can realize floating input. The equivalent resistance of MEC has two kinds of high resistance and low resistance, which change with the polarity of the voltage. The MEC has the characteristic of non-volatility, that is, the resistance state of the circuit remains when the input signal is withdrawn. Through simulation analysis and experimental verification, both circuits have good performance.

Integrable emulation of a floating incremental/decremental inverse memristor for memristor bandwidth extension

Abstract The article explores the compact emulation of the inverse memristor through a circuit-based approach. It introduces a floating emulator architecture that incorporates a dual output OTA (Operation Transconductance Amplifier) and DVCC (Differential Voltage Current Conveyor), along with two grounded passive elements, to achieve the emulation of an inverse memristor. The utilization of grounded resistance allows for tunability over the realized behaviour. A key contribution of this research is the novel application of the inverse memristor to extend the operating frequency range of any memristor emulator circuit. Validation of the proposed emulator circuit, in both incremental and decremental modes, along with its application, is conducted using PSPICE-generated simulation results in the 0.18 µm TSMC CMOS technology. Additionally, an inverse memristor emulator configuration employing the IC LM13700 is presented, and its functionality is tested through a breadboard implementation.

A Microcontroller-Controlled Optocoupler-Based Memristor Emulator and Its Usage in a Low-Pass Filter

A Microcontroller-Controlled Optocoupler-Based Memristor Emulator and Its Usage in a Low-Pass Filter

New DTMOS Based High Frequency Memristor Emulator and Its Nonlinear Applications

New DTMOS Based High Frequency Memristor Emulator and Its Nonlinear Applications

Implementation of tunable OTA-based memristor emulator circuit with chaotic behavior

Implementation of tunable OTA-based memristor emulator circuit with chaotic behavior

A floating memristor emulator for analog and digital applications with experimental results

A floating memristor emulator for analog and digital applications with experimental results

A general discrete memristor emulator based on Taylor expansion for the reconfigurable FPGA implementation and its application

A general discrete memristor emulator based on Taylor expansion for the reconfigurable FPGA implementation and its application

A gate‐tunable memristor emulator for motion detection

SummaryWith its low power consumption and small size, the memristor has shown great potential for improving data storage density and computing efficiency. Compared to the dual‐port memristor, greater attention should be paid to researching gate‐tunable memristor for image processing to improve the processing speed and reduce hardware resource consumption. Developing gate‐tunable memristor emulators is highly attractive given the immaturity of current fabrication of the gate‐tunable memristor. This work proposes a digital gate‐tunable memristor emulator based on Raspberry Pi, which addresses the non‐reconfigurability and inflexibility issues of the analog emulators. The proposed emulator can match the behavior of different memristor devices by regulating the gate voltage parameter. Additionally, it can operate at a maximum frequency of 500 MHz. To test the functionality of the proposed emulator, a digital implementation of the memristive circuit for motion detection is designed and verified experimentally. Experiments demonstrate that when moving object detection is performed on a 640 × 350 pixel video stream, low power consumption of 53 mW and a delay of 3.52 μs can be achieved.

A general configuration for nonlinear circuit employing current-controlled nonlinearity: Application in Chua’s circuit

In this paper, a general configuration for nonlinear circuit employing current-controlled nonlinearity is proposed, which has a simple topology and only contains three linear energy storage components, one nonlinear element, and one multi-port network that can be made by linear resistor. Under this configuration, we design two new five-element chaotic circuits including the first third-order one employing a current-controlled anti-parallel connection diode pair and the second fourth-order one employing a current-controlled memristor emulator. The analyses show that the third-order chaotic circuit is dual to the canonical Chua’s circuit, and the extended fourth-order one can be regarded as a dual canonical memristive Chua’s circuit. The basic analyses including the model description, equilibrium point and stability are presented. Several rich dynamical properties of the two chaotic circuits are investigated using numerical simulations and certified by both Pspice circuit simulations and analog circuit measurements.

Tunable floating and grounded memristor emulator Model

ABSTRACT A Differential Difference Current Conveyor Transconductance Amplifier (DDCCTA) based resistor tunable memristor emulator has been proposed in this work. The emulator can be used in both grounded and floating circumstances. The proposed design incorporates only one active block along with few passive components. Moreover, the circuit can operate in both incremental and decremental modes, by simply changing the input ports. The circuit demonstrates all the characteristics of an ideal memristor up to 6 MHz. The proposed model has been simulated using TSMC 0.18m process parameter and occupies an area of 51 × 42.5 m2 chip-area, excluding capacitor. The circuit’s reliability has been verified by studying non-ideal, non-volatile, Monte-Carlo, process corner variations analysis. The circuit applicability has been tested through series/parallel combinations. To validate the experimental demonstration, AD844AN and CA3080 have been used to make a prototype, which shows good agreement with theoretical and simulation results.

VLSI Implementation of Hybrid Memristor Based Logic Gates

Practical memristors have gained attention from researchers and scientists due to their potential use in a variety of electronic circuits and devices. In our paper, a hybrid Memristor-CMOS (MeMOS) logic circuit was designed and its transient response was analyzed. This circuit, which uses a N-type metal oxide semiconductor (NMOS), and P-type metal oxide semiconductor (PMOS) transistors, Operational amplifiers (OPAMPs), resistors, capacitors and multipliers replicate memristor characteristics. To facilitate the development of real memristor circuit applications, a memristor emulator is utilized for breadboard experiments. This emulator can be connected in a variety of configurations, including serial, parallel, or a combination of both, with identical or opposite polarities. By simply changing the connection, the emulator can be switched between decremental and incremental configurations. In our paper, we implemented AND logic using MeMOS. PSpice simulation of the proposed emulator have been demonstrated for TiO2 memristor model.