Memristor Emulator Circuit Research Articles

A novel resistorless memristor emulator circuit and its implementation of chaotic Jerk system

This work presents a novel resistorless memristor emulator circuit designed in both grounded and floating configurations. The grounded memristor consists of a Current-Controlled Current Conveyor Transconductance Amplifier (CC-CCTA) and a capacitor. On the other hand, a floating memristor includes a CC-CCTA and a capacitor, along with an additional Operational Transconductance Amplifier (OTA). These proposed emulators are electronically controllable owing to the internal structures of active elements. Theoretical analysis and simulation results have been obtained for the proposed designs. Simulation results have been conducted utilizing the LTspice program and TSMC 180 nm technology has been used for internal structures. In these results, the effects of the changing capacitor values, different frequencies, electronic tunability, reactions to temperature change, and pulse response have been investigated. Subsequently, a chaotic Jerk circuit has been implemented incorporating the proposed memristor emulator. The chaotic behavior of the floating memristor has been investigated using the LTspice simulation software.

A simple passive floating memristor emulator circuit

In this research article, we propose a passive two-terminal floating memristor emulator circuit (MEC). The proposed MEC consists of two NMOS transistors, one PMOS transistor and one capacitor. The MEC has a simple circuit topology structure and is more advantageous for integration, which has a chip area of only 218.04 μm2. The circuit can operate without additional bias and performs well in the high frequency environment at 50 MHz. Some of the memristor’s characteristics, such as pinched hysteresis loop and non-volatility, are verified using the Cadence Virtuoso environment with 0.18 μm SMIC technology. The MEC has also been successfully proven to be effective and reliable through the temperature variation, process corner variation and Monte Carlo analysis. In addition, we built a circuit for experimental testing by using the CD4007s to verify the theoretical and simulated results. Finally, the proposed memristor emulator circuit is applied to logic circuits.

A new CMOS-memristor based D-latch with fewer components

In order to study the function of memristor in new devices, a new D-latch is proposed in this paper, which is composed of threshold-type memristor, transistor, resistor and NOT gate. The proposed D-latch uses fewer components than previous. The transistor controls the on-off of the signal, and NOT gate changes the resistance state of memristor. The voltage divider circuit composed of memristor and resistor realizes the latching function. To verify the D-latch, a modified threshold-type memristor emulator circuit (MEC) is proposed. The proposed MEC is composed of operational amplifier, multiplier and second-generation current conveyor. The MEC is a voltage-controlled memristor that can realize floating input. The equivalent resistance of MEC has two kinds of high resistance and low resistance, which change with the polarity of the voltage. The MEC has the characteristic of non-volatility, that is, the resistance state of the circuit remains when the input signal is withdrawn. Through simulation analysis and experimental verification, both circuits have good performance.

Integrable emulation of a floating incremental/decremental inverse memristor for memristor bandwidth extension

Abstract The article explores the compact emulation of the inverse memristor through a circuit-based approach. It introduces a floating emulator architecture that incorporates a dual output OTA (Operation Transconductance Amplifier) and DVCC (Differential Voltage Current Conveyor), along with two grounded passive elements, to achieve the emulation of an inverse memristor. The utilization of grounded resistance allows for tunability over the realized behaviour. A key contribution of this research is the novel application of the inverse memristor to extend the operating frequency range of any memristor emulator circuit. Validation of the proposed emulator circuit, in both incremental and decremental modes, along with its application, is conducted using PSPICE-generated simulation results in the 0.18 µm TSMC CMOS technology. Additionally, an inverse memristor emulator configuration employing the IC LM13700 is presented, and its functionality is tested through a breadboard implementation.

Implementation of tunable OTA-based memristor emulator circuit with chaotic behavior

Implementation of tunable OTA-based memristor emulator circuit with chaotic behavior

A new passive non-ideal floating memristor emulator circuit

A new passive non-ideal floating memristor emulator circuit (MEC) is proposed in this paper. The MEC is only composed of four transistors, two resistors, and one capacitor. The circuit needs no external bias. Transistors control the direction of current conduction, changing the resistance state of the circuit, while capacitors make the circuit exhibit hysteresis characteristics. The V-I curve of the circuit exhibits the Type-II memristive hysteresis loop. The validity of the theoretical study is demonstrated by simulation results using the Cadence design environment with 0.18 μm SMIC technology. Additionally, the proposed MEC has been tested in the Schmitt trigger circuit and amplitude demodulation circuit, proving that it can be used in practical applications.

Tunable memristor employing only four transistors

This paper introduces a flux-controlled memristor emulator circuit which can be controlled by electronically both fix and variable parts of memristance. Here, the fix part symbolizes the average memristance value, and the variable part refers to the changing part around the fixed part. Another advantage of the presented circuit is that it is composed of only four transistors and one grounded capacitor which provides memory to the circuit. For this reason, it can be said that the circuit is very simple, compatible with both VLSI implementation, and suitable for implementation on breadboards using discrete circuit elements. The proposed circuit can be operated at MHz frequency ranges and a strong pinched hysteresis loop can be seen at these frequencies. Finally, all simulation and experimental results are compatible with previous studies.

CMOS-Based Memristor Emulator Circuits for Low-Power Edge-Computing Applications

In this paper, an optimized memristor emulator circuit is designed, by using nine MOSFET transistors and a ground capacitor. Our area- and power-optimized emulator circuit can be used for basic data storage and processing at the monitoring edge, in real-time applications. The memristor shows a nonlinear voltage–current relationship, but no multiplier circuit provides the memristor’s nonlinear characteristics. As a result, the proposed memristor emulator has a very low chip area. The memristor circuit is designed in LTSpice, using 16 nm and 45 nm CMOS technology parameters, and the operating voltage is ±0.9 V. In this research, the theoretical derivations are validated using the simulated results of the memristor emulator circuit using different frequencies, capacitors, and input voltages in SPICE simulations.

Research progress and applications of memristor emulator circuits

From the perspective of circuit theoretical integrity, it can be predicted that there is a fourth passive basic element, and this missing circuit element is named as memristor. Memristor is a two-terminal device whose value depends on the history of the magnetic flux or charge flowing through it. As a fourth basic element, it is considered a promising device in many analog and digital applications. However, the cost and difficulty of making nanodevices limit the commercialization of memristor. To better study memristor, researchers have proposed the use of circuits composed of different components to simulate memristor characteristics, also known as memristor emulator circuits. This paper presents the current research status of memristor emulator circuits, and analyses the design ideas, circuit composition, advantages and disadvantages of emulator circuits implemented by different schemes, then introduces the application of some emulators in real circuits.

Simplification of Chua corsage memristor and hardware implementation of its neuron circuit

<sec>The Chua corsage memristor (CCM) is a voltage-controlled locally-active memristor, which has complex dynamic behaviors and potential applications in the field of neuromorphic computing. According to the DC <i>V</i>-<i>I</i> plot, the CCM can be classified as two-lobe, four-lobe, and six-lobe type. By analyzing their non-volatility and local activity, it is found that they have the same locally-active region and a common stable equilibrium. The mathematical models of the three CCMs are simplified based on the mechanism of neuromorphic behavior, namely, local activity. After the model simplification, the absolute value operation disappears, but the locally-active domain remains unchanged. For the simplified CCM, its small-signal equivalent circuit at the locally-active operating point is established, which is consistent with CCMs before being simplified. Hence, the model simplification does not change the small-signal characteristics of CCMs.</sec><sec>To further investigate the application of voltage-controlled locally-active memristor in modeling the neuromorphic behavior of neurons, the simplified CCM model is used to connect a capacitor and an inductor to construct a third-order neuron circuit. By applying theoretical analysis methods such as local activity, edge of chaos, and Lyapunov exponents, we predict the parameter domains where different neuromorphic behaviors are generated. The distribution of neuromorphic behaviors is described on a dynamic map determined by the parameters of applied voltage <i>V</i><sub>D</sub> and external inductance <i>L</i>. When the memristor is biased in the locally-active region, the system response changes among resting state, periodic spiking oscillation, and chaotic behaviors.</sec><sec>Finally, according to the simplified CCM mathematical model, the corresponding emulator circuit is designed by using three operational amplifiers, two multipliers, a current conveyor, and several resistors and capacitors. Based on the presented memristor emulator circuit, the hardware implementation of the neuron circuit is given. The experimental results verify the correctness and feasibility of the simplified CCM emulator circuit, and show that the simplified CCM-based neuron circuit can produce a variety of neuromorphic behaviors, including resting state, periodic spiking, chaotic state, bimodal response, periodic oscillation, all-or-nothing phenomenon, and spike clustering phenomenon. We expect that this work is helpful in further studying the mechanism of neuromorphic behaviors of the neuron circuit and its practical applications.</sec>

New FTFN-Based Tunable Memristor Emulator Circuit and its Mutation to Meminductor and Memcapacitor Emulators

For the first time, a new memristor emulator structure using a single four-terminal floating nullor (FTFN) and a transconductance stage has been presented with tunable circuit configuration. Along with that the circuit requires only a single grounded capacitance and two external MOS transistors to realize both incremental and decremental types of memductance functions. The use of the FTFN block has been demonstrated for the first time to build such a compact memristor emulator, which fully utilizes the employed circuit resources. The wide-band operating frequency range (1 kHz–3 MHz) is another attractive feature of the proposed emulator. Moreover, the mutation of the proposed memristor emulator into meminductor and memcapacitor emulators is also presented by the mutators based on FTFN. All the presented circuits have been tested by performing simulations using PSPICE with 0.18-[Formula: see text]m CMOS technology. The generated simulation results clearly show the ideal nonvolatile nature of the realized memristor, which has also been utilized in an op-amp-based circuit designed to exhibit associative learning phenomena. The proposed FTFN-based memristor has been implemented using commercially available ICs, LM13700, and AD844, and the generated PHL plot is discussed.

FinFET-based non-linear analog signal processing modules

FinFETs exhibit far superior transistor characteristics (better gate control and a lower sub-threshold slope) as compared to the standard MOSFETs, this paper first employs the FinFETs in the design of an operational transconductance amplifier (OTA). The FinFET-based OTA offers a linearity range and - 3 dB bandwidth of ± 300 mV and 631.81 GHz, respectively. Further, the non-linear applications of the proposed OTA, viz. voltage divider, memristor emulator, and a memristive neuron, are presented. The proposed analog voltage divider circuit contains one OTA and two external N-FinFETs. The maximum bandwidth obtained for the voltage divider is 217.54 GHz. The memristor emulator contains one OTA, two external N-FinFETs, and one grounded capacitor. The proposed emulator circuit follows the signature characteristics of the actual memristor device. The frequency response characteristics of the proposed emulator circuit depict a bandwidth of 22.7 GHz. The proposed emulator shows non-volatile as well as electronically tunable features. Next, Monte-Carlo simulation analysis has been performed on the proposed circuits in order to observe the effects of statistical variation in different operating conditions. Furthermore, we propose a FinFET-based passive memristive neuron model using a memristor emulator circuit. The proposed neuron circuit follows a tangent hyperbolic activation function. All the proposed circuits are suitable for monolithic implementation. The proposed circuits are verified using 20 nm FinFET technology. The simulation results obtained using HSPICE agree well with the theoretical analysis.

Current-controlled grounded memristor emulator circuit based on analog multiplier

This paper proposes a current-controlled grounded memristor emulator circuit based on single four-quadrant analog multiplier, a resistor and a capacitor. The behavioral model of the proposed emulator circuit is analyzed, highlighting its characteristics. Experimental results are given to investigate its ability for different operating frequencies and they are in accordance with theoretical analysis and simulation results. By using a divider circuit, the memristance variation in the time domain is obtained. It is observed that the pinched hysteresis loop at high frequency loses symmetry due in part to the shift that introduces a multiplication of sinusoidal signals.

Design of the Threshold-Controllable Memristor Emulator Based on NDR Characteristics.

Due to the high manufacturing cost of memristors, an equivalent emulator has been employed as one of the mainstream approaches of memristor research. A threshold-type memristor emulator based on negative differential resistance (NDR) characteristics is proposed, with the core part being the R-HBT network composed of transistors. The advantage of the NDR-based memristor emulator is the controllable threshold, where the state of the memristor can be changed by setting the control voltage, which makes the memristor circuit design more flexible. The operation frequency of the memristor emulator is about 250 kHz. The experimental results prove the feasibility and correctness of the threshold-controllable memristor emulator circuit.

Charge-controlled grounded memristor emulator circuits based on Arbel-Goldminz cell with variable switching behaviour

Charge-controlled grounded memristor emulator circuits based on Arbel-Goldminz cell with variable switching behaviour

Electronically Tunable Flux-Controlled Resistorless Memristor Emulator

This article demonstrates a voltage differencing inverting buffered amplifier (VDIBA)-based resistorless flux-controlled memristor emulator circuit with tunability. Two VDIBA blocks serve as active components, and a grounded capacitor serving as a passive part. The proposed emulator design is devoid of multipliers and resistors through effective utilization of port relationships. Including tunability, the suggested emulator functions in both incremental and decremental modes. It accurately depicts the attributes of an ideal memristor up to 12.7 MHz and consumes a total power of 1.34 mW. The mathematical analysis is substantiated through Cadence simulation in 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$</tex-math> </inline-formula> m Taiwan Semiconductor Manufacturing Company (TSMC) technology with the supply voltage of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\pm$</tex-math> </inline-formula> 1 V. Nonideal, single/parallel, Monte-Carlo sampling and corner analysis were conducted to confirm circuit resilience. The nonvolatile nature of the presented emulator model has also been included. A breadboard prototype incorporating the ICs CA3080 and LT1193 are built to conduct an experimental demonstration. The experimental findings were consistent with the theoretical expectations and simulation results.

A simple time-delay memristor and its application in 2D HR neuron model

Since the concept of memristor was proposed, the memristor, as the fourth-generation electronic component, has attracted great attention from researchers. Memristors can be used not only for nonvolatile memory but also to mimic the behavior of nervous system. The inherent nonlinearity of memristor makes it valuable in nonlinear circuits. Since it is still difficult to realize the commercial application of memristors at present, designing suitable memristor models can play a guiding role in practical application. This work proposes a novel memristor model with a time-delay state variable. The proposed memristor cannot only generate pinched hysteresis loop under periodic signal excitation, but also can generate chaotic current or even hyperchaotic current under DC voltage. The nonlinear dynamics of the proposed time-delay memristor are studied by phase portraits, bifurcation diagram and Lyapunov exponents. Furthermore, the proposed memristor is used in the HR neuron model to study neuronal electrical activities with electromagnetic induction. Multiple firing patterns of the memristive neuron can be generated such as periodic, bursting and chaotic. Finally, the memristor emulator circuit and the HR neuron model circuit are designed and simulated by Pspice.

Simple flux‐controlled grounded memristor emulator circuits based on current follower

Simple flux‐controlled grounded memristor emulator circuits based on current follower

New area efficient memristor realizations

In this paper, new active-only memristor emulator circuits based on only one active element and one single transistor are proposed. These circuits use intrinsic capacitors of the MOS transistors without using any external passive components. These types of circuits have some important advantages over the integrated circuit, such as low occupied chip area and electronic tuning capability. However, memristor emulator circuits suffer from limited operation frequency range. To address this issue, a new modification technique used to extend circuits’ operating frequency range is introduced. Furthermore, the proposed memristor emulators can also be used to implement basic filtering functions. The main nonidealities are studied and proper operations of these circuits are provided via Spectre Simulation results in 0.18 ​μm Cadence design tool.

Resistorless Memristor Emulator Using CFTA and Its Experimental Verification

This article presents a novel charge-controlled memristor emulator circuit. The proposed memristor emulator utilizes a single Current Follower Transconductance Amplifier (CFTA) as an active current mode analog building block and a grounded capacitor as a passive element. The circuit presented follows all the fingerprints of an ideal memristor. It operates in both incremental as well as decremental mode. The functional performance of the emulator circuit is verified at different operating frequencies and performs well up to 9 MHz . The theoretical and non-ideal analyses are verified for the proposed emulator. Moreover, Monte Carlo sampling and non-volatility analysis are performed to investigate the robustness of the emulator circuit. The functionality of the proposed model has been verified through PSPICE simulation using TSMC 0.18 $\mu m$ CMOS technology at the supply voltage of $\pm 1.2~V$ . The experimental confirmation of the presented circuit is also performed by building a breadboard micromodel using ICs CA3080 and AD844AN. Memristor based Chua’s circuit model is included as one of its applications.