Memory Utilization Research Articles

Enhancing Memory Utilization For On-Device Training of TinyML Models Utilizing Enhanced Grey Wolf Optimization Pushing State-of-the-Art Limits - TinyWolf

Enhancing Memory Utilization For On-Device Training of TinyML Models Utilizing Enhanced Grey Wolf Optimization Pushing State-of-the-Art Limits - TinyWolf

A Blockchain-Based Architecture for Securing Industrial IoTs Data in Electric Smart Grid

There are numerous internet-connected devices attached to the industrial process through recent communication technologies, which enable machine-to-machine communication and the sharing of sensitive data through a new technology called the industrial internet of things (IIoTs). Most of the suggested security mechanisms are vulnerable to several cybersecurity threats due to their reliance on cloud-based services, external trusted authorities, and centralized architectures; they have high computation and communication costs, low performance, and are exposed to a single authority of failure and bottleneck. Blockchain technology (BC) is widely adopted in the industrial sector for its valuable features in terms of decentralization, security, and scalability. In our work, we propose a decentralized, scalable, lightweight, trusted and secure private network based on blockchain technology/smart contracts for the overhead circuit breaker of the electrical power grid of the Al-Kufa/Iraq power plant as an industrial application. The proposed scheme offers a double layer of data encryption, device authentication, scalability, high performance, low power consumption, and improves the industry’s operations; provides efficient access control to the sensitive data generated by circuit breaker sensors and helps reduce power wastage. We also address data aggregation operations, which are considered challenging in electric power smart grids. We utilize a multi-chain proof of rapid authentication (McPoRA) as a consensus mechanism, which helps to enhance the computational performance and effectively improve the latency. The advanced reduced instruction set computer (RISC) machines ARM Cortex-M33 microcontroller adopted in our work, is characterized by ultra-low power consumption and high performance, as well as efficiency in terms of real-time cryptographic algorithms such as the elliptic curve digital signature algorithm (ECDSA). This improves the computational execution, increases the implementation speed of the asymmetric cryptographic algorithm and provides data integrity and device authenticity at the perceptual layer. Our experimental results show that the proposed scheme achieves excellent performance, data security, real-time data processing, low power consumption (70.880 mW), and very low memory utilization (2.03% read-only memory (RAM) and 0.9% flash memory) and execution time (0.7424 s) for the cryptographic algorithm. This enables autonomous network reconfiguration on-demand and real-time data processing.

Split: A Hash-based Memory Optimization Method for Zero-Knowledge Succinct Non-Interactive Argument of Knowledge (zk-SNARK)

Zero-Knowledge Succinct Non-Interactive Argument of Knowledge (zk-SNARK) is a practical zero-knowledge proof system for Rank-1 Constraint Satisfaction (R1CS), enabling privacy preservation and addressing the previous scalability concerns on zero-knowledge proofs. Existing constructions of zk-SNARKs require huge memory overhead to generate proofs in that the size of the zk-SNARK circuit can be large even for a very simple use case, which limits the applications for regular resource-constrained users. To reduce the memory utilization of zk-SNARKs, this paper presents a hash-based method “Split”. Concretely, Split intends to partition the zk-SNARK circuits so that components can be processed sequentially while ensuring strong security properties leveraging hash circuits. As a zk-SNARK circuit is partitioned, obsolete variables are no longer preserved in the memory. We further propose an enhanced Split as <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$n$</tex-math></inline-formula> -Split, which leads to better optimization by properly choosing multiple splits. Our experimental results validate the effectiveness and efficiency of Split in conserving memory usage for resource-constrained provers as long as the circuit can be partitioned to a Good Split, indicating that via Split zk-SNARKs can be brought one step closer to practical applications.

PDP-CNN: A Deep Learning Model for Post-Hurricane Reconnaissance of Electricity Infrastructure on Resource-Constrained Embedded Systems at the Edge

Unmanned aerial vehicles (UAVs) equipped with cameras have provided new capabilities for the reconnaissance of disaster-stricken areas. Deep learning-based computer vision algorithms enable the analysis of the captured images and the detection of damage to the built environment. If such analyses are conducted onboard in UAVs, they will provide real-time actionable information that is critical for the accelerated restoration of systems. However, conventional deep learning algorithms are computationally demanding. Moreover, the deployment of deep learning models with a large number of parameters in scenarios that require low-latency inference is prohibitive. To address this fundamental gap, we develop an efficient deep learning-based computer vision model of power distribution poles (PDPs) damage detection that is capable of onboard deployment in UAVs. Specifically, we propose a lightweight convolutional neural network (CNN) architecture called PDP-CNN that embodies multiscale feature operations and anchor-less object detection. This model is applied to a dedicated image database from a post-hurricane reconnaissance in PDPs. Results of extensive experiments show that PDP-CNN is capable of achieving high throughput, competitive accuracy, and efficient memory utilization on power-constrained embedded systems.

Container Profiler: Profiling resource utilization of containerized big data pipelines.

This article presents the Container Profiler, a software tool that measures and records the resource usage of any containerized task. Our tool profiles the CPU, memory, disk, and network utilization of containerized tasks collecting over 60 Linux operating system metrics at the virtual machine, container, and process levels. The Container Profiler supports performing time-series profiling at a configurable sampling interval to enable continuous monitoring of the resources consumed by containerized tasks and pipelines. To investigate the utility of the Container Profiler, we profile the resource utilization requirements of a multistage bioinformatics analytical pipeline (RNA sequencing using unique molecular identifiers). We examine profiling metrics to assess patterns of CPU, disk, and network resource utilization across the different stages of the pipeline. We also quantify the profiling overhead of our Container Profiler tool to assess the impact of profiling a running pipeline with different levels of profiling granularity, verifying that impacts are negligible. The Container Profiler provides a useful tool that can be used to continuously monitor the resource consumption of long and complex containerized applications that run locally or on the cloud. This can help identify bottlenecks where more resources are needed to improve performance.

GPU accelerated grouped magnetic resonance fingerprinting using clustering techniques

Magnetic Resonance Fingerprinting (MRF) is a new quantitative technique of Magnetic Resonance Imaging (MRI). Conventionally, MRF requires sequential correlation of the acquired MRF signals with all the signals of (a large sized) MRF dictionary. This is a computationally intensive matching process and is a major challenge in MRF image reconstruction. This paper introduces the use of clustering techniques (to reduce the effective size of MRF dictionary) by splitting MRF dictionary into multiple small sized MRF dictionary components called MRF signal groups. The proposed method has been further optimized for parallel processing to reduce the computation time of MRF pattern matching. A multi-core GPU based parallel framework has been developed that enables the MRF algorithm to process multiple MRF signals simultaneously. Experiments have been performed on human head and phantom datasets. The results show that the proposed method accelerates the conventional MRF (MATLAB based) reconstruction time up to 25× with single-core CPU implementation, 300× with multi- core CPU implementation and 1035× with the proposed multi-core GPU based framework by keeping the SNR of the resulting images in a clinically acceptable range. Furthermore, experimental results show that the memory requirements of MRF dictionary get significantly reduced (due to efficient memory utilization) in the proposed method.

ODSearch

Mobile and wearable technologies have promised significant changes to the healthcare industry. Although cutting-edge communication and cloud-based technologies have allowed for these upgrades, their implementation and popularization in low-income countries have been challenging. We propose ODSearch, an On-device Search framework equipped with a natural language interface for mobile and wearable devices. To implement search, ODSearch employs compression and Bloom filter, it provides near real-time search query responses without network dependency. In particular, the Bloom filter reduces the temporal scope of the search and compression reduces the size of the data to be searched. Our experiments were conducted on a mobile phone and smartwatch. We compared ODSearch with current state-of-the-art search mechanisms, and it outperformed them on average by 53 times in execution time, 26 times in energy usage, and 2.3% in memory utilization.

PIRAP: Chaotic Fuzzy Encryption (CFE) Technique and Greedy Chemical Reaction Optimization (GCRO) Algorithm-Based Secured Mobi-Cloud Framework

This paper uses the chaotic fuzzy encryption (CFE) technique and a greedy chemical reaction optimization algorithm based on mobile cloud computing to protect data from any assault. Mobile users who use protected mobile cloud computing (Mobi-Cloud) must trust the cloud service provider to keep the data sent from their mobile devices safe when mobile users express strong reservations about storing personal information in the public cloud. The Greedy Chemical Reaction Optimization (G-CRO) algorithm reduces critical limitations by determining the offloading end with motion at run time, i.e. the task’s operating time, CPU usage, memory utilization, and energy usage. The experimental results show that the proposed method performs better in terms of file uploading time, file downloading time, memory usage in file uploading, memory usage in file downloading, encryption time, decryption time, memory usage on file encryption, memory usage on file decryption, security levels, and key generation time. Compared to the Proxy Re-Encryption (PRE) algorithm, the suggested method consumes less time for key creation (26.04).

ExtendedSketch+: Super host identification and network host trust evaluation with memory efficiency and high accuracy

Host cardinality estimation is one crucial task in network traffic measurement. Super host is the host that exhibits anomalies in host cardinality and it is usually related to network abnormal events. Therefore, accurate host cardinality estimation is the premise of super host identification and it can be used to measure the trust degree of a network. Sketches have been widely used in super host identification. However, expanding network scale and increasing link rate bring challenges to the efficiency and accuracy of sketch-based super host identification. The size of the counters in most sketches requires a trade-off between memory resources and accuracy. To meet the need of measuring high cardinalities, large size counters are applied, which leads to memory waste in monitoring low cardinality hosts. On the other hand, most sketches have high computational overhead when tracking superhosts, resulting in inefficiency. In order to address these issues, we propose a novel memory efficient and reversible sketch, named ExtendedSketch+, to provide accurate host cardinality estimation with the purpose of super host identification and network host trust evaluation. ExtendedSketch+ achieves both high memory utilization efficiency and high accuracy, in addition to high super host identification efficiency. It applies extensible counters to record unbalanced host cardinality distribution, by adaptively expanding the counters with the increase of cardinality. It adopts a lossless traffic information transfer strategy during counter extension to ensure the accuracy of cardinality estimation. It can directly tracks the host with the highest cardinality in each bucket, which greatly improves the identification efficiency of super hosts. Based on accurate cardinality estimation of ExtendedSketch+, we can further accurately evaluate host trust degree. We theoretically analyze ExtendedSketch+ with regard to its space and time complexities and estimation accuracy. We conduct performance evaluation based on real network traffic traces. Experimental results show that ExtendedSketch+ performs better than state-of-the-art sketches regarding super host identification and provides accurate host trust evaluation.

Welding defects classification through a Convolutional Neural Network

This letter presents a Convolutional Neural Network (CNN), named WelDeNet, customized to classify welding defects, such as lack of penetration (LP), cracks (CR), porosity (PO) and no defect (ND), by inspecting digitalized radiographic images. A new dataset that collects 24,407 images representing welding defects is also presented. WelDeNet consists of 14 cascaded convolutional layers and achieves a test accuracy of 99.5 %. When hardware implemented within the Raspberry Pi 3B + board, WelDeNet exhibits an inference time of only 134 ms, with CPU and memory utilizations of just 51 % and 47 MB, thus offering a promising solution easy-to-integrate in a real industrial environment.

Exploiting HBM on FPGAs for Data Processing

Field Programmable Gate Arrays (FPGAs) are increasingly being used in data centers and the cloud due to their potential to accelerate certain workloads as well as for their architectural flexibility, since they can be used as accelerators, smart-NICs, or stand-alone processors. To meet the challenges posed by these new use cases, FPGAs are quickly evolving in terms of their capabilities and organization. The utilization of High Bandwidth Memory (HBM) in FPGA devices is one recent example of such a trend. In this article, we study the potential of FPGAs equipped with HBM from a data analytics perspective. We consider three workloads common in analytics-oriented databases and implement them on an FPGA showing in which cases they benefit from HBM: range selection, hash join, and stochastic gradient descent for linear model training. We integrate our designs into a columnar database (MonetDB) and show the trade-offs arising from the integration related to data movement and partitioning. We consider two possible configurations of the HBM, using a single and a dual clock version design. With the right design, FPGA+HBM-based solutions are able to surpass the highest performance provided by either a two-socket POWER9 1 system or a 14-core Xeon 2 E5 by up to 5.9× (range selection), 18.3× (hash join), and 6.1× (SGD).

Autonomous image background removal for accurate and efficient close-range photogrammetry

Close-range photogrammetry can be used to reconstruct dense point clouds of an object with very high surface coverage, making it useful for manufacturing metrology tasks such as part inspection and validation. However, compared to competing techniques, data processing times can be slow. In this paper we present a method to autonomously remove the background from the images within a photogrammetric dataset. We show that using masked images directly in the reconstruction results in much lower data processing times, with lower memory utilisation. Furthermore, we show that the point density on the object surface is increased while the number of superfluous background points is reduced. Finally, a set of reconstruction results are compared to a set of tactile coordinate measurements. Reconstructions with the background removed are shown to have a standard deviation in the point to mesh distance of up to 30 µm lower than if the background is not removed. This improvement in standard deviation is likely due to the static background, relative to the object on the rotation stage, causing triangulation errors when points are detected and matched on this background data. The proposed approach is shown to be robust over several example artefacts and can, therefore, be implemented to improve the measurement efficiency and measurement results of photogrammetry coordinate measurement systems.

Validation of Parallel Distributed Adaptive Signal Processing (PDASP) Framework through Processing-Inefficient Low-Cost Platforms

The computational complexity of the multiple-input and multiple-output (MIMO) based least square algorithm is very high and it cannot be run on processing-inefficient low-cost platforms. To overcome complexity-related problems, a parallel distributed adaptive signal processing (PDASP) architecture is proposed, which is a distributed framework used to efficiently run the adaptive filtering algorithms having high computational cost. In this paper, a communication load-balancing procedure is introduced to validate the PDASP architecture using low-cost wireless sensor nodes. The PDASP architecture with the implementation of a multiple-input multiple-output (MIMO) based Recursive Least Square (RLS) algorithm is deployed on the processing-inefficient low-cost wireless sensor nodes to validate the performance of the PDASP architecture in terms of computational cost, processing time, and memory utilization. Furthermore, the processing time and memory utilization provided by the PDASP architecture are compared with sequentially operated RLS-based MIMO channel estimator on 2×2, 3×3, and 4×4 MIMO communication systems. The measurement results show that the sequentially operated MIMO RLS algorithm based on 3×3 and 4×4 MIMO communication systems is unable to work on a single unit; however, these MIMO systems can efficiently be run on the PDASP architecture with reduced memory utilization and processing time.

VCSR: An Efficient GPU Memory-Aware Sparse Format

The Sparse Matrix-Vector Multiplication (SpMV) kernel is used in a broad class of linear algebra computations. SpMV computations result in a performance bottleneck in many high performance applications, so optimizing SpMV performance is paramount. While implementing this kernel on a GPU can potentially boost performance significantly, current GPU libraries either provide modest performance gains or are burdened with high sparse format conversion overhead. In this paper we introduce the Vertical Compressed Sparse Row (VCSR) format, a novel memory-aware format that out-performs previous proposed formats on a GPU. We first motivate the design of our baseline VCSR format and then step through a series of enhancements that further improve VCSR's memory efficiency (VCSR-MEM) and performance (VCSR-INTRLV), while also considering conversion overhead. VCSR attempts to produce a high degree of thread-level parallelism and memory utilization by exploiting knowledge of GPU memory microarchitecture. VCSR can reduce the number of global memory transactions significantly, an issue not addressed by most other sparse formats. In addition, VCSR provides a novel reordering mechanism. It minimizes the size of the compressed matrix, handles both regular/irregular sparse matrices, and can be customized based on matrix size. VCSR also minimizes conversion overhead, as compared to full or partial row reordering. Our methodology is highly configurable and can be optimized for any sparse matrix. We have evaluated the VCSR format for the SpMV kernel when run on two different NVIDIA GPUs, the Kepler K40 and the Volta V100. We compare VCSR with NVIDIA's cuSPARSE library (the HYB format), a state-of-the-art sparse library. We also compare against other state-of-the-art CSR-based formats, including CSR5, merge-base SpMV and HOLA. We evaluate the benefits of VCSR over the entire University of Florida's SuiteSparse dataset collection. The VCSR-baseline format achieves an average speedup ranging from <inline-formula><tex-math notation="LaTeX">$1.10\times$</tex-math></inline-formula> to <inline-formula><tex-math notation="LaTeX">$1.39\times$</tex-math></inline-formula> when compared to the performance of the four state-of-the-art formats on an NVIDIA V100. While the VCSR-MEM format can save a significant amount of memory space, it is a bit slower than our VCSR-baseline. VCSR-INTRLV performs much better than the VCSR-baseline, and even when including the conversion overhead, achieves an average speedup of <inline-formula><tex-math notation="LaTeX">$1.08\times$</tex-math></inline-formula> as compared to HOLA (the best performing format among the prior schemes).

Optimized Page Fault Handling During RDMA

Remote Direct Memory Access (RDMA) is widely used in High-Performance Computing (HPC) while making inroads in datacenters and accelerators. State-of-the-art RDMA engines typically do not endure page faults, therefore users are forced to pin their buffers, which complicates the programming model, limits the memory utilization, and moves the pressure to the Network Interface Cards (NICs). In this article we introduce a mechanism for handling dynamic page faults during RDMA, named PART, suitable for emerging processors that also integrate the Network Interface. PART leverages the IOMMU already present in modern processors for translations. PART avoids the pinning overheads, allows any buffer to be used for communication, and enables overlapping page fault handling with serving subsequent RDMA transfers. We implement and optimize PART for a cluster of ARMv8 cores with tightly-coupled network interfaces. Handling a minor page-fault of a small transfer at the destination takes approximately 38 <inline-formula><tex-math notation="LaTeX">$\mu$</tex-math></inline-formula> secs, while there is no performance degradation when running three full MPI applications in 16 nodes and 64 cores. Detailed breakdown uncovers the hardware and system software components of this overhead and was used to further optimize the system. A 4MB RDMA transfer performs 1.46x better over pinning.

OSM: Off-Chip Shared Memory for GPUs

Graphics Processing Units (GPUs) employ a shared memory, a software-managed cache for programmers, in each streaming multiprocessor to accelerate data sharing among the threads in a thread block. Although 60% of the shared memory space is underutilized, on average, there are some workloads that demand higher shared memory capacities. Therefore, improving shared memory utilization while satisfying the needs of shared memory intensive workloads is challenging. We make a key observation that the lifetime of each shared memory address is significantly shorter than the execution time of a thread block. In this paper, we first propose Off-Chip Shared Memory (OSM) that allocates shared memory space in the off-chip memory, and accelerates accesses to it via a small on-chip cache. Using an 8 KB cache for shared memory addresses, OSM provides almost the same performance as the baseline GPU that uses 96 KB on-chip shared memory. OSM improves GPU performance in two ways. First, it allocates higher shared memory capacities in the off-chip memory, and improves thread-level parallelism (TLP). Second, it designs a unified cache for shared memory and global address spaces, providing more caching space for global memory address space even for the workloads with high shared memory utilization. Our experimental results show an average 21% and 18% IPC improvement compared to the baseline and the state-of-the-art architectures.

Comparison of Memory usage between REST API in Javascript and Golang

Various mobile devices have limited memory, thus it must be used as effectively as possible. As a result, apps that will operate on mobile devices must take memory usage efficiency into account. The REST API, which is typically used to connect several applications that utilize different types of technology so that the applications can be connected, is one sort of technology that is currently commonly used to construct mobile applications. Javascript and Golang are the types of technology used to create the REST API. Undoubtedly, each of these technologies offers a unique performance. Research that can give a broad overview of the variations in the impact of memory resource utilization between Javascript and Golang is therefore required. In this work, two REST APIs are created using Javascript and Golang by researchers utilizing an experimental quantitative methodology. Following that, the memory utilization of the two REST APIs was evaluated using the exact same two types of datasets obtained from console.cloud.google.com. There was a difference in memory consumption between Javascript and Golang after the Wilcoxon test, t-test for paired data, and equivalence test, but the difference was essentially inconsequential (practically insignificant).

UMOTMA: Underwater multiple object tracking with memory aggregation

Underwater multi-object tracking (UMOT) is an important technology in marine animal ethology. It is affected by complex factors such as scattering, background interference, and occlusion, which makes it a challenging computer vision task. As a result, the stable continuation of trajectories among different targets has been the key to the tracking performance of UMOT tasks. To solve such challenges, we propose an underwater multi-object tracking algorithm based on memory aggregation (UMOTMA) to effectively associate multiple frames with targets. First, we propose a long short-term memory (LSTM)-based memory aggregation module (LSMAM) to enhance memory utilization between multiple frames. Next, LSMAM embeds LSTM into the transformer structure to save and aggregate features between multiple frames. Then, an underwater image enhancement module ME is introduced to process the original underwater images, which improves the quality and visibility of the underwater images so that the model can extract better features from the images. Finally, LSMAM and ME are integrated with a backbone network to implement the entire algorithm framework, which can fully utilize the historical information of the tracked targets. Experiments on the UMOT datasets and the underwater fish school datasets show that UMOTMA generally outperforms existing models and can maintain the stability of the target trajectory while ensuring high-quality detection. The code is available via Github.

Unsharp masking image enhancement the parallel algorithm based on cross-platform

In view of the low computational efficiency and the limitations of the platform of the unsharp masking image enhancement algorithm, an unsharp masking image enhancement parallel algorithm based on Open Computing Language (OpenCL) is proposed. Based on the analysis of the parallel characteristics of the algorithm, the problem of unsharp masking processing is implemented in parallel. Making use of the characteristics of data reuse in the algorithm, the effective allocation and optimization of global memory and constant memory are realized according to the access attributes of the data and the characteristics of the OpenCL storage model, and the use efficiency of off-chip memory is improved. Through the data storage access mode, the fast computing local memory access mode is discovered, and the logical data space transformation is used to convert the storage access mode, so as to improve the bandwidth utilization of the on-chip memory. The experimental results show that, compared with the CPU serial algorithm, the OpenCL accelerated unsharp masking image enhancement parallel algorithm greatly reduces the execution time of the algorithm while maintaining the same image quality, and achieves a maximum speedup of 16.71 times. The high performance and platform transplantation of the algorithm on different hardware platforms are realized. It provides a reference method for real-time processing of a large amount of data of high-resolution images for image enhancement.

Implementing cryptographic-based DH approach for enterprise network

The network is emerging as it involves multiple heterogeneous devices that are interconnected and able to communicate through certain information. Here security plays an important role in overcoming certain problems like loss of information, data traffic and protecting data activity. To the above security issues, the cryptography concept will enhance the security and also be able to protect the network resource that is transferred. To ensure data protection and privacy, here we recommend proposing a cryptographic-based DH approach to ensure the security enhancement consumes a lot of resources, power, memory, and CPU utilization time; here go for the modified key exchange and the encryption process. Initially, the modified Encryption process, where encryption is applied between the client and server and the encryption is processed at the client side to enhance the data privacy and integrity. Then, user authentication performs Modified Diffie Hellman to enhance the authentication process while sharing the data and avoid unauthorized users; finally, by overcoming certain attacks like Man in Middle and Discrete Logarithm attacks with the key exchange process, Modified Zero Knowledge Proof (ZKP) algorithm is applied. The analysis will be performed based on key aspects of size, key generation, encryption time, decryption time, and execution time.