Memory Protection Unit Research Articles

DEMIX: Domain-Enforced Memory Isolation for Embedded System

Memory isolation is an essential technology for safeguarding the resources of lightweight embedded systems. This technique isolates system resources by constraining the scope of the processor's accessible memory into distinct units known as domains. Despite the security offered by this approach, the Memory Protection Unit (MPU), the most common memory isolation method provided in most lightweight systems, incurs overheads during domain switching due to the privilege level intervention. However, as IoT environments become increasingly interconnected and more resources become required for protection, the significant overhead associated with domain switching under this constraint is expected to be crucial, making it harder to operate with more granular domains. To mitigate these issues, we propose DEMIX, which supports efficient memory isolation for multiple domains. DEMIX comprises two mainelements-Domain-Enforced Memory Isolation and instruction-level domain isolation-with the primary idea of enabling granular access control for memory by validating the domain state of the processor and the executed instructions. By achieving fine-grained validation of memory regions, our technique safely extends the supported domain capabilities of existing technologies while eliminating the overhead associated with switching between domains. Our implementation of eight user domains shows that our approach yields a hardware overhead of a slight 8% in Ibex Core, a very lightweight RISC-V processor.

ShieLD: Shielding Cross-Zone Communication Within Limited-Resourced IoT Devices Running Vulnerable Software Stack

Securing IoT devices is gaining attention as the security risks associated with these devices increase rapidly. TrustZone-M, a Trusted Execution Environment (TEE) for Cortex-M processors, ensures stronger security within an IoT device by allowing isolated execution of security-critical operations, without trusting the entire software stack. However, TrustZone-M does not guarantee secure cross-world communication between applications in the Normal and Secure worlds. The cryptographic protection of the communication channel is an obvious solution; however, within a low-power IoT device, it incurs high overhead if applied to each cross-world message exchange. We present ShieLD, a framework that enables a secure communication channel between the two TrustZone-M worlds by leveraging the Memory Protection Unit (MPU). ShieLD guarantees confidentiality, integrity and authentication services without requiring any cryptographic operations. We implement and evaluate ShieLD using a Musca-A test chip board with Cortex-M33 that supports TrustZone-M. Our empirical evaluation shows, among other gains, the cross-zone communication protected with ShieLD is <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5 times</i> faster than the conventional crypto-based communication.

FASLR: Function-Based ASLR via TrustZone-M and MPU for Resource-Constrained IoT Systems

The address space layout randomization (ASLR) has been widely deployed on modern operating systems against code reuse attacks (CRAs), such as return-oriented programming (ROP) and jump-oriented programming (JOP). However, porting ASLR to resource-constrained IoT devices is a great challenge due to the limited memory space for randomization. We propose a function-based ASLR scheme (fASLR) for IoT runtime security utilizing the ARM TrustZone-M technology and the memory protection unit (MPU) supported by ARM Cortex-M processors. fASLR loads a function from the flash and randomizes its base address in a randomization region in RAM when the function is being called. We design novel mechanisms on cleaning up finished functions from the RAM and memory addressing to tackle the complexity of function relocation and randomization. Optimizations are applied to effectively reduce overhead introduced by runtime memory management. We also formally prove that user applications will run correctly with fASLR enabled. Compared with the related work, a prominent advantage of fASLR is that fASLR can run an application even if the application code cannot be completely loaded into RAM for execution. We test fASLR with 21 applications. The experimental results show that fASLR achieves a high randomization entropy and incurs a runtime overhead of less than 10%.

ACE-M: Automated Control Flow Integrity Enforcement Based on MPUs at the Function Level

Control-flow integrity(CFI) ensures that the execution flow of a program follows the control-flow graph(CFG) determined at compile time. CFI is a security technique designed to prevent runtime attacks such as return-oriented programming (ROP). With the development of the Internet of Things (IoT), the number of embedded devices has increased, and security and protection techniques in embedded systems have become important. Since the hardware-based CFI technique requires separate hardware support, it is difficult to apply to an embedded device that is already arranged. In this paper, we propose a function-level CFI technique named ACE-M, which uses the memory protection unit (MPU) included in most embedded devices. MPU may provide attributes such as read-write-execute to the memory area. ACE-M has three steps: (1) initiate—inserts an MPU-related function into a specific position; (2) profiling—provides information for MPU configuration. After the initation step, several pieces of information can be determined; (3) set—modify the already-inserted function’s arguments. We propose a design that supports the MPU. In our model, the MPU becomes a control flow monitor that detects control flow errors(CFEs), and the inserted codes cause the MPU to act as a control flow checker. If the program deviates from the original control flow, the MPU raises an exception since its corresponding area will not be included in the executable area. This approach not only verifies the target address but also guarantees the running position. Our technique can detect any modification of the program counter (PC) to an arbitrary address.

Lightweight Microcontroller with Parallelized ECC-Based Code Memory Protection Unit for Robust Instruction Execution in Smart Sensors.

Embedded systems typically operate in harsh environments, such as where there is external shock, insufficient power, or an obsolete sensor after the replacement cycle. Despite these harsh environments, embedded systems require data integrity for accurate operation. Unintended data changes can cause a serious error in reduced instruction set computer (RISC)-based small embedded systems. For instance, if communication is performed on an edge, where there is insufficient power supply, the peak threshold is not reached, resulting in data transmission failure or incorrect data transmission. To ensure data integrity, we use an error-correcting code (ECC), which can detect and correct errors. The ECC parity bit and data are stored together using additional ECC memory, and the original data are extracted through the ECC decoding process. The process of extracting the original data is executed in the instruction fetch stage, where a bottleneck appears in the RISC-based structure. When the ECC decoding process is executed in the bottleneck, the instruction fetch stage increases the instruction fetch time and significantly reduces the overall performance. In this study, we attempt to minimize the effect of ECC on the transmission speed by executing the ECC decoding process in parallel to improve speed by degrading the bottleneck. To evaluate the performance of a parallelized ECC decoding block, we applied the proposed method to the tiny processing unit (TPU) with a RISC-based von Neumann structure and compared memory usage, speed, and reliability according to different transmission success rates in each model. The experiment was conducted using a benchmark that repeatedly executed several 3*3 matrix calculations, and reliability improvement was compared by corrupting the stored random date to confirm the reliability of the transmission success rate. As a result, in the proposed model, using the additional parity bits for parallel processing, memory usage increased by 10 bits per instruction, reducing the data rate from 80 to 61%. However, it showed an improvement in overall reliability and a 7% increase in speed.

New safe reliable design methodologies examined by fault injection testing and Monte Carlo simulation: tolerating shared-memory interferences in multicore architectures

Nowadays, the automotive industry utilises multicore processors to meet autonomous driving requirements. This imposes a higher complexity on the development and the verification of software applications. Compliance to the ISO 26262 safety standard increases this complexity. In this paper, means of shared-memory interferences that affect Automotive Safety Integrity Level (ASIL)-D multicore architectures have been addressed. This work proposes new safety mechanisms to detect and react to systematic and random transient memory faults as follows: 1) an enhanced software partitioning design pattern; 2) a new methodology on the memory protection unit; 3) an improved stack monitoring mechanism. New safe and reliable design configurations are introduced. The proposed safety mechanisms have been evaluated for Aurix multicore targets with suggestions to have a fully compliant architecture followed with ISO 26262 methods and principles of tolerating memory interferences. A novel fault injection platform is presented to show the experimental results with a Monte Carlo simulation proof of concept.

MxU

The advanced functionality requirements of modern embedded and Internet of Things (IoT) devices -- from autonomous vehicles, to city and power-grid management -- are driving an ever-increasing software complexity. At the same time, the pervasive internet connections of these systems necessitate the fundamental design of security into these devices. The isolation of complex features from those that are critical through protection domains is an effective means to constrain the scope of faults and security breaches. Common hardware-provided memory facilities to enforce protection domains through memory access control -- including Memory Management Units (MMUs) usually found in microprocessors, and Memory Protection Units (MPUs) usually found in microcontrollers -- must meet the goals of enabling flexible, efficient and dynamic management of memory , and must enable tight bounds on the worst-case execution of critical code. Unfortunately, current system memory management facilities are ill-prepared to handle this challenge: MMUs that use extensive caches to achieve strong average-case performance suffer from debilitating worst-case and even average-case behavior under hefty interference, while MPUs struggle to provide flexible memory management. This paper details MxU, a memory protection and allocation abstraction that integrates temporal specifications into the memory management subsystem, to enable portable code to achieve both predictable, tightly-bounded execution and dynamic management across both MMU- and MPU-based systems. We implement MxU in the Composite microkernel, and evaluate its flexibility and predictability over two different architectures: a MPU-based Cortex-M7 microcontroller and a MMU-based Cortex-A9 microprocessor using a suite of modern applications including neural network-based inference, SQLite, and a javascript runtime. For MMU-based systems, MxU reduces application TLB stall by up to 68.0%. For MPU-based systems, MxU enables flexible dynamic memory management often with application overheads of 1%, increasing to 6.1% under significant interference.

S The Security MicroVisor: A Formally-Verified Software-Based Security Architecture for the Internet of Things

The Internet of Things (IoT) is shaped by the increasing number of low-cost Internet-connected embedded devices that are becoming ubiquitous in every aspect of modern life. With their cost-sensitive design, integrating hardware-based security mechanisms into such devices is undesirable. Therefore, securing these devices is a particularly difficult challenge, especially, due to their growing popularity as attack targets, via remote malware infestations. The vast majority of such devices are bare-metal, where they execute programs in fully-accessible and unprotected memories without any operating system and even without including any form of security. This is beside the fact that IoToperating systems offer little or no protection. This paper addresses this problem through the concept of a Security MicroVisor (S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ</sub> V), which provides embedded devices that lack hardware-based memory protection units with memory isolation using software virtualisation and assembly-level code verification. More specifically, our contribution is two-fold. First, we propose S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ</sub> V as a software-based memory isolation technique. We then formally verify the software architecture, written in C, to prove that it is memory-safe and crash-free. Second, we propose a software-based remote attestation, as an example of a fundamental security service that can be implemented on top of S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ</sub> V, to detect malware-infected devices. We first describe the design and implementation of S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ</sub> V. Then, we highlight the formal verification of software architecture, and characterize the remote attestation protocol. We evaluate the S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ</sub> V implementation using an 8-bit AVR microcontroller that is widely used in IoT devices. Evaluation results show that S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ</sub> V provides strong security guarantees while maintaining extremely low overhead in terms of memory footprint, performance, and power consumption. Furthermore, we extend the performance evaluation also to the remote attestation scheme, illustrating its limited overhead.

Atlas: Application Confidentiality in Compromised Embedded Systems

Due to the requirements of the Internet-of-Things, modern embedded systems have become increasingly complex, running different applications. In order to protect their intellectual property as well as the confidentiality of sensitive data they process, these applications have to be isolated from each other. Traditional memory protection and memory management units provide such isolation, but rely on operating system support for their configuration. However, modern operating systems tend to be vulnerable and cannot guarantee confidentiality when compromised. We present Atlas, a hardware-based security architecture, complementary to traditional memory protection mechanisms, ensuring code and data confidentiality through transparent encryption, even when the system software has been exploited. Atlas relies on its zero-software trusted computing base to protect against system-level attackers and also supports secure shared memory. We implemented Atlas based on the LEON3 softcore processor, including toolchain extensions for developers. Our FPGA-based evaluation shows minimal cycle overhead at the cost of a reduced maximum frequency.

Hardware-Based Data Protection/Isolation at Runtime in Ada Code for Microcontrollers

This article describes an approach for using a memory protection unit (MPU) to enforce data protection/isolation at runtime, for individual data structures and memorymapped peripherals, in Ada bare-metal embedded software for microcontrollers. First, an MPU-based data protection architecture for Ada programs is described. Then, the changes required for the GNAT small-foot-print Ravenscar Ada runtime library, to implement this data protection architecture, are described.

Lightweight IO virtualization on MPU enabled microcontrollers

In the era of the Internet of Things (IoT), millions of devices and embedded platforms based on low-cost and limited resources microcontroller units (MCUs) will be used in continuous operation. Even if over-the-air firmware update is today a common feature, many applications might require not to reboot or to support hardware resource sharing. In such a context stop, update and reboot the platform is unpractical and dynamic loading of new user code is required. This in turn requires mechanisms to protect the MCU hardware resources and the continuously executing system tasks from uncontrolled perturbation caused by new user code being dynamically loaded. In this paper, we present a framework which provides a lightweight virtualization of the IO and platform peripherals and permits the dynamic loading of new user code. The aim of this work is to support critical isolation features typical of virtualization-ready CPUs on low-cost low-power microcontrollers with no MMU (Memory Management Unit), IOMMU or dedicated instruction extensions. Our approach only leverages the Memory Protection Unit (MPU), which is generally available in all ARM Cortex-M3 and Cortex-M4 microcontrollers. Experimental evaluations demonstrate not only the feasibility, but also the really low impact of the proposed framework in terms of memory requirements and runtime overhead.

For Safety and Security Reasons: The Cost of Component-Isolation in IoT

Abstract The current development trend of Internet of Things (IoT) aims for a tighter integration of mobile and stationary devices via various networks. This includes communication of vehicles to roadside infrastructure (V2I), as well as intelligent sensors / actors in Logistics and smart home environments. Compared to isolated traditional embedded systems, the exposure to open networks increases the attack surface, and errors in the networking components could compromise the safety and security of the embedded application or the whole network. But often current system architectures for mass-market IoT devices lack the required isolation concepts. Using a partitioning microkernel and enforcing the use of a microcontroller’s memory protection unit (MPU) facilities, we compare different isolation concepts for a publish/subscribe middleware implementing OMG’s Data Distribution Service (DDS) standard and we evaluate our results on an STM32F4 microcontroller. The results of this case study show moderate costs for increased memory usage and additional context switches.

Hardware support for memory protection in sensor nodes

With reference to the typical hardware configuration of a sensor node, we present the architecture of a memory protection unit (MPU) designed as a low-complexity addition to the microcontroller. The MPU is aimed at supporting memory protection and the privileged execution mode. It is connected to the system buses, and is seen by the processor as a memory-mapped input/output device. The contents of the internal MPU registers specify the composition of the protection contexts of the running program in terms of access rights for the memory pages. The MPU generates a hardware interrupt to the processor when it detects a protection violation. The proposed MPU architecture is evaluated from a number of salient viewpoints, which include the distribution, review and revocation of access permissions, and the support for important memory protection paradigms, including hierarchical contexts and protection rings.

OEM Software Integration into an ASIL D Control Device

The following example from a series project shall describe how customer software components have been integrated into an existing controller box and then the integration has been verified using highly automated processes. Both safety-relevant (up to ASIL D) and non-safety-relevant (QM) software components were encountered, with each ASIL level assigned its own memory protection unit (MPU) controlled RAM partition. The process is structured into several “gates”, ➊, which must be passed before proceeding to the next one. Once the last gate is passed, the integration process — including automated testing — is completed and the RTE has been verified in accordance with ISO 26262. Open image in new window ➊ Software integration and test process — mapping to the different chapters of ISO 26262-6 At Gate I, as the first step in each integration stage, artefacts describing the customer software components (in an AUTOSAR-compliant way) in different files are delivered by the customer. They include the software component description (SWCD) as well as timing information (Artime, Arexec), diagnostics (ODX), and communication (Fibex) information. The completeness of all artefacts is checked here to ensure a valid integration starting point. Afterwards, at Gate II, the input files received for Gate I must oftentimes be double checked regarding consistency, design or parser failures, or otherwise be made fit for use. So a consolidated set of system description files (SWCD etc.) is created at Gate III, BSW modules are modified or configured. The software architecture is created or modified. Software and interface requirements and a test specification are created. In the next step, Gate IV, the RTE is generated according to the consolidated system description files from Gate III using Continental’s own AUTOSAR development environment Cessar-CT (an Artop/Eclipse extension) and the RTE generator Cessar-RTE. Gates V and VI include BSW configuration and test development (design and implementation) and an integration test using stubbed versions of the customer software components. Finally, in Gate VII to VIII, the customer software is integrated and integration tests thereof are carried out and reviewed. Upon the passing of Gate VIII, the integration is complete. The various process steps of the software integration process relate to the chapters of ISO 26262-6, establishing the full ISO compliance.

Towards spatial isolation design in a multi-core real-time kernel targeting safety-critical applications

In mixed-criticality systems, applications naturally have different safety criticality levels. Partitioning technology is usually used to enable the integration of such mixed criticality applications upon one platform, aiming at reducing hardware, power consumption and especially certification cost. Partitioning can prevent fault propagation among mixed-criticality applications, if spatial and temporal isolation are adequately ensured. This paper focuses on the solution of spatial isolation in the HARTEX kernel on a multi-core platform in terms of memory, communication between applications and I/O sharing. According to formulated isolation requirements, a simple partitioning multi-core hardware architecture is proposed using SoC and memory protection units, and the kernel is extended to support spatial isolation between the kernel and applications as well as between applications. Combined design of hardware and software can easily achieve this isolation. At last, the spatial isolation is evaluated using a statistical sampling method and its performance is tested in terms of task switch, system call and footprint.

Shared heap management for memory-limited java virtual machines

One scarce resource in embedded systems is memory. Multitasking makes the lack of memory problem even worse. Most current embedded systems, which do not provide virtual memory, simply divide physical memory and evenly assign contiguous memory chunks to multiple applications. Such simple memory management can frequently cause the lack of available memory for some applications, while others are not using the full amount of assigned memory. To overcome inefficiency in current memory management, we present an efficient heap management scheme that allows multiple applications to share heap space. To reduce overall heap memory usage, applications adaptively acquire subheaps out of shared pool of memory and release surplus subheaps to shared pool. As a result, applications see noncontiguous multiple subheaps as a heap in their address space. We target Java applications to implement our heap-sharing scheme in the KVM from Sun Microsystems. To protect fragmented heap space with a limited number of regions in memory protection unit (MPU), we maintain only a limited number of subheaps. We experimentally evaluate our heap management scheme with J2ME MIDP applications. Our static and dynamic schemes reduce heap memory usage, on average, by 30 and 27%, respectively. For both schemes, overheads are kept low. The execution times in our schemes are increased only by 0.01% for static scheme and 0.35% for dynamic scheme, on average.

A microprogrammed virtual memory for Eclipse

The Eclipse S-200 is a Data General minicomputer available since 1975. It is a microprogrammed and microprogrammable computer: the user can buy a writable control store (WCS) to define his own specialized instructions. The Eclipse is also available with a memory allocation and protection unit (“MAP”) : so, the memory can be extended up to 128 K 16-bit words. However, the user's space is limited to 32 K words because of the address field structure in the instructions. For large programs, the user can define overlay areas or he can use chaining or swapping but these methods are sometimes not appropriate (e.g., for large recursive Algol programs). In this paper, we describe a realization of a virtual memory system that allows the user to have a working space larger than 32 K while relieving him from the management problems. Unfortunately, DG'S WCS feature is unsatisfactory: the last chapter describes some displeasing features. It should also be mentioned that Data General does not provide microutilities (microassembler or microloader), a fact which complicates the microprogramming task.

Microprocessing and microprogramming in Belgium

The Eclipse S-200 is a Data General minicomputer available since 1975. It is a microprogrammed and microprogrammable computer: the user can buy a writable control store (WCS) to define his own specialized instructions.The Eclipse is also available with a memory allocation and protection unit (“MAP”) : so, the memory can be extended up to 128 K 16-bit words.However, the user's space is limited to 32 K words because of the address field structure in the instructions. For large programs, the user can define overlay areas or he can use chaining or swapping but these methods are sometimes not appropriate (e.g., for large recursive Algol programs).In this paper, we describe a realization of a virtual memory system that allows the user to have a working space larger than 32 K while relieving him from the management problems.Unfortunately, DG'S WCS feature is unsatisfactory: the last chapter describes some displeasing features. It should also be mentioned that Data General does not provide microutilities (microassembler or microloader), a fact which complicates the microprogramming task.