Memory Polynomial Predistorter Research Articles

A Novel Digital Predistortion Identification Algorithm Based on Variable Forgetting Factor Recursive Least Square Method

The transmitting signal of wireless communication system is impaired by the nonlinearity of RF power amplifier (PA) which leads to signal distortion and spectrum spillover, by which the signal transmission quality is affected. Digital predistortion (DPD) is an efficient and economical way to correct the nonlinear effects of power amplifiers. The recursive least square (RLS) recognition algorithm is commonly used to extract the correction coefficients of the DPD model, and the accuracy of the extraction directly affects the system performance. In this paper, a new variable forgetting factor identification algorithm (new variable forgetting factor recursive least square, NVFFRLS) is proposed for recursive least square (RLS) identification algorithm. The 64-QAM signal is combined with a memory polynomial (MP) predistortion model for predistortion system simulation. The experimental results show that, compared with the RLS identification algorithm and two kinds of variable forgetting factor RLS identification algorithms, the algorithm has smaller estimation error, faster convergence, and better tracking capability, stability, and adaptability; the predistortion system based on NVFFRLS identification algorithm can compensate the nonlinear memory effects of power amplifier more effectively.

A low-power high-performance digital predistorter for wideband power amplifiers

In this paper, we present a low-power high-performance digital predistorter (DPD) for the linearization of wideband RF power amplifiers (PAs). It is based on the novel FIR memory polynomial (FIR-MP) predistorter model, which significantly augments the performance of the conventional memory polynomial predistorter with the use of complex baseband digital FIR filter prior to the memory polynomial. The adjacent channel leakage ratio (ACLR) performance comparison between the conventional MP and the proposed FIR-MP is done based on simulations with multi-carrier modulated signals of 20 and 80 MHz bandwidths. The PA models used for the simulations are extracted from the measurements of a commercial $$1\,\hbox {W}$$ GaAs HBT PA. At the ideal system-level simulations, the improvements in ACLR over the conventional MP are 7.2 and 15.6 dB, respectively, for 20 and 80 MHz signals. The choice of selection of various parameters of the predistorter along with the subsequent digital-to-analog converter (DAC) is presented. The impact of fixed-point representation is assessed using ACLR metrics, which shows that a wordlength of 14 bits is sufficient to obtain ACLR beyond $$45\,\hbox {dBc}$$ with a margin of $$10\,\hbox {dB}$$ . The proposed predistorter is synthesized in $$28\,\hbox {nm}$$ fully-depleted silicon-on-insulator (FDSOI) CMOS process. It is shown that with a fraction of the power and die area of that of the MP a huge improvement in ACLR is attained. With an overall power consumption of 8.2 and 88.8 mW, respectively, for 20 and 80 MHz signals, the FIR-MP DPD proves to be a suitable candidate for small-cell base station PA linearization.

Experimental demonstration of digital predistortion for orthogonal frequency‐division multiplexing‐radio over fibre links near laser resonance

Radio over fibre (RoF), an enabling technology for distribution of wireless broadband service signals through analogue optical links, suffers from non-linear distortion. Digital predistortion has been demonstrated as an effective approach to overcome the RoF non-linearity. However, questions remain as to how the approach performs close to laser resonance, a region of significant dynamic non-linearity, and how resilient the approach is to changes in input signal and link operating conditions. In this work, the performance of a digital predistortion approach is studied for directly modulated orthogonal frequency-division multiplexing RoF links operating from 2.47 to 3.7 GHz. It extends previous works to higher frequencies, and to higher quadrature amplitude modulation (QAM) levels. In addition, the resilience of the predistortion approach to changes in modulation level of QAM schemes, and average power levels are investigated, and a novel predistortion training approach is proposed and demonstrated. Both memoryless and memory polynomial predistorter models, and a simple off-line least-squares-based identification method, are used, with excellent performance improvements demonstrated up to 3.0 GHz.

A Digital Predistortion System With Extended Correction Bandwidth With Application to LTE-A Nonlinear Power Amplifiers

This article presents a bandwidth extended digital predistortion system suitable for LTE-advanced applications. The proposed predistortion system uses a two-box architecture based on the cascade of a memory polynomial followed by a memoryless predistortion function. The memoryless predistorter is identified offline and used to perform a coarse linearization which cancels out most of the static nonlinearity of the device under test allowing for a reduced observation bandwidth for the synthesis of the memory polynomial predistortion sub-function. The proposed predistorter was experimentally validated and its performance benchmarked against a predistorter having the same structure but identified using the conventional approach. The measurement results demonstrate that the proposed predistorter requires 30% less sampling speed for the analog to digital converter of the feedback path.

Lattice‐based memory polynomial predistorter for wideband radio frequency power amplifiers

This study addresses the ill-conditioning problem of the memory polynomial (MP) model with application to the predistortion of highly non-linear power amplifiers with memory effects. A resource-efficient lattice-based MP structure built using the cascade of a MP generator and a lattice predictor is proposed to overcome the ill-conditioning of the MP's data matrix. The proposed model performances are benchmarked against those of the MP model as well as the orthogonal MP model. The experimental results demonstrate the suitability of the proposed predistorter as it achieves similar performance in the time and the frequency domains compared to the MP counterpart while alleviating its ill-conditioning problem.

A Time Misalignment Tolerant 2D-Memory Polynomials Predistorter for Concurrent Dual-Band Power Amplifiers

This letter proposes a modified 2-D memory polynomial predistorter for concurrent dual band power amplifiers, which is tolerant to the time misalignment between the two bands. The new model is derived from the prior 2-D DPD model by substituting the interpolation expression into it. For performance validation, the proposed method is applied to a dual-band transmitter. In the presence of 4.87 samples time-misalignment existing between the two input signals, the proposed method achieves normalized mean square error of -40 dB and adjacent channel power ratio improvement of about 15 dB in the dual bands. Further experiment shows the proposed 2-D predistorter outperforms 2D-GMP in terms of complexity and signal quality.

New predistorter using triangular memory polynomial for power amplifier of OFDM-based wireless broadband communication system

A triangular memory polynomial (TMP) predistorter is presented in this paper to linearize a power amplifier's nonlinear with memory effects. Compared with the traditional memory polynomial (MP) predistorter, the coefficients of TMP predistorter is reduced more than 75%, which can effectively decrease the implementation complexity. The coefficients of predistorter are directly extracted from an offline system identification process by an open-loop structure in our approach. Several signals with data rate 5 MHz, 10 MHz, 15 MHz and 20 MHz are used to verify the performance of the proposed predistorter. Experimental results show that the proposed TMP predistorter and the traditional MP predistorter almost have the same performance.

THE RESEARCH AND APPLICATION OF COMBINING LUT AND MEMORY COMPENSATION FOR TWTA LINEARIZATION WITH RELATIVELY LOW SAMPLING FREQUENCY

If sampling frequency is not high enough, the efiect of adaptive memory polynomial predistortion linearizer is not very good for TWTA linearization. In order to keep the adaptive memory polynomial predistortion linearizer valid, usually the output power level of the TWTA must be reduced, which corresponds to a reduced e-ciency of the TWTA. In this paper, we present a digital predistortion linearizer by combining LUT (Look-Up-Table) and memory-efiect compensation technique, which may provide good linear performance with less reduction of the output power and relatively low sampling frequency. The results of simulations and experiments show that good linearity improvement can be reached for an X-band TWTA with this predistortion linearizer.

Look-up table-based digital predistorter implementation for field programmable gate arrays using long-term evolution signals with 60 MHz bandwidth

This study discusses the implementation of a digital predistorter to linearise radiofrequency (RF) power amplifiers, using input signals 60 MHz in bandwidth. The digital predistorter characterisation procedure is performed on a digital signal processor, using a memory polynomial modelling technique with QR-based recursive least squares (QR-RLS) as the extraction procedure. A multiple look-up table design for the memory polynomial predistorter is introduced, and by using fixed-point operations, reduces the processing latency considerably when compared with a floating-point-based predistorter implementation on a field programmable gate array (FPGA). Linearisation results are shown for a laterally diffused metal oxide semi-conductor (LDMOS)-based power amplifier (PA) biased in class AB operation with a three-carrier long-term evolution-time division duplex (LTE-TDD) input signal. Combining both the optimised predistortion coefficient extraction and predistorter implementation gives up to 20 dBc improvement in the adjacent channel and meets the wireless communication standard requirements.

An open-loop digital predistorter based on memory polynomial inverses for linearization of RF power amplifier

Digital Predistorter is a cost-effective solution to compensate for the nonlinear distortions appearing in the RF power amplifiers (PAs). The indirect learning scheme is widely implemented because of its flexibility to eliminate the requirement for building a closed-loop real time system, which dramatically reduces the complexity for measurement setup. However, such scheme is sensitive to the measurement noise that may cause biasing in the coefficients estimation. To minimize the influence of measurement noise and simultaneously enable the open-loop implementation, we propose a predistortion technique that first model the PA and then generates predistorted signal iteratively through a feedback configured structure to avoid using the noisy signal when performing the inverse model estimation. Unlike the indirect learning which estimates the postinverse of the PA, our predistortion is based on the preinverse of the PA. Both simulations and measurements show that utilizing the proposed predistortion can obtain adjacent channel power ratio (ACPR) improvement in wideband code division multiple access (WCDMA) signal test compared with the conventional memory polynomial predistortion based on indirect learning. © 2011 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2011.

Robust Fractional Order Memory Polynomial Based Pre-Distorter

In this paper, a robust fractional order memory polynomial pre-distorter with two novel schemes to conduct digital base-band power amplifier pre-distortion is proposed. For the first scheme, fractional order terms are included in the conventional memory polynomial containing the odd and even order polynomial terms, which is called Scheme One. The second scheme, called Scheme Two, simply replaces even order polynomial terms with fractional order polynomial terms to improve the linear performance of power amplifiers. The mathematical expressions for these two schemes are derived. The computer simulations and numerical analysis show that, compared with the conventional pre-distortion methods, 11dB and 8.5dB more out-of-band suppression gain can be obtained by Scheme One and Scheme Two, respectively. Corresponding FPGA realization shows that the two schemes are cost-effective in terms of hardware resources.

Filter Lookup Table Method for Power Amplifier Linearization

This paper presents a new method of digital adaptive predistortion for linearization of power amplifiers (PAs) exhibiting memory effects. The predistorter (PD) device consists of a lookup table (LUT) gain followed by a codebook of filters addressed by the index of the LUT. The adaptation is derived from direct learning for the LUT gains and indirect learning for the filter coefficients. We compared our results with those of two reference methods: a simple LUT system (with direct learning) and a memory polynomial system (with indirect learning). The performances of the new approach lie between those of the two reference methods in terms of adjacent channel power regrowth and error vector magnitude. The LUT is the less complex of the three methods, but it is a memoryless system, and it cannot correct the memory effects in the PA. The memory polynomial PD is more powerful, but its complexity is very high. The new technique, due to the addition of filters to the LUT, has possibilities to compensate not only for the nonlinearity but also for the memory effects in the PA, and it is one order of magnitude less complex than the memory polynomial system