Memory Management Method Research Articles

Simulation and reconstruction for 3D elastic wave using multi-GPU and CUDA-aware MPI

3D finite-difference time-domain numerical simulation and reconstruction based on the domain decomposition technique are essential parts of high-performance computation for reverse-time migration and full-waveform inversion. However, the low GPU utilization in computing for small-sized models and the tremendous memory consumption for large-sized models may result in low computational efficiency and high memory costs. This paper proposes a contiguous memory management (CMM) method and a variable-order wavefield reconstruction (VWR) method. The CMM allocates the memory of many small-sized arrays used for MPI communications on a larger-sized contiguous memory block, which aims to reduce the number of MPI communications between subdomains and improve the communication bandwidth, thus reducing the MPI time overhead and improving the GPU utilization. Meanwhile, the VWR can flexibly set the number of layers of boundary wavefield used for source wavefield reconstruction according to the host memory capacity and accuracy requirements. Since one layer of boundary wavefield could be stored using the VWR, the memory consumption of host memory can be significantly alleviated. Numerical experiments show that GPU utilization in computing for the model with a size of 1213 can be improved from 25% to 90% using the CMM method, and the VWR method can reduce memory consumption by about 86% while maintaining good accuracy in wavefield reconstruction. In addition, the issue of how to obtain a domain decomposition scheme with optimal performance is discussed in this paper.

An Embedded-GPU-Based Scheme for Real-Time Imaging Processing of Unmanned Aerial Vehicle Borne Video Synthetic Aperture Radar

The UAV-borne video SAR (ViSAR) imaging system requires miniaturization, low power consumption, high frame rates, and high-resolution real-time imaging. In order to satisfy the requirements of real-time imaging processing for the UAV-borne ViSAR under limited memory and parallel computing resources, this paper proposes a method of embedded GPU-based real-time imaging processing for the UAV-borne ViSAR. Based on a parallel programming model of the compute unified device architecture (CUDA), this paper designed a parallel computing method for range-Doppler (RD) and map drift (MD) algorithms. By utilizing the advantages of the embedded GPU characterized with parallel computing, we improved the processing speed of real-time ViSAR imaging. This paper also adopted a unified memory management method, which greatly reduces data replication and communication latency between the CPU and the GPU. The data processing of 2048 × 2048 points took only 1.215 s on the Jetson AGX Orin platform to form a nine-consecutive-frame image with a resolution of 0.15 m, with each frame taking only 0.135 s, enabling real-time imaging at a high frame rate of 5 Hz. In actual testing, continuous mapping can be achieved without losing the scenes, intuitively obtaining the dynamic observation effects of the area. The processing results of the measured data have verified the reliability and effectiveness of the proposed scheme, satisfying the processing requirements for real-time ViSAR imaging.

Incremental Image De-raining via Associative Memory

While deep learning models have achieved the state-of-the-art performance on single-image rain removal, most methods only consider learning fixed mapping rules on the single synthetic dataset for lifetime. This limits the real-life application as iterative optimization may change mapping rules and training samples. However, when models learn a sequence of datasets in multiple incremental steps, they are susceptible to catastrophic forgetting that adapts to new incremental episodes while failing to preserve previously acquired mapping rules. In this paper, we argue the importance of sample diversity in the episodes on the iterative optimization, and propose a novel memory management method, Associative Memory, to achieve incremental image de-raining. It bridges connections between current and past episodes for feature reconstruction by sampling domain mappings of past learning steps, and guides the learning to trace the current pathway back to the historical environment without storing extra data. Experiments demonstrate that our method can achieve better performance than existing approaches on both inhomogeneous and incremental datasets within the spectrum of highly compact systems.

Capability of processing the GNDS format evaluated nuclear data in NECP-Atlas for neutronics calculations

The Generalized Nuclear Data Structure (GNDS) has been being designed as the replacement of the conventional ENDF-6 format for the evaluated nuclear data libraries. The specification for the GNDS format was released by OECD/NEA in 2020. And the latest evaluated nuclear data libraries ENDF/B-VIII.0 and TENDL2019 were released in the ENDF-6 format and the GNDS format, simultaneously. The capability of processing the GNDS format evaluated nuclear data libraries is developed in the nuclear data processing code NECP-Atlas. To be compatible with the GNDS and ENDF-6 formats, the memory management method and the data structure in NECP-Atlas are modified to support more data beyond the ENDF-6 format. At the same time, a module called GNDS-Toolkit is developed to read, parse and convert the GNDS/XML format libraries. The ENDF/B-VIII.0 library in GNDS/XML format is processed into ACE format and multi-group libraries, and used in criticality calculations, lattice physics calculations and shielding calculations. The results show that the GNDS format libraries can be exactly processed by NECP-Atlas.

Перспективні напрямки розвитку IT-сфери в світі

To study promising areas of IT development is very important not only because it helps find competitive advantages for IT managers, but also because of the impact it makes on various aspects of economic activity, such as customers, clients, ecosystem, etc. The article in question is aimed at determining promising areas of IT development in the world by analyzing the current trends and predict researchers’ publication and patent activity. The methodological basis for the article is made up by the following: research review, analysis of general trends in the IT development, bibliometric and patent analysis, and graphic and statistical analysis. A general approach is suggested to identify promising areas of IT development in the world, the approach being comprehensive, unlike the already existing ones. The main trends in the IT development are studied by reviewing scientific literature and reports on the technological development of the industry. In particular, Gartner Hype Cycle for Emerging Technologies is analyzed. The world’s technological foresights, in particular those of the EU countries, the USA, South Korea, and Japan, were analyzed, which allowed us to identify the most probable trends in the IT development in the world. The dynamics and structure of scientists’ publishing activity on the topic of “Computer Science” are analyzed according to the bibliometric indicators of the SCImago Journal & Country Rank portal, and patent applications published in the field of information technology is analyzed according to the data of the World Intellectual Property Organization (WIPO). The changes in the structure and number of publications and patent applications for the period 1996–2020 are analyzed. The most promising areas of research in the IT sphere are determined. Due to grouping the obtained results we can determine such promising areas of IT development in the world: artificial intelligence, cloud technologies, blockchain technology, information and communication technologies, big data, computing memory, chatbots, cybersecurity, language recognition, digital communication, computer networks, and IT management methods. The obtained results of the research can serve as a basis to determine the priorities of developing IT research in Ukraine

Distributed Real-Time Image Processing of Formation Flying SAR Based on Embedded GPUs

<b>Formation flying synthetic aperture radar (FF-SAR) systems, as an important development direction of multichannel SAR, can achieve high-resolution wide-swath (HRWS) imaging. Coherently combining data from satellite receivers puts a strain on traditional real-time processing systems based on individual satellites. Characteristics such as the power of real-time on-orbit processing platform must be properly balanced with constrained memory and parallel computational resources. This paper proposes a distributed SAR real-time imaging method based on embedded Graphics Processing Units (GPUs). The parallel computing method of chirp scaling (CS) algorithm is designed based on parallel programming model of compute unified device architecture (CUDA), and the optimization methods of memory and performance are proposed for the hardware architecture of embedded GPUs. In particular, unified memory management method is used to avoid data copying and communication delays between the CPU and GPU. A hardware verification system for distributed SAR real-time imaging processing based on multiple embedded GPUs is constructed. The proposed algorithm takes 5.86 seconds to process single-precision floating-point complex imaging with a data size of 8192 &#x00D7; 8192 on a single Jetson Nano platform. The actual power consumption is less than 5 W, and the performance-to-power ratio is greater than 1.7&#x0025;. The experimental results show that the real-time processing method based on embedded GPUs proposed in this paper has high performance and low power consumption.</b>

An efficient multi-threaded memory allocator for PDES applications

Parallel Discrete Event Simulation (PDES) aims at providing high performance solutions for simulation with large and complex models. Like traditional multi-threaded applications, PDES applications are also confronted with large overhead produced by memory allocation. Especially, complex models and frequent inter-thread communications in PDES applications will lead to large amounts of memory allocation and deallocation requests. Inter-thread communications are implemented by sending and receiving events based on shared memory. Hence, an efficient memory allocator has great impact on the performance of such applications. Current well-known allocators are dedicated to be scalable and lock-free. However, they ignore the difference between thread local and shared memory and manage them in the same way, which cannot make good use of their own characteristics. To solve this problem, this paper proposes a high efficient multi-threaded memory allocator named HMalloc, which innovatively separates thread local memory from shared memory. Thus, local memory allocation and deallocation will not lead to false sharing and lock contention. Moreover, coalescence free is applied to free local memory blocks. Furthermore, a flag-based shared memory management method is proposed to achieve lock-free shared memory allocation and deallocation. Experimental results show that HMalloc can achieve significant performance improvement in both traditional memory allocation benchmarks and typical PDES benchmarks when compared with existing well-known memory allocators.

An Efficient VNS Algorithm to Solve the Multi-Attribute Technician Routing and Scheduling Problem

This article addresses a technician routing and scheduling problem inspired from an application for the repair of electronic transactions equipment. It consists of designing routes for staff to perform requests while considering certain constraints and resources. The objective is to minimize a linear combination of total weighted distance, overtime, and maximize the served requests. An efficient meta-heuristic algorithm based on variable neighborhood search with an adaptive memory and advanced diversity management method is proposed. Numerical results show that the meta-heuristic outperforms the best existing algorithm from the literature which is a Tabu Search.

Memory system optimization for graph processing: a survey

Containing a variety of information, a graph is a complex data structure comprising vertices and edges. Graph processing or graph computing is the abstraction of the relation and properties of graph structures in real-life situations and performing some complex computations. Owing to the bottlenecks in the performance of the central processing unit, many coprocessors and domain-specific accelerators have been designed to improve running speed and to save energy. Considering the strong data dependence of graphs, improving the efficiency of memory access is a critical issue to improve system performance. In particular, memory management and optimization have become extremely important due to the expansion of graph data scale and the acceleration of various graph processing. This study aims to propose a memory architecture and management methods in graph processing on heterogeneous architecture. We describe the graph data layout that can improve the efficiency of memory access, analyze recent work on memory optimization and features of GPU, FPGA, ASIC, PIM, among others. Furthermore, we summarize relevant research progresses in recent years in China, and conclude the opportunities and challenges of graph processing in memory.

Internet of Things (IoT) Operating Systems Support, Networking Technologies, Applications, and Challenges: A Comparative Review

The Internet of Things (IoT) has become a reality. As the IoT is now becoming a far more common field, the demand for IoT technologies to manage the communication of devices with the rest of the world has increased. The IoT is connecting various individual devices called things and wireless sensor networks is also playing an important role. A thing can be defined as an embedded device based on a micro controller that can transmit and receive information. These devices are extremely low in power, memory, and resources. Therefore, the research community has recognized the importance of IoT device operating systems (OSs). An adequate OS with a kernel, networking, real-time capability, and more can make these devices flexible. This review provides a detailed comparison of the OSs designed for IoT devices on the basis of their architecture, scheduling methods, networking technologies, programming models, power and memory management methods, together with other features required for IoT applications. In addition, various applications, challenges, and case studies in the field of IoT research is discussed.

Analyzing memory management methods on integrated CPU-GPU systems

Heterogeneous systems that integrate a multicore CPU and a GPU on the same die are ubiquitous. On these systems, both the CPU and GPU share the same physical memory as opposed to using separate memory dies. Although integration eliminates the need to copy data between the CPU and the GPU, arranging transparent memory sharing between the two devices can carry large overheads. Memory on CPU/GPU systems is typically managed by a software framework such as OpenCL or CUDA, which includes a runtime library, and communicates with a GPU driver. These frameworks offer a range of memory management methods that vary in ease of use, consistency guarantees and performance. In this study, we analyze some of the common memory management methods of the most widely used software frameworks for heterogeneous systems: CUDA, OpenCL 1.2, OpenCL 2.0, and HSA, on NVIDIA and AMD hardware. We focus on performance/functionality trade-offs, with the goal of exposing their performance impact and simplifying the choice of memory management methods for programmers.

그래픽 프로세서를 이용한 시간 영역 3차원 파동 전파 모델링과 메모리 관리

효율적인 시간 영역 3차원 파동 전파 모델링을 위해 그래픽 프로세서를 사용하였다. 그래픽 프로세서는 대규모 병렬 연산을 위한 프로세서로, 그래픽 프로세서를 효율적으로 이용하기 위해서는 계산 과정과 메모리 복사 과정을 최적화할 필요가 있다. 본 연구에서는 메모리 관리에 초점을 맞추고 메모리 관리 방법에 따라 그래픽 프로세서를 이용한 프로그램의 성능이 어떻게 달라지는지 확인하였다. 또한 유한 차분법 차수와 속도 모델의 크기를 변화시켜가며 메모리 복사가 프로그램 성능에 미치는 영향을 시험하였다. 그 결과 3차원 파동장 전체를 복사하는 프로그램에서 메모리 관리가 유한 차분법 계산보다 큰 비중을 차지함을 알 수 있었다. We used graphics processing units for an efficient time-domain 3D wave propagation modeling. Since graphics processing units are designed for massively parallel processes, we need to optimize the calculation and memory management to fully exploit graphics processing units. We focused on the memory management and examined the performance of programs with respect to the memory management methods. We also tested the effects of memory transfer on the performance of the program by varying the order of finite difference equation and the size of velocity models. The results show that the memory transfer takes a larger portion of the running time than that of the finite difference calculation in programs transferring whole 3D wavefield.

ROHOM: Requirement-aware Online Hybrid On-chip Memory Management for Multicore Systems

Many studies have shown that energy consumption of on-chip memory is a critical issue for multicore embedded systems. In order to reduce energy consumption, scratchpad memory (SPM), a software controlled on-chip memory, has been increasingly used. In a typical multicore embedded system that uses SPM in the on-chip memory, each core has local SPM and can access data in both local SPM and SPMs of other cores (i.e., remote SPM). Since the latency and energy of accessing remote SPMs is higher than accessing local SPM, how data are allocated in local and remote SPMs influences the performance and energy consumption of the system. This paper proposes a requirement-aware online hybrid on-chip memory management (ROHOM) method. This method contains an SPM supervisor that determines the SPM allocation of each task according to the dynamic access behavior and SPM requirements of the task. In addition, two policies: 1) free remote SPM space first and 2) get local SPM space first, are proposed in ROHOM to reduce the access frequency of remote SPMs. The experimental results show ROHOM can reduce energy delay product up to 69% (42% on average) in an 8-core system and up to 69% (50% on average) in a 16-core system when compared to a contention aware SPM allocation method. The hardware area overhead is insignificant (about 1.8%).

A novel memory management method for multi-core processors

This study examines a multicore processor based on a system-on-chip (SoC) and configured by a Tensilica Xtensa® LX2. The multicore processor is a heterogeneous, configurable dual-core processor. In this study, one core was used as the host to control the processor chip, and the other was used as a slave to extend digital signal processing applications. Each core not only owned its local memory, but also shared common data memory. In addition, the proposed multicore processors had a virtual memory. This additional memory supported the processor by enabling it to easily manage complex programs; it also allowed the two cores to access data from the unified data memory of different tasks. For bus management, a bus arbitration mechanism was added to handle the cores and to distribute the priority of asynchronous access requests. The benefits of the proposed structure include avoiding hardwired memory and reducing interface handshaking. To verify the proposed processor, it was simulated on the model level using a Petri net graph, and on the system level using ARM SoC designer tools. In the performance simulation, we found that the lowest latency-to-cost ratios were achieved using a 32-bit bus interface and a 4-entry data queue.

Receiver memory management method for HARQ in LTE-based satellite communication system

Summary For the successful deployment of the long term evolution (LTE)-based mobile satellite service, the price of a user terminal is one of the major factors. A user terminal for the LTE-based satellite communication needs to be implemented with a similar hardware size that is used for a terrestrial LTE user terminal. However, for quality of service provision, the satellite user terminal needs a larger size of memories than the terrestrial terminal does. This is very evident by considering that the N-channel stop and wait hybrid automatic repeat request requires proportionally increasing memory size by the propagation delay, resulting in unmanageable amount of memories in the satellite system. To resolve this problem, we propose an efficient memory management method at the user terminal when the size of memory is insufficient. The simulation results in this paper reveal that the proposed method can increase the throughput about 20.7% when a user terminal is operated under very low throughput condition with an insufficient memory size, compared with the case without memory management scheme. In addition, we show that the additional throughput gain can be obtained by the packet scheduling using the information of receiver memory status. Copyright © 2015 John Wiley & Sons, Ltd.

Non-volatile main memory management methods based on a file system.

There are upcoming non-volatile (NV) memory technologies that provide byte addressability and high performance. PCM, MRAM, and STT-RAM are such examples. Such NV memory can be used as storage because of its data persistency without power supply while it can be used as main memory because of its high performance that matches up with DRAM. There are a number of researches that investigated its uses for main memory and storage. They were, however, conducted independently. This paper presents the methods that enables the integration of the main memory and file system management for NV memory. Such integration makes NV memory simultaneously utilized as both main memory and storage. The presented methods use a file system as their basis for the NV memory management. We implemented the proposed methods in the Linux kernel, and performed the evaluation on the QEMU system emulator. The evaluation results show that 1) the proposed methods can perform comparably to the existing DRAM memory allocator and significantly better than the page swapping, 2) their performance is affected by the internal data structures of a file system, and 3) the data structures appropriate for traditional hard disk drives do not always work effectively for byte addressable NV memory. We also performed the evaluation of the effects caused by the longer access latency of NV memory by cycle-accurate full-system simulation. The results show that the effect on page allocation cost is limited if the increase of latency is moderate.

Appearance-Based Loop Closure Detection for Online Large-Scale and Long-Term Operation

In appearance-based localization and mapping, loop-closure detection is the process used to determinate if the current observation comes from a previously visited location or a new one. As the size of the internal map increases, so does the time required to compare new observations with all stored locations, eventually limiting online processing. This paper presents an online loop-closure detection approach for large-scale and long-term operation. The approach is based on a memory management method, which limits the number of locations used for loop-closure detection so that the computation time remains under real-time constraints. The idea consists of keeping the most recent and frequently observed locations in a working memory (WM) that is used for loop-closure detection, and transferring the others into a long-term memory (LTM). When a match is found between the current location and one stored in WM, associated locations that are stored in LTM can be updated and remembered for additional loop-closure detections. Results demonstrate the approach's adaptability and scalability using ten standard datasets from other appearance-based loop-closure approaches, one custom dataset using real images taken over a 2-km loop of our university campus, and one custom dataset (7 h) using virtual images from the racing video game “Need for Speed: Most Wanted”.

Research about NAND-Based Adaptive Storage Management Method

Since the physical characteristics and access mode of flash memory both have significant difference with disk, storage management research become the basis and key factor of flash memory database, the performance of storage management often directly impacted on the performance of other subsystems in flash memory database system. Against the characteristics of database data access and problems of existing methods, this paper presented an adaptive flash memory management method which improved performance of data updating in flash memory while taking into account of the better read performance.

A Robust and Space-Efficient Stack Management Method for Wireless Sensor Network OS with Scarce Hardware Resources

Due to such requirements as low power consumption and low cost, sensor nodes commonly do not include advanced H/W features. The absence of the features such as the memory management unit enforces several tasks to share a memory address domain on a small data memory space (1 ~16 KB). It exposes each task to the stack overflow causing the corruption of other memory areas. In this paper, we propose a robust and efficient stack memory management method (RESM) that dynamically assigns and releases a preestimated amount of stack memory to each function call at runtime. RESM maintains the stack memory usage with the similar amount of the stack usage that the system actually requires, and the stack memory area of each task is individually protected from corruption by the stack overflow. RESM can also anticipate a saturated condition in data memory at runtime. When the memory state is unsafe from the saturated condition, it conditionally allows function calls to operate tasks without any memory fault by using the proposed function call deferring algorithm. From the analytical and experiment results, it is proven that the performance of RESM outperforms the other mechanisms and RESM can provide more robust stack operation environment.

Power Variability in Contemporary DRAMs

Technology scaling has led to significant variability in chip performance and power consumption. In this work, we measured and analyzed the power variability in dynamic random access memories (DRAMs). We tested 22 double date rate third generation (DDR3) dual inline memory modules (DIMMs), and found that power usage in DRAMs depends on both operation type (write, read, and idle) as well as data, with write operations consuming more than reads, and 1s in the data generally costing more power than 0s. Temperature had little effect (1-3%) across the C to 50 C range. Variations were up to 12.29% and 16.40% for idle power within a single model and for different models from the same vendor, respectively. In the scope of all tested 1 gigabyte (GB) modules, deviations were up to 21.84% in write power. Our ongoing work addresses memory management methods to leverage such power variations.