Memory Management Algorithm Research Articles

Cloud-based Cost Effective IIoT Model Towards Industry 5.0

Companies across industries increasingly depend upon cloud computing to manage their Industrial Internet of Things (IIoT) technology. Machines are connected over a network in the IIoT. Cloud computing plays an essential role by connecting people, devices, work processes, and buildings to deliver cloud services in industries. But cloud computing faces a problem with task scheduling, high latency delay, and memory management, affecting the overall cost of industries using cloud services. A major concern in the cloud computing field is task scheduling which is essential for achieving cost-effective execution and improving resource usage. It refers to assigning available resources to user tasks. This problem can be solved effectively by improving task execution and increasing the use of resources. The waiting time between a client’s sent request and a cloud service provider to give a response, known as latency, is another issue in cloud environments. In cloud computing, this delay can be significantly higher. As a result, users of various cloud services may incur increased expenses due to this delay. Finally, among the most significant topics in cloud computing is efficient memory management, which handles integrated data and optimizes memory management algorithms. This paper proposes a cloud model for IIoT, which provides task scheduling, helps reduce latency, and optimizes memory management. This proposed model helps to reduce the cost of using cloud computing in IIoT.

Study of Energy-Efficient Optimization Techniques for High-Level Homogeneous Resource Management

Resource management efficiency can be a beneficial step toward optimizing power consumption in software-hardware integrated systems. Languages such as C, C++, and Fortran have been extremely popular for dealing with optimization, memory management, and other resource management. We investigate novel algorithmic architectures capable of optimizing resource requirements and increasing energy efficiency. The experimental results obtained with C++ can be extended to other programming languages as well. We emphasize the inherent drawbacks of memory management operators. These operators are intended to be extremely generic in their application, just as the concept of dynamic memory is. As a result, they are unable to take advantage of the various optimization techniques and opportunities that specific use cases present. Each source code file is modeled after its own distinct memory usage pattern, which can be used to speed up memory management routines. Such concepts are frequently time-consuming and costly to implement; consequently, they are not the primary concern of application developers, as they require manual development and integration. We intend to address this gap by providing a suite of memory management algorithms that enable dramatic performance improvements at the source code level while allowing for seamless integration across multiple use cases. The techniques have been evaluated on several performance parameters, and results have been presented. In this paper, we have compared a variety of memory allocation techniques and compared their space and energy efficiency requirements. Three variants of SSDAM, SSDAM-E, and DLLOM strategies have been evaluated and compared against the base performance of new and delete operators. SSDAM-E, SSDAM with new delete operators, and DDLOM improve the memory consumption by the factors of 8.01, 7.0, and 4.0, respectively. In the worst case, SSDAM-E gave an average running time of 5.650 sec faster than the DLLOM average time of 7.496 sec. As far as energy efficiency is considered, SSDAM-Original and SSDAM-E-Original attain 100%, in comparison with the base efficiency of 12.48% characterized by new/delete operators.

Metall: A persistent memory allocator for data-centric analytics

Data analytics applications transform raw input data into analytics-specific data structures before performing analytics. Unfortunately, such data ingestion steps are often more expensive than analytics. In addition, various types of NVRAM devices are already used in many HPC systems today. Such devices will be useful for storing and reusing data structures beyond a single process life cycle.We developed Metall, a persistent memory allocator built on top of the memory-mapped file mechanism. Metall enables applications to transparently allocate custom C++ data structures into various types of persistent memories. Metall incorporates a concise and high-performance memory management algorithm inspired by Supermalloc and the rich C++ interface developed by Boost.Interprocess library.On a dynamic graph construction workload, Metall achieved up to 11.7x and 48.3x performance improvements over Boost.Interprocess and memkind (PMEM kind), respectively. We also demonstrate Metall’s high adaptability by integrating Metall into a graph processing framework, GraphBLAS Template Library. This study’s outcomes indicate that Metall will be a strong tool for accelerating future large-scale data analytics by allowing applications to leverage persistent memory efficiently.

DAFA: Diversity-Aware Feature Aggregation for Attention-Based Video Object Detection

We present a framework for attention-based video object detection using a simple yet effective external memory management algorithm. An attention mechanism has been adopted in video object detection task to enrich the features of key frames using adjacent frames. Although several recent studies utilized frame-level first-in-first-out (FIFO) memory to collect global video information, such a memory structure suffers from collection inefficiency, which results in low attention performance and high computational cost. To address this issue, we developed a novel scheme called diversity-aware feature aggregation (DAFA). Whereas other methods do not store sufficient feature information without expanding memory capacity, DAFA efficiently collects diverse features while avoiding redundancy using a simple Euclidean distance-based metric. Experimental results on the ImageNet VID dataset demonstrate that our lightweight model with global attention achieves 83.5 mAP on the ResNet-101 backbone, which exceeds the accuracy levels of most existing methods with a minimum runtime. Our method with global and local attention stages obtains 84.5 and 85.9 mAP on ResNet-101 and ResNeXt-101, respectively, thus achieving state-of-the-art performance without requiring additional post-processing methods.

Randomized C/C++ dynamic memory allocator

Dynamic memory management requires special attention in programming. It should be fast and secure at the same time. This paper proposes a new randomized dynamic memory management algorithm designed to meet these requirements. Randomization is a key feature intended to protect applications from “use-after-free” or similar attacks. At the same time, the state in the algorithm consists only of one pointer, so it does not consume extra memory for itself. However, our algorithm is not a universal solution. It does not solve the memory fragmentation problem and it needs further development and testing.

ДОСЛІДЖЕННЯ СИСТЕМНИХ ПРОЦЕСІВ ТА КОРИСТУВАЦЬКИХ ДОДАТКІВ ОПЕРАЦІЙНОЇ СИСТЕМИ ANDROID В КОНТЕКСТІ ЯВИЩА СТАРІННЯ ПРОГРАМНОГО ЗАБЕЗПЕЧЕННЯ

Android operating system is vulnerable to the aging-related effects such as performance degradation and increased of aging-related failures rate due prolonged usage of a mobile device without rebooting. This paper considers software aging phenomenon in system processes and user applications of the Android operating system and means for counteracting this phenomenon. Experimental research was performed using a methodology that consists in performing stress tests on mobile applications, collecting system data on running processes, converting the collected data into time series for the relevant metrics and analyzing these data using statistical methods. Thus, the analysis of oom_adj_score for determining processes priorities in the context of software aging allowed to identify two groups of processes, namely system processes and user applications. It is also pointed out the possibility of using oom_adj_score to determine the state of system usage in the tasks of software aging predicting and performing software rejuvenation. The results of the system processes analysis showed that the indicators of aging are system_server and surfaceflinger processes, as well as com.android.phone, cameraserver in the case of active use of contacts and camera applications. The considered processes can be used to implement software rejuvenation. Research has shown that user applications are also vulnerable to aging-related effects, but the rejuvenation procedure cannot be applied to them at the system level. It is important to take steps to prevent aging-related errors, such as using appropriate data structures and algorithms for efficient memory management, minimizing the load on the main UI stream, and using effective graphics techniques to reduce the number of delayed frames. In future works it is important to investigate the considered system processes and services in tasks of software aging forecasting and performing of rejuvenation procedure. It is important for user applications to develop tools that provide developers with information about the state of software aging in the system, which would allow to decide on the feasibility of performing important and resource-intensive tasks in conditions when the system is already in a state with a high probability of aging-related failure.

A cost model for random access queries in document stores

Document stores have become one of the key NoSQL storage solutions. They have been widely adopted in different domains due to their ability to store semi-structured data and expressive query capabilities. However, implementations differ in terms of concrete data storage and retrieval. Unfortunately, a standard framework for data and query optimization for document stores is nonexistent, and only implementation-specific design and query guidelines are used. Hence, the goal of this work is to aid automating the data design for document stores based on query costs instead of generic design rules. For this, we define a generic storage and query cost model based on disk access and memory allocation that allows estimating the impact of design decisions. Since all document stores carry out data operations in memory, we first estimate the memory usage by considering characteristics of the stored documents, their access patterns, and memory management algorithms. Then, using this estimation and metadata storage size, we introduce a cost model for random access queries. We validate our work on two well-known document store implementations: MongoDB and Couchbase. The results show that the memory usage estimates have the average precision of 91% and predicted costs are highly correlated to the actual execution times. During this work, we have managed to suggest several improvements to document storage systems. Thus, this cost model also contributes to identifying discordance between document store implementations and their theoretical expectations.

PairCon-SLAM: Distributed, Online, and Real-Time RGBD-SLAM in Large Scenarios

This article proposed a PairCon-simultaneous localization and mapping algorithm to construct dense maps of large-scale scenarios in real time, which is operated in an integral platform containing two personal computers (PCs). This platform can operate the mapping thread independently in a PC to guarantee sufficient memory resources. In this context, the synchronous visualization of 3-D maps can be achieved in such a platform. In contrast, traditional algorithms are limited by the short operation distance, under the requirement of simultaneous data collection and 3-D maps construction in a PC. In addition, the memory resource provided by a single PC is limited, which restricts the constructing scale of maps. Thus, we use a separate PC to construct maps independently to relieve the distance constraint and exploit the socket method to conduct the transmission of data with the point cloud. Meanwhile, we introduce the ReBlur algorithm into the semi-direct method to reduce the error accumulation of the odometer in the tracking thread, which improves the robustness performance. In addition, the method combining the memory management and DBow2 algorithm is adopted to improve the accuracy of loop detection. In the considered system, the quality of maps and the performance of the odometer are evaluated by ICL-NUIM and the datasets, such as TUM, DIODE, and so on, respectively. Finally, under the simulation environment of AirSim and Gazebo, we construct maps based on the image data of other scenarios, which is used to show the quality of the construction.

Profit Based Unit Commitment of Thermal Units with Renewable Energy and Electric Vehicles in Power Market

In restructured power system, Generation Companies (GENCOs) has an opportunity to sell power and reserve in power market to earn profit by market clearing process. Defining unit commitment problem in a competitive environment to maximize the profit of GENCOs while satisfying all the network constraints is called Profit Based Unit Commitment problem (PBUC). The main contribution of this paper is modeling and inclusion of Market Clearing Price (MCP) in PBUC problem. In Day market, MCP is determined by market operator which provides maximum social welfare for both GENCOs and Consumers.On other hand this paper proposes a novel combination of solution methodology: Improved Pre-prepared power demand (IPPD) table and Analytical Hierarchy method (AHP) for solving the optimal day ahead scheduling problem as an another contribution. In this method, the status of unit commitment is obtained by IPPD table and AHP provides an optimal solution to PBUC problem. Minimizing total operating cost of thermal units to provide maximum profit to GENCOs is called an optimal day ahead scheduling problem. Also it will be more realistic to redefine this problem to include multiple distributed resources and Electric vehicles with energy storage. Because of any uncertainties or fluctuation of renewable energy resources (RESs), Electric vehicles (EV) can be used as load, energy sources and energy storage. This would reduce cost, emission and to improve system power quality and reliability. So output power of solar (PS), wind output power (PW) and Electric Vehicles power (PEV) are modeled and included into day ahead scheduling problem.The proposed methodology is tested on a standard thermal unit system with or without RESs and EVs. Cost and emission reduction in a smart grid by maximum utilization of EVs and RESs are presented in this literature. It is indicated that the proposed method provides maximum profit to GENCOs when compared to other methodologies such as Memory Management Algorithm, Improved Particle Swarm Optimization (PSO), Muller method, Gravitational search algorithm etc.

An expert system for checking the correctness of memory systems using simulation and metamorphic testing

During the last few years, computer performance has reached a turning point where computing power is no longer the only important concern. This way, the emphasis is shifting from an exclusive focus on the optimisation of the computing system to optimising other systems, like the memory system. Broadly speaking, testing memory systems entails two main challenges: the oracle problem and the reliable test set problem. The former consists in deciding if the outputs of a test suite are correct. The latter refers to providing an appropriate test suite for determining the correctness of the system under test.In this paper we propose an expert system for checking the correctness of memory systems. In order to face these challenges, our proposed system combines two orthogonal techniques – simulation and metamorphic testing – enabling the automatic generation of appropriate test cases and deciding if their outputs are correct. In contrast to conventional expert systems, our system includes a factual database containing the results of previous simulations, and a simulation platform for computing the behaviour of memory systems. The knowledge of the expert is represented in the form of metamorphic relations, which are properties of the analysed system involving multiple inputs and their outputs. Thus, the main contribution of this work is two-fold: a method to automatise the testing process of memory systems, and a novel expert system design focusing on increasing the overall performance of the testing process.To show the applicability of our system, we have performed a thorough evaluation using 500 memory configurations and 4 different memory management algorithms, which entailed the execution of more than one million of simulations. The evaluation used mutation testing, injecting faults in the memory management algorithms. The developed expert system was able to detect over 99% of the critical injected faults, hence obtaining very promising results, and outperforming other standard techniques like random testing.

Design and analysis of a parallel hybrid memory architecture for per-flow buffering in high-speed switches and routers

The network switches and routers require both high-speed and large-capacity packet buffers. However, existing packet buffer architectures have the problems of speed scaling and flow number scaling limitations. To address the two problems simultaneously, this paper proposes a parallel hybrid SRAM/DRAM architecture for per-flow buffering in high-speed switches and routers. Tail SRAM and head SRAM are used to apply per-flow buffering for packet aggregation, so that the middle DRAM is accessed in a larger granularity and the DRAM's bandwidth utilization is improved. To mitigate the flow number scaling limitation, a dynamic memory allocation with hard timeout (DMA-HT) memory management algorithm is designed. The key idea of DMA-HT is that the memory space is dynamically allocated for the newly arrived flows, and a hard timeout is assigned for each queue. After a specific period of time, the memory space is freed, so that the SRAM space is efficiently utilized by the most recently active flows. A queuing system is used to model the proposed method, and theoretical analysis is performed to optimize the timeout value. With the derived formulas, multiple performance parameters are quantitatively analyzed, and the optimal timeout can be obtained. Both numerical results and simulations show that the proposed architecture can and reduce packet loss rate and average delay significantly compared with previous solutions with the same SRAM capacity.

Constructing an Efficient Model to Inspire Design Education Sustainability in Rural Areas

Advancements of information and communication technologies, as well as the reduction of computer prices, have brought computer-assisted design from applications by large manufacturers to education. The number of computer-assisted learning activities and research projects in developing countries and rural areas has been on the rise over recent years. However, there are very few studies focused on the design education of rural areas. Understandably, it is critical to establish a fundamental environment integrating design education and constructing an efficiently model to inspire design education sustainability in rural areas. By considering limited resources and the educational milieu prevalent in rural areas, this paper constructed a central kitchen model anchored in teaching equipment of design education and designed an algorithm for supporting the operation of this model efficiently. We analyzed the core algorithm MMAFS (A Memory Management Algorithm with Fast Speed) of model and comparing the MMAFS algorithm with the current popular Segregated lists algorithm and the Buddy algorithm by adopting the comparative analysis method, also demonstrated the feasibility of this central kitchen model through a case study. Given the large number of urgent and unresolved issues in developing countries and rural areas, it is essential to emphasize design education and encourage local design education specifically for rural communities and promoting a positive loop in the rural ecology through local designs.

A Study on Garbage Collection Algorithms for Big Data Environments

The need to process and store massive amounts of data—Big Data—is a reality. In areas such as scientific experiments, social networks management, credit card fraud detection, targeted advertisement, and financial analysis, massive amounts of information are generated and processed daily to extract valuable, summarized information. Due to its fast development cycle (i.e., less expensive to develop), mainly because of automatic memory management, and rich community resources, managed object-oriented programming languages (e.g., Java) are the first choice to develop Big Data platforms (e.g., Cassandra, Spark) on which such Big Data applications are executed. However, automatic memory management comes at a cost. This cost is introduced by the garbage collector, which is responsible for collecting objects that are no longer being used. Although current (classic) garbage collection algorithms may be applicable to small-scale applications, these algorithms are not appropriate for large-scale Big Data environments, as they do not scale in terms of throughput and pause times. In this work, current Big Data platforms and their memory profiles are studied to understand why classic algorithms (which are still the most commonly used) are not appropriate, and also to analyze recently proposed and relevant memory management algorithms, targeted to Big Data environments. The scalability of recent memory management algorithms is characterized in terms of throughput (improves the throughput of the application) and pause time (reduces the latency of the application) when compared to classic algorithms. The study is concluded by presenting a taxonomy of the described works and some open problems, with regard to Big Data memory management, that could be addressed in future works.

An FPGA-Based High-Speed Error Resilient Data Aggregation and Control for High Energy Physics Experiment

Due to the dramatic increase of data volume in modern high energy physics (HEP) experiments, a robust high-speed data acquisition (DAQ) system is very much needed to gather the data generated during different nuclear interactions. As the DAQ works under harsh radiation environment, there is a fair chance of data corruption due to various energetic particles like alpha, beta, or neutron. Hence, a major challenge in the development of DAQ in the HEP experiment is to establish an error resilient communication system between front-end sensors or detectors and back-end data processing computing nodes. Here, we have implemented the DAQ using field-programmable gate array (FPGA) due to some of its inherent advantages over the application-specific integrated circuit. A novel orthogonal concatenated code and cyclic redundancy check (CRC) have been used to mitigate the effects of data corruption in the user data. Scrubbing with a 32-b CRC has been used against error in the configuration memory of FPGA. Data from front-end sensors will reach to the back-end processing nodes through multiple stages that may add an uncertain amount of delay to the different data packets. We have also proposed a novel memory management algorithm that helps to process the data at the back-end computing nodes removing the added path delays. To the best of our knowledge, the proposed FPGA-based DAQ utilizing optical link with channel coding and efficient memory management modules can be considered as first of its kind. Performance estimation of the implemented DAQ system is done based on resource utilization, bit error rate, efficiency, and robustness to radiation.

Reverse engineering a Java Card memory management algorithm

Smart cards are tamper resistant devices that manipulate assets in a secure way. Among the assets, one is of a particular interest the native layers. If some attacks have succeeded in getting access to the applicative layer very few of them have had access to the native layers. We propose here to use applicative programs to perform data reverse engineering in order to understand the hidden algorithms that manage the memory allocation. We are then able to generate our own fake references on objects that can be manipulated by the system as legal objects. Then, we propose a new attack called auto-forges that leads the system to interpret its own data or program as valid Java meta data. This attack provides access to new memory fragments where the native layers are stored. Getting access to this asset allows us to start the reverse engineering of these native layers.

Optimizing Memory Usage in L4-Based Microkernel

Memory allocation is a critical aspect of any modern operating system kernel because it must run continuously for long periods of time, therefore memory leaks and inefficiency must be eliminated. This paper presents different memory management algorithms and their aplicability to an L4-based microkernel. We aim to reduce memory usage and increase the performance of allocation and deallocation of memory.

User-Assisted Store Recycling for Dynamic Task Graph Schedulers

The emergence of the multi-core era has led to increased interest in designing effective yet practical parallel programming models. Models based on task graphs that operate on single-assignment data are attractive in several ways. Notably, they can support dynamic applications and precisely represent the available concurrency. However, for efficient execution, they also require nuanced algorithms for scheduling and memory management. In this article, we consider memory-efficient dynamic scheduling of task graphs. Specifically, we present a novel approach for dynamically recycling the memory locations assigned to data items as they are produced by tasks. We develop algorithms to identify memory-efficient store recycling functions by systematically evaluating the validity of a set of user-provided or automatically generated alternatives. Because recycling functions can be input data-dependent, we have also developed support for continued correct execution of a task graph in the presence of a potentially incorrect store recycling function. Experimental evaluation demonstrates that this approach to automatic store recycling incurs little to no overheads, achieves memory usage comparable to the best manually derived solutions, often produces recycling functions valid across problem sizes and input parameters, and efficiently recovers from an incorrect choice of store recycling functions.

On efficient data storage service for IoT

SummaryThe increasing popularity of Internet of Things (IoT) services causes tremendous growth of the amount of produced data. These data must be effectively stored and retrieved by the IoT service providers. The solution is to access the data through application programming interfaces. The paper focuses on the problem of designing an effective data storage service for IoT, which will be available through the universal application programming interface. We propose and analyze eight variants of the distributed data storage service that differ in the database structure, that is, the hierarchical structure based on Data‐Oriented Network Architecture or the flat structure based on distributed hash table, the type of stored records, and the memory management algorithm that decides about using cache or base memory. The proposed solutions have been evaluated in the comprehensive simulation studies. The obtained results confirmed the effectiveness of the preferred solution with Dynamic Routing Records stored in the cache memory. Copyright © 2016 John Wiley & Sons, Ltd.

User-assisted storage reuse determination for dynamic task graphs

Models based on task graphs that operate on single-assignment data are attractive in several ways, but also require nuanced algorithms for scheduling and memory management for efficient execution. In this paper, we consider memory-efficient dynamic scheduling of task graphs, and present a novel approach for dynamically recycling the memory locations assigned to data items as they are produced by tasks.

Area-Efficient Near-Associative Memories on FPGAs

Associative memories can map sparsely used keys to values with low latency but can incur heavy area overheads. The lack of customized hardware for associative memories in today’s mainstream FPGAs exacerbates the overhead cost of building these memories using the fixed address match BRAMs. In this article, we develop a new, FPGA-friendly, memory system architecture based on a multiple hash scheme that is able to achieve near-associative performance without the area-delay overheads of a fully associative memory on FPGAs. At the same time, we develop a novel memory management algorithm that allows us to statistically mimic an associative memory. Using the proposed architecture as a 64KB L1 data cache, we show that it is able to achieve near-associative miss rates while consuming 3--13 × fewer FPGA memory resources for a set of benchmark programs from the SPEC CPU2006 suite than fully associative memories generated by the Xilinx Coregen tool. Benefits for our architecture increase with key width, allowing area reduction up to 100 ×. Mapping delay is also reduced to 3.7ns for a 1,024-entry flat version or 6.1ns for an area-efficient version compared to 17.6ns for a fully associative memory for a 64-bit key on a Xilinx Virtex 6 device.