Memory Error Rates Research Articles

HBM3 RAS: Enhancing Resilience at Scale

HBM3 is the next-generation technology in the JEDEC High Bandwidth Memory™ die-stacked DRAM standard. HBM3 is expected to be widely used in future SoCs to accelerate data center and automotive workloads. Reliability, Availability, and Serviceability (RAS) are key requirements in most of these computing domains and use cases. Memory reliability is especially key to attaining resilience at scale. This paper presents the RAS challenges facing HBM3 and how they are addressed by a novel memory RAS architecture that is now part of the HBM3 standard. The paper shows how this novel HBM3 RAS architecture can reduce the uncorrected memory error rate by 7X compared to HBM2 in future large-scale systems for assumed DRAM fault rates and modes <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">.</i> HBM3 also provides architected metadata to further enhance RAS or enable innovations in memory system design.

E2CNNs: Ensembles of Convolutional Neural Networks to Improve Robustness Against Memory Errors in Edge-Computing Devices

To reduce energy consumption, it is possible to operate embedded systems at sub-nominal conditions (e.g., reduced voltage, limited eDRAM refresh rate) that can introduce bit errors in their memories. These errors can affect the stored values of convolutional neural network (CNN) weights and activations, compromising their accuracy. In this article, we introduce Embedded Ensemble CNNs (E <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> CNNs), our architectural design methodology to conceive ensembles of convolutional neural networks to improve robustness against memory errors compared to a single-instance network. Ensembles of CNNs have been previously proposed to increase accuracy at the cost of replicating similar or different architectures. Unfortunately, state-of-the-art (SoA) ensembles do not suit well embedded systems, in which memory and processing constraints limit the number of deployable models. Our proposed architecture solves that limitation applying SoA compression methods to produce an ensemble with the same memory requirements of the original architecture, but with improved error robustness. Then, as part of our new E <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> CNNs design methodology, we propose a heuristic method to automate the design of the voter-based ensemble architecture that maximizes accuracy for the expected memory error rate while bounding the design effort. To evaluate the robustness of E <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> CNNs for different error types and densities, and their ability to achieve energy savings, we propose three error models that simulate the behavior of SRAM and eDRAM operating at sub-nominal conditions. Our results show that E <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> CNNs achieves energy savings of up to 80 percent for LeNet-5, 90 percent for AlexNet, 60 percent for GoogLeNet, 60 percent for MobileNet and 60 percent for an optimized industrial CNN, while minimizing the impact on accuracy. Furthermore, the memory size can be decreased up to 54 percent by reducing the number of members in the ensemble, with a more limited impact on the original accuracy than obtained through pruning alone.

Research on 3D TLC NAND flash reliability from the perspective of threshold voltage distribution

Aiming at the inaccurate problems of lifetime prediction and reliability evaluation of 3D Trinary-Level Cell (TLC) NAND flash memory, a method to evaluate the remaining lifetime and the reliability of flash memory based on the threshold voltage distribution is proposed. In order to analyze the impact on Program/Erase (P/E) cycles on the flash memory from the perspective of voltage distribution, a complete distribution curve of threshold voltage is drawn from the construction of a reasonable mathematical model. Compared with the conventional used curve of P/E cycles-error rate, it reflects the most concentrated part of the flash memory error rate and makes lifetime prediction more accurate.

High-Energy Versus Thermal Neutron Contribution to Processor and Memory Error Rates

We present the results of accelerated radiation testing on an AMD accelerated processing unit, three Nvidia graphic processing units, an Intel accelerator, a field-programmable gate array, and two double-data-rate memories under thermal and high-energy neutrons separately. The sensitivity depends on the device type and the code being executed and we show that thermal neutrons contribute to the error rate of modern computing devices under certain conditions.

Large Scale Studies of Memory, Storage, and Network Failures in a Modern Data Center

The workloads running in the modern data centers of large scale Internet service providers (such asAlibaba, Amazon, Baidu, Facebook, Google, and Microsoft) support billions of users and span globallydistributed infrastructure. Yet, the devices used in modern data centers fail due to a variety of causes, fromfaulty components to bugs to misconfiguration. Faulty devices make operating large scale data centerschallenging because the workloads running in modern data centers consist of interdependent programsdistributed across many servers, so failures that are isolated to a single device can still have a widespreadeffect on a workload.In this dissertation, we measure and model the device failures in a large scale Internet service company,Facebook. We focus on three device types that form the foundation of Internet service data centerinfrastructure: DRAM for main memory, SSDs for persistent storage, and switches and backbone linksfor network connectivity. For each of these device types, we analyze long term device failure data brokendown by important device attributes and operating conditions, such as age, vendor, and workload. Wealso build and release statistical models of the failure trends for the devices we analyze.For DRAM devices, we analyze the memory errors in the entire fleet of servers at Facebook over thecourse of fourteen months, representing billions of device days of operation. The systems we examinecover a wide range of devices commonly used in modern servers, with DIMMs that use the modernDDR3 communication protocol, manufactured by 4 vendors in capacities ranging from 2GB to 24GB.We observe several new reliability trends for memory systems that have not been discussed before inliterature, develop a model for memory reliability, show how system design choices such as using lowerdensity DIMMs and fewer cores per chip can reduce failure rates of a baseline server by up to 57.7%.We perform the first implementation and real-system analysis of page offlining at scale, on a cluster ofthousands of servers, identify several real-world impediments to the technique, and show that it canreduce memory error rate by 67%. We also examine the efficacy of a new technique to reduce DRAMfaults, physical page randomization, and examine its potential for improving reliability and its overheads.For SSD devices, we perform a large scale study of flash-based SSD reliability at Facebook. We analyzedata collected across a majority of flash-based solid state drives over nearly four years and manymillions of operational hours in order to understand failure properties and trends of flash-based SSDs.Our study considers a variety of SSD characteristics, including: the amount of data written to and readfrom flash chips; how data is mapped within the SSD address space; the amount of data copied, erased,and discarded by the flash controller; and flash board temperature and bus power. Based on our fieldanalysis of how flash memory errors manifest when running modern workloads on modern SSDs, we make several major observations and find that SSD failure rates do not increase monotonically with flashchip wear, but instead they go through several distinct periods corresponding to how failures emerge andare subsequently detected.For network devices, we perform a large scale, longitudinal study of data center network reliabilitybased on operational data collected from the production network infrastructure at Facebook. Our studycovers reliability characteristics of both intra and inter data center networks. For intra data center networks,we study seven years of operation data comprising thousands of network incidents across twodifferent data center network designs, a cluster network design and a state-of-the-art fabric network design.For inter data center networks, we study eighteen months of recent repair tickets from the field tounderstand the reliability of Wide Area Network (WAN) backbones. In contrast to prior work, we studythe effects of network reliability on software systems, and how these reliability characteristics evolve overtime. We discuss the implications of network reliability on the design, implementation, and operation oflarge scale data center systems and how the network affects highly-available web services.Our key conclusion in this dissertation is that we can gain a deep understanding of why devicesfail—and how to predict their failure—using measurement and modeling. We hope that the analysis,techniques, and models we present in this dissertation will enable the community to better measure,understand, and prepare for the hardware reliability challenges we face in the future.

Noise threshold for a fault-tolerant two-dimensional lattice architecture

We consider a model of quantum computation in which the set of operations is limited to nearest-neighbor interactions on a 2D lattice. We model movement of qubits with noisy SWAP operations. For this architecture we design a fault-tolerant coding scheme using the concatenated [7, 1, 3] Steane code. Our scheme is potentially applicable to ion-trap and solid-state quantum technologies. We calculate a lower bound on the noise threshold for our local model using a detailed failure probability analysis. We obtain a threshold of 1.85×10-5 for the local setting, where memory error rates are one-tenth of the failure rates of gates, measurement, and preparation steps. For the analogous nonlocal setting, we obtain a noise threshold of 3.61 × 10-5. Our results thus show that the additional SWAP operations required to move qubits in the local model affect the noise threshold only moderately.

Neonatal exposure to BDE 209 impaired learning and memory, decreased expression of hippocampal core SNAREs and synaptophysin in adult rats

Polybrominated diphenyl ethers (PBDEs) are a class of flame retardants. While the mechanism remains unknown, the potential neurotoxic effects of PBDEs remain a relevant issue. In the present study, neonatal Sprague-Dawley rats of both sexes were administered BDE 209 (1, 10, or 20mg/kg body weight) or peanut oil once daily from postnatal day (PND) 5 to PND 10. We examined the spatial learning and memory by Morris water maze and the working and reference memory by eight-arm radial maze in the stage of adulthood. Compared with controls, significantly longer escape latencies and fewer platform-crossings in the Morris water maze were observed in rats exposed to 1, 10, and 20mg/kg BDE 209, and these effects were dose-dependent. Significantly higher working and reference memory error rates in the eight-arm radial maze were also observed in rats exposed to 10 and 20mg/kg BDE 209. Furthermore, we detected the mRNA and protein expressions of hippocampal synaptobrevin 2, syntaxin 1A, Synaptosome Associated Protein 25 (SNAP-25), and synaptophysin using quantitative reverse transcription-polymerase chain reaction (qRT-PCR) and western blot methods. Compared with controls, the mRNA expressions of synaptobrevin 2, syntaxin 1A, SNAP-25, and synaptophysin were significantly decreased in the hippocampi of rats exposed to 1, 10, and 20 mg/kg BDE 209, and the protein expressions of synaptobrevin 2 and SNAP-25 were significantly decreased in the hippocampi of rats exposed to 10 and 20 mg/kg BDE 209, while syntaxin 1A and synaptophysin were significantly decreased in rats exposed to 1, 10, and 20 mg/kg BDE 209. Alterations that may be involved in the learning and memory deficits induced by BDE 209 reveal the possibility of synapse loss.

Energy Barrier Model of SRAM for Improved Energy and Error Rates

We propose an energy barrier model of Static Random Access Memory (SRAM). The model provides useful insights about memory error rates for write, read, and retention. We introduce the concept of intrinsic energy margin induced write failure. The proposed model is employed for evaluating various write and read assist mechanisms and their potential in modulating the memory failures. Our analysis reveals that this model is very effective in predicting the behavior of SRAM stability and can be used as a tool to expedite the early phases of design to build assist circuits. Additionally, it can also be used to optimize energy dissipation of SRAM cache.

Performance and error analysis of Knill's postselection scheme in a two-dimensional architecture

Knill demonstrated a fault-tolerant quantum computation scheme based on concatenated error-detecting codes and postselection with a simulated error threshold of $3\%$ over the depolarizing channel. We show how to use Knill's postselection scheme in a practical two-dimensional quantum architecture that we designed with the goal to optimize the error correction properties, while satisfying important architectural constraints. In our 2D architecture, one logical qubit is embedded in a tile consisting of $5\times 5$ physical qubits. The movement of these qubits is modeled as noisy SWAP gates and the only physical operations that are allowed are local one- and two-qubit gates. We evaluate the practical properties of our design, such as its error threshold, and compare it to the concatenated Bacon-Shor code and the concatenated Steane code. Assuming that all gates have the same error rates, we obtain a threshold of $3.06\times 10^{-4}$ in a local adversarial stochastic noise model, which is the highest known error threshold for concatenated codes in 2D. We also present a Monte Carlo simulation of the 2D architecture with depolarizing noise and we calculate a pseudo-threshold of about $0.1\%$. With memory error rates one-tenth of the worst gate error rates, the threshold for the adversarial noise model, and the pseudo-threshold over depolarizing noise, are $4.06\times 10^{-4}$ and $0.2\%$, respectively. In a hypothetical technology where memory error rates are negligible, these thresholds can be further increased by shrinking the tiles into a $4\times 4$ layout.

Effect of beef consumption on body iron and cognitive function in iron‐deficient women

Iron depletion is associated with cognitive impairment in women of reproductive age. This project investigates the effect of moderate beef intake on total body iron and cognitive function in university undergraduate women. At baseline, women (n=17) were classified by body iron tertile and randomly assigned to a beef or nonbeef meat lunch group (85 g, 3x weekly) for 16 weeks. Computerized neurocognitive tests were administered at baseline and week 16. Changes in calculated body iron and cognitive performance from baseline to endpoint were analyzed using generalized linear models and Spearman correlations. Women in the 1st (lowest) vs. 2nd and 3rd iron tertile responded to either lunch intervention with significant increases in body iron (ANOVA, P&lt;0.01) and significant improvements in tests of spatial working memory (decrease in errors and improvement in strategy, P&lt;0.05). Change in body iron was inversely associated with change in spatial working memory error rate (r=−0.49; P&lt;0.05). These preliminary findings suggest that working memory improves in association with increased iron status in iron‐deficient women consuming moderate amounts of beef or nonbeef meat. Funded by the Idaho Beef Council.

Noise threshold for a fault-tolerant two-dimensional lattice architecture

We consider a model of quantum computation in which the set of operations is limited to nearest-neighbor interactions on a 2D lattice. We model movement of qubits with noisy \SWAP\ operations. For this architecture we design a fault-tolerant coding scheme using the concatenated $[[7,1,3]]$ Steane code. Our scheme is potentially applicable to ion-trap and solid-state quantum technologies. We calculate a lower bound on the noise threshold for our local model using a detailed failure probability analysis. We obtain a threshold of $1.85 \times 10^{-5}$ for the local setting, where memory error rates are one-tenth of the failure rates of gates, measurement, and preparation steps. For the analogous nonlocal setting, we obtain a noise threshold of $3.61 \times 10^{-5}$. Our results thus show that the additional \SWAP\ operations required to move qubits in the local model affect the noise threshold only moderately.

Training Pilots to Prioritize Tasks

The purpose of this study was to develop and evaluate the effectiveness of a technique to help pilots prioritize tasks. A part-task simulator experiment was conducted in which three groups of general aviation pilot participants flew pre-and post-training flights. Participants in two groups received task prioritization training between the flights while those in a control group did not. Task prioritization error rates and prospective memory error rates from pre-and post-training flights were compared. Task prioritization and memory error rates improved in the training groups and did not improve in the control group. However, these findings must be considered preliminary, as several issues remain to be resolved by follow-on studies.

Interactions between the effects of propranolol and nicotine on radial maze performance of rats with lesions of the forebrain cholinergic projection system.

This experiment investigated the hypothesis that nicotine-induced regional release of noradrenaline contributes to the improvements in radial maze performance following nicotine treatment in rats with lesions to the forebrain cholinergic projection system (FCPS), by examining whether pretreatment with the noradrenergic beta-receptor antagonist propranolol abolished the facilitative effects of nicotine. After S-AMPA (8.0mM) lesions to the nuclei of origin of the FCPS in the nucleus basalis and medial septal areas, rats displayed long-lasting impairment in long-term reference and short-term working memory in both spatial (place) and associative (cue) radial maze tasks. Performance of control and lesioned rats was assessed after administration of nicotine (0.1mg/kg), propranolol (either 0.5 or 5.0mg/kg) and both treatments. Nicotine reduced working memory error rates in lesioned animals, but did not affect the performance of controls. Propranolol dose-relatedly increased error rates in both control and lesioned animals. Adverse effects were more marked in controls, all four types of error being increased under the high dose of propranolol, whereas in lesioned rats significant increases in error rates above baseline were confined to working memory. The low dose of propranolol, in conjunction with nicotine, abolished the improvement in working memory seen with nicotine alone in lesioned rats. However, under joint treatment with the high dose, the substantial increases in working memory error rates seen in lesioned rats after propranolol alone were reduced to baseline level. In controls, reduction in errors to baseline was seen only in the cue task; place task errors remained significantly elevated. These results suggest that both cholinergic depletion and noradrenergic blockade exert disruptive effects on cognition, but that these effects are largely independent, since an additive or interactive mechanism would be predicted to produce greater disruption, following noradrenergic blockade, in lesioned rather than in control animals. Although facilitative effects of nicotine were abolished with the low dose of propranolol, the results further suggest that these effects are independent of release of noradrenaline, since nicotine continued to reduce errors in control and lesioned animals following blockade of beta receptors with the high dose of propranolol.