Memory Benchmarks Research Articles

A sensitivity analysis of cellular automata and heterogeneous topology networks: partially-local cellular automata and homogeneous homogeneous random boolean networks

ABSTRACT Elementary Cellular Automata (ECA) are well-studied computational universes capable of impressive computational variety, but harnessing their potential has been challenging. When combined with Reservoir Computing (RC), harnessing this computation becomes feasible, and furthermore enables energy efficient AI. This study compares ECA reservoirs to topological heterogeneous and more biological plausible counterparts of Partially-Local CA (PLCA) and Homogeneous Homogeneous Random Boolean Networks (HHRBN). Using the 5-bit memory benchmark, Temporal Derrida plots and collapse rate, finding are that more disordered topology does not equate to more disordered computation and moreover the evidence suggest this heterogeneity shrinks the critical range.

Investigating Rules and Parameters of Reservoir Computing with Elementary Cellular Automata, with a Criticism of Rule 90 and the Five-Bit Memory Benchmark

Reservoir computing with cellular automata (ReCAs) is a promising concept by virtue of its potential for effective hardware implementation. In this paper, we explore elementary cellular automata rules in the context of ReCAs and the 5-bit memory benchmark. We combine elementary cellular automaton theory with our results and use them to identify and explain some of the patterns found. Furthermore, we use these findings to expose weaknesses in the 5-bit memory benchmark as it is typically applied in ReCAs, such as pointing out what features it selects for or solving it using random vectors. We look deeply into previously successful rules in ReCAs such as rule 90 and explain some of the consequences of its additive properties as well as the correlation between grid size and performance. Additionally, we present results from exhaustively exploring ReCAs on key parameters such as distractor period, iterations and grid size. The findings of this paper should motivate the ReCAs community to move away from using the 5-bit memory benchmark as it is being applied today.

Context-Aware Resiliency: Unequal Message Protection for Random-Access Memories

A common way to protect data stored in DRAM and related memory systems is through the use of an error-correcting code such as the extended Hamming code. Traditionally, these error-correcting codes provide equal protection guarantees to all messages. In this paper, we focus on unequal message protection (UMP), in which a subset of messages is deemed as special, and is afforded additional error-correction protection while maintaining the same number of redundancy bits as the baseline code. UMP is a powerful approach when the special messages are chosen based on the knowledge of data patterns in context. Our objective is to construct deterministic, algebraic codes with guaranteed UMP properties, derive their cardinality bounds using novel combinatorial techniques, and to demonstrate their efficacy for realistic memory benchmarks. We first introduce a UMP alternative to the single-bit parity-check code, and then we generalize to a broader UMP code family, including a UMP alternative to the extended Hamming code, offering full double-error correction protection to special messages. Our UMP constructions, applied to main memory in high-performance computing applications, could lead to significant system-level benefits such as less frequent checkpoints in supercomputers and decreased risk of catastrophic failure from erroneous special messages.

Neuroevolution of a Modular Memory-Augmented Neural Network for Deep Memory Problems.

We present Modular Memory Units (MMUs), a new class of memory-augmented neural network. MMU builds on the gated neural architecture of Gated Recurrent Units (GRUs) and Long Short Term Memory (LSTMs), to incorporate an external memory block, similar to a Neural Turing Machine (NTM). MMU interacts with the memory block using independent read and write gates that serve to decouple the memory from the central feedforward operation. This allows for regimented memory access and update, giving our network the ability to choose when to read from memory, update it, or simply ignore it. This capacity to act in detachment allows the network to shield the memory from noise and other distractions, while simultaneously using it to effectively retain and propagate information over an extended period of time. We train MMU using both neuroevolution and gradient descent, and perform experiments on two deep memory benchmarks. Results demonstrate that MMU performs significantly faster and more accurately than traditional LSTM-based methods, and is robust to dramatic increases in the sequence depth of these memory benchmarks.

3D Tomography Back-Projection Parallelization on Intel FPGAs Using OpenCL

This article deals with the evaluation of FPGAs resurgence for hardware acceleration applied to computed tomography on the back-projection operator used in iterative reconstruction algorithms. We focus our attention on the tools developed by FPGAs manufacturers, in particular the Intel FPGA SDK for OpenCL, that promises a new level of hardware abstraction from the developers perspective, allowing a software-like programming of FPGAs. Our first contribution is to propose an accurate memory benchmark, and we follow with an evaluation of different custom OpenCL implementations of the back- projection algorithm. With some clues on memory fetching and coalescing, we then further tune designs to improve performance. Finally, a comparison is made with GPU implementations, and a preliminary conclusion is drawn on FPGAs future for computed tomography.

Working memory benchmarks-A missed opportunity: Comment on Oberauer et al. (2018).

This commentary addresses a number of problems with the benchmarks proposed for evaluating theories of short-term and working memory (Oberauer et al., 2018). First, it is shown that the proposed benchmarks intentionally exclude findings regarding the core of the working memory construct and also miss some important findings from other subdomains. For these reasons, the benchmarks cannot be considered as a valid representation of the findings on short-term and working memory. Second, it is shown that although theory-neutrality of the benchmarks was aimed for, this goal was not achieved because theory-neutrality in the formulation of the benchmarks does not guarantee inclusion of all theory-dependent findings. For these reasons, the benchmarks miss their purpose and are defined in such a way as to encourage a future theory development that studies working memory in isolation from other cognitive activities and thus misses the opportunity to stimulate a better integrative understanding of working memory in the broader context of cognition. (PsycINFO Database Record

Evaluating ARM HPC clusters for scientific workloads

SummaryThe power consumption of modern high‐performance computing (HPC) systems that are built using power hungry commodity servers is one of the major hurdles for achieving Exascale computation. Several efforts have been made by the HPC community to encourage the use of low‐powered system‐on‐chip (SoC) embedded processors in large‐scale HPC systems. These initiatives have successfully demonstrated the use of ARM SoCs in HPC systems, but there is still a need to analyze the viability of these systems for HPC platforms before a case can be made for Exascale computation. The major shortcomings of current ARM‐HPC evaluations include a lack of detailed insights about performance levels on distributed multicore systems and performance levels for benchmarking in large‐scale applications running on HPC. In this paper, we present a comprehensive evaluation of results that covers major aspects of server and HPC benchmarking for ARM‐based SoCs. For the experiments, we built an unconventional cluster of ARM Cortex‐A9s that is referred to as Weiser and ran single‐node benchmarks (STREAM, Sysbench, and PARSEC) and multi‐node scientific benchmarks (High‐performance Linpack (HPL), NASA Advanced Supercomputing (NAS) Parallel Benchmark, and Gadget‐2) in order to provide a baseline for performance limitations of the system. Based on the experimental results, we claim that the performance of ARM SoCs depends heavily on the memory bandwidth, network latency, application class, workload type, and support for compiler optimizations. During server‐based benchmarking, we observed that when performing memory intensive benchmarks for database transactions, x86 performed 12% better for multithreaded query processing. However, ARM performed four times better for performance to power ratios for a single core and 2.6 times better on four cores. We noticed that emulated double precision floating point in Java resulted in three to four times slower performance as compared with the performance in C for CPU‐bound benchmarks. Even though Intel x86 performed slightly better in computation‐oriented applications, ARM showed better scalability in I/O bound applications for shared memory benchmarks. We incorporated the support for ARM in the MPJ‐Express runtime and performed comparative analysis of two widely used message passing libraries. We obtained similar results for network bandwidth, large‐scale application scaling, floating‐point performance, and energy‐efficiency for clusters in message passing evaluations (NBP and Gadget 2 with MPJ‐Express and MPICH). Our findings can be used to evaluate the energy efficiency of ARM‐based clusters for server workloads and scientific workloads and to provide a guideline for building energy‐efficient HPC clusters. Copyright © 2015 John Wiley & Sons, Ltd.

Effectiveness of Mindful Meditation on Attention, Short Term Memory and Visual Reaction Time on Normal Individual

Background of the study: People who have undergone extensive meditation have shown improvement on cognitive performance .It does this by training and bringing mental processes under greater voluntary control and direction them in beneficial ways. This study was designed with the purpose to observe the effectiveness of mindful meditation on attention, short term memory and visual reaction time on normal individual. We examined whether brief mindfulness training affects on cognition. Our findings suggest that two weeks of meditation training can enhance the ability to sustain attention, short term memory and visual reaction time on normal individual. Purpose of the study: To examine whether brief mindful training affects on attention.short term memory and visual reaction time on normal indivisual. Procedure: A total no. of 230 subjects age group(15-25) were taken for the study. Pre evaluation has been done by using Trail making test, Digit span test and Human Benchmark test. Trail making test for attention, Digit span test for short term memory and Human Benchmark test for visual reaction time. These test were carried out to the subjects for pre and post Evaluation. Mindful meditation was provided to subjects for 15 minutes once a day for two weeks. Subject were made to sit comfortably on a mat and asked them to take a deep breath before meditation. Each subject is given a mantra (OM) and is instructed to concentrate through this mantra(OM). Results: The data was statically analyzed by using SPSS software. There is overall increased attention, increase short term memory and decrease reaction time were shown. The P- Value of TMTA1-TMTA2- .000 , TMTB1-TMTB2- .000 , RT1-RT2 - .007 , DTI-DT2 -.000 . The value is < .05 as seen in table-3 so this study accepts the alternate hypothesis. Conclusion: Our findings suggests that two weeks of meditation training can enhance the ability to sustain Attention ,Short term Memory and visual reaction time on normal individual.

Performance modeling of hybrid MPI/OpenMP scientific applications on large-scale multicore supercomputers

In this paper, we present a performance modeling framework based on memory bandwidth contention time and a parameterized communication model to predict the performance of OpenMP, MPI and hybrid applications with weak scaling on three large-scale multicore supercomputers: IBM POWER4, POWER5+ and BlueGene/P, and analyze the performance of these MPI, OpenMP and hybrid applications. We use STREAM memory benchmarks and Intelʼs MPI benchmarks to provide initial performance analysis and model validation of MPI and OpenMP applications on these multicore supercomputers because the measured sustained memory bandwidth can provide insight into the memory bandwidth that a system should sustain on scientific applications with the same amount of workload per core. In addition to using these benchmarks, we also use a weak-scaling hybrid MPI/OpenMP large-scale scientific application: Gyrokinetic Toroidal Code (GTC) in magnetic fusion to validate our performance model of the hybrid application on these multicore supercomputers. The validation results for our performance modeling method show less than 7.77% error rate in predicting the performance of hybrid MPI/OpenMP GTC on up to 512 cores on these multicore supercomputers.

Employing NeuGen 2.0 to Automatically Generate Realistic Morphologies of Hippocampal Neurons and Neural Networks in 3D

Detailed cell and network morphologies are becoming increasingly important in Computational Neuroscience. Great efforts have been undertaken to systematically record and store the anatomical data of cells. This effort is visible in databases, such as NeuroMorpho.org. In order to make use of these fast growing data within computational models of networks, it is vital to include detailed data of morphologies when generating those cell and network geometries. For this purpose we developed the Neuron Network Generator NeuGen 2.0, that is designed to include known and published anatomical data of cells and to automatically generate large networks of neurons. It offers export functionality to classic simulators, such as the NEURON Simulator by Hines and Carnevale (2003). NeuGen 2.0 is designed in a modular way, so any new and available data can be included into NeuGen 2.0. Also, new brain areas and cell types can be defined with the possibility of constructing user-defined cell types and networks. Therefore, NeuGen 2.0 is a software package that grows with each new piece of anatomical data, which subsequently will continue to increase the morphological detail of automatically generated networks. In this paper we introduce NeuGen 2.0 and apply its functionalities to the CA1 hippocampus. Runtime and memory benchmarks show that NeuGen 2.0 is applicable to generating very large networks, with high morphological detail.

Resource-bounded multicore emulation using Beefarm

In this article, we present the Beefarm infrastructure for FPGA-based multiprocessor emulation, a popular research topic of the last few years both in FPGA and computer architecture communities. We explain how we modify and extend a MIPS-based open-source soft core, we discuss various design tradeoffs to make efficient use of the bounded resources available on chip and we demonstrate superior scalability compared to traditional software instruction set simulators through experimental results running Software Transactional Memory (STM) benchmarks. Based on our experience, we comment on the pros and cons and the future trends of using hardware-based emulation for multicore research.

RMS-TM

Transactional Memory (TM) has been proposed as an alternative concurrency mechanism for the shared memory parallel programming model. Its main goal is to make parallel programming for Chip Multiprocessors (CMPs) easier than using the traditional lock synchronization constructs, without compromising the performance and the scalability. This topic has received substantial research attention and several TM designs have been proposed using various TM benchmarks. We believe that the evaluation of TM proposals would be more solid if it included realistic applications, that address on-going TM research issues, and that provide the potential for straightforward comparison against locks. In this paper, we introduce RMS-TM, a Transactional Memory benchmark suite composed of seven real-world applications from the Recognition, Mining and Synthesis (RMS) domain. In addition to featuring current TM research issues such as nesting and I/O and system calls inside transactions, the RMS-TM applications also provide a mix of short and long transactions with small/large read and write sets with low/medium/high contention rates. These characteristics, as well as providing lock-based versions of the applications, make RMS-TM a useful TM tool. Current TM benchmarks do not explore all these features. In our evaluation with selected STM and HTM systems, we find that our benchmark suite is also scalable, which is useful for evaluating TM designs on high core counts.

Performance and Scalability Evaluation of ‘Big Memory’ on Blue Gene Linux

We address memory performance issues observed in Blue Gene Linux and discuss the design and implementation of ‘Big Memory’——an alternative, transparent memory space introduced to eliminate the memory performance issues. We evaluate the performance of Big Memory using custom memory benchmarks, NAS Parallel Benchmarks, and the Parallel Ocean Program, at a scale of up to 4,096 nodes. We find that Big Memory successfully resolves the performance issues normally encountered in Blue Gene Linux. For the ocean simulation program, we even find that Linux with Big Memory provides better scalability than does the lightweight compute node kernel designed solely for high-performance applications. Originally intended exclusively for compute node tasks, our new memory subsystem dramatically improves the performance of certain I/O node applications as well. We demonstrate this performance using the central processor of the LOw Frequency ARray radio telescope as an example.

Neuroevolution and complexifying genetic architectures for memory and control tasks

The way genes are interpreted biases an artificial evolutionary system towards some phenotypes. When evolving artificial neural networks, methods using direct encoding have genes representing neurons and synapses, while methods employing artificial ontogeny interpret genomes as recipes for the construction of phenotypes. Here, a neuroevolution system (neuroevolution with ontogeny or NEON) is presented that can emulate a well-known neuroevolution method using direct encoding (neuroevolution of augmenting topologies or NEAT), and therefore, can solve the same kinds of tasks. Performance on challenging control and memory benchmark tasks is reported. However, the encoding used by NEON is indirect, and it is shown how characteristics of artificial ontogeny can be introduced incrementally in different phases of evolutionary search.

Improving the performance of software distributed shared memory with speculation

We study the performance benefits of speculation in a release consistent software distributed shared memory system. We propose a new protocol, speculative home-based release consistency (SHRC) that speculatively updates data at remote nodes to reduce the latency of remote memory accesses. Our protocol employs a predictor that uses patterns in past accesses to shared memory to predict future accesses. We have implemented our protocol in a release consistent software distributed shared memory system that runs on commodity hardware. We evaluate our protocol implementation using eight software distributed shared memory benchmarks and show that it can result in significant performance improvements.

The genesis distributed memory benchmarks. Part 2: COMMS1, TRANS1, FFT1 and QCD2 benchmarks on the suprenum and IPSC/860 computers

AbstractThe Genesis benchmark suite has been assembled to evaluate the performance of distributed‐memory MIMD systems. The problems selected all have a scientific origin (mostly from physics or theoretical chemistry), and range from synthetic code fragments designed to measure the basic hardware properties of the computer (especially communication and synchronisation overheads), through commonly used library subroutines, to full application codes. This is the second of a series of papers on the Genesis distributed‐memory benchmarks, which were developed under the European ESPRIT research program. Results are presented for the SUPRENUM and iPSC/860 computers when running the following benchmarks: COMMS1 (communications), TRANS1 (matrix transpose), FFT1 (fast Fourier transform) and QCD2 (conjugate gradient kernel). The theoretical predictions are compared with, or fitted to, the measured results, and then used to predict (with due caution) how the performance might scale for larger problems and more processors than were actually available during the benchmarking.

The genesis distributed memory benchmarks

A brief overview of the Genesis Distributed Memory Benchmark suite developed in the Esprit-2 Genesis project is presented. These benchmarks are directed towards the evaluation of Distributed Memory MIMD systems and are therefore rather different in character from the PERFECT benchmarks. A sample of the performance results for these benchmarks is given for a wide variety of different parallel systems. Some conclusions and remarks about future work are also included.