Memory Allocation Scheme Research Articles

Using a Mathematical Model to Evaluate the Efficiency of Memory Allocation Algorithm

One of the key research areas in operating systems is memory allocation and process management by the operating system. Memory allocation is the process of allocating blocks of memory to different executing processes in order to improve overall system performance. This paper analyses the efficiency of memory allocation algorithms (first fit, best fit and worst fit) in the multiple partition and contiguous memory allocation scheme. A Mathematical model was used on process sizes in terms of percentage internal fragmentation (IF%), percentage external fragmentation (EF%), and percentage total utilization (TU%), this was done to compare the performance of the memory allocation algorithm. Results from the analysis show that the best fit made more efficient use of the available memory space than that of first-fit and worst fit.

Streamlined Algorithms for Large-Scale Matrix Computations in High-Performance Computing

In the realm of high-performance computing (HPC), large-scale matrix computations are fundamental to a myriad of scientific and engineering applications, from simulations in physics and engineering to data analysis in machine learning. This paper addresses the critical need for efficient and scalable algorithms capable of handling the growing computational demands of these applications. This study explores advanced algorithmic strategies that leverage the architecture of modern HPC systems, including parallelism, distributed computing, and optimized memory usage. The proposed algorithms are designed to minimize computational complexity and maximize performance, ensuring that largescale matrix operations can be executed swiftly and accurately. One of the key contributions of this work is the development of parallel algorithms that distribute the computational workload across multiple processors, significantly reducing execution time. By employing techniques such as data partitioning and workload balancing, the algorithms ensure optimal use of available computational resources, thus enhancing scalability. Furthermore, the paper introduces innovative approaches to memory management, which are crucial for handling large matrices that exceed the memory capacity of individual computing nodes. These approaches include efficient data storage formats and dynamic memory allocation strategies that reduce overhead and improve data access speeds. Another critical aspect of this research is the application of these algorithms to real-world problems. The paper presents case studies in fields such as climate modeling, structural analysis, and machine learning, demonstrating the practical benefits and performance gains achieved through the use of streamlined matrix computation algorithms. The results show substantial improvements in computation time and resource utilization, validating the effectiveness of the proposed methods. Additionally, the paper discusses the integration of these algorithms into existing HPC frameworks and libraries, making them accessible to a broader community of researchers and practitioners. By providing detailed implementation guidelines and performance benchmarks, the study ensures that the benefits of these advanced algorithms can be readily harnessed in various applications. The research also delves into the theoretical underpinnings of the proposed algorithms, offering a rigorous analysis of their computational complexity and scalability. In conclusion, this paper makes significant strides in addressing the challenges of large-scale matrix operations. Through the development of efficient, scalable, and practical algorithms, this research enhances the capability of HPC systems to tackle complex computational tasks, paving the way for advancements in various scientific and engineering domains. The proposed methods not only improve performance and resource utilization but also contribute to the broader goal of making high-performance computing more accessible and effective for large-scale data analysis and simulation.

Streamlined Algorithms for Large-Scale Matrix Computations in High-Performance Computing

In the realm of high-performance computing (HPC), large-scale matrix computations are fundamental to a myriad of scientific and engineering applications, from simulations in physics and engineering to data analysis in machine learning. This paper addresses the critical need for efficient and scalable algorithms capable of handling the growing computational demands of these applications. This study explores advanced algorithmic strategies that leverage the architecture of modern HPC systems, including parallelism, distributed computing, and optimized memory usage. The proposed algorithms are designed to minimize computational complexity and maximize performance, ensuring that largescale matrix operations can be executed swiftly and accurately. One of the key contributions of this work is the development of parallel algorithms that distribute the computational workload across multiple processors, significantly reducing execution time. By employing techniques such as data partitioning and workload balancing, the algorithms ensure optimal use of available computational resources, thus enhancing scalability. Furthermore, the paper introduces innovative approaches to memory management, which are crucial for handling large matrices that exceed the memory capacity of individual computing nodes. These approaches include efficient data storage formats and dynamic memory allocation strategies that reduce overhead and improve data access speeds. Another critical aspect of this research is the application of these algorithms to real-world problems. The paper presents case studies in fields such as climate modeling, structural analysis, and machine learning, demonstrating the practical benefits and performance gains achieved through the use of streamlined matrix computation algorithms. The results show substantial improvements in computation time and resource utilization, validating the effectiveness of the proposed methods. Additionally, the paper discusses the integration of these algorithms into existing HPC frameworks and libraries, making them accessible to a broader community of researchers and practitioners. By providing detailed implementation guidelines and performance benchmarks, the study ensures that the benefits of these advanced algorithms can be readily harnessed in various applications. The research also delves into the theoretical underpinnings of the proposed algorithms, offering a rigorous analysis of their computational complexity and scalability. In conclusion, this paper makes significant strides in addressing the challenges of large-scale matrix operations. Through the development of efficient, scalable, and practical algorithms, this research enhances the capability of HPC systems to tackle complex computational tasks, paving the way for advancements in various scientific and engineering domains. The proposed methods not only improve performance and resource utilization but also contribute to the broader goal of making high-performance computing more accessible and effective for large-scale data analysis and simulation.

A unified hybrid memory system for scalable deep learning and big data applications

Emerging non-volatile memory (NVM) technologies are of dynamic random access memory (DRAM)-like, high capacity, and low cost, at the expense of slower bandwidth and higher read/write latency compared to DRAM. Typically, NVM finds its primary application in serving as an extension of conventional DRAM to create hybrid memory systems tailored to non-uniform memory access (NUMA) architectures. This strategic integration offers the potential for high performance, enhanced capacity efficiency, and a favorable balance of cost considerations. Traditional NUMA memory management policies distribute data uniformly across both DRAM and NVM, overlooking the inherent performance gap between these heterogeneous memory systems. This challenge becomes particularly pronounced when provisioning resources for deep learning and big data applications in hybrid memory systems. To tackle the performance issues in the hybrid memory systems, we propose and develop a unified memory system, UniRedl, which automatically optimizes data migration between DRAM and NVM based on data access patterns and computation graphs of applications. To improve application performance, we provide a new memory allocation strategy named HiLowAlloc. We further design two data migration strategies in UniRedl, Idle Migration and Dynamic Migration, for management of hybrid memory systems. Specifically, Idle Migration aims to manage data placed in DRAM, while Dynamic Migration manages data saved in NVM. The experimental results demonstrate that on average UniRedl improves application performance by 33.2%, 20.6%, 19.0%, and 17.5% compared to the traditional NUMA, NUMA with anb, BMPM, and OIM, respectively. It also achieves 52.0%, 34.3%, 30.6%, 22.1% on average improvement in data locality against the state-of-the-art solutions.

Memory Allocation Strategy in Edge Programmable Logic Controllers Based on Dynamic Programming and Fixed-Size Allocation

With the explosive growth of data at the edge in the Industrial Internet of Things (IIoT), edge devices are increasingly performing more data processing tasks to alleviate the load on cloud servers. To achieve this goal, Programmable Logic Controllers (PLCs) are gradually transitioning into edge PLCs. However, efficiently executing a large number of computational tasks in memory-limited edge PLCs is a significant challenge. Therefore, there is a need to design an efficient memory allocation strategy for edge PLCs. This paper proposes a dynamic memory allocation strategy for edge PLCs. It adopts an approach of organizing memory into small blocks to handle memory requests from real-time tasks and utilizes a well-performing dynamic programming method for resource allocation problems to handle memory requests from non-real-time tasks. This approach ensures real-time performance while improving the efficiency of non-real-time task processing. In the simulation experiments, the algorithm implemented based on this allocation strategy is compared with the default method and several open-source memory allocators. The experimental results demonstrate that the proposed algorithm, on average, improves the speed of real-time task processing by 13.7% and achieves a maximum speed improvement of 17.0% for non-real-time task processing. The experimental results show that the allocation strategy effectively improves memory allocation efficiency in memory-limited environments.

AutoMap: Automatic Mapping of Neural Networks to Deep Learning Accelerators for Edge Devices

Emerging deep neural networks (DNNs) have been emerging in applications (object detection, automatic speech recognition, etc.) deployed on edge devices. To improve the energy efficiency of edge devices, domain specific deep learning accelerators (DLAs) are designed with limited on-chip resources. The manifold DLA designs and evolving DNN topologies bring challenges for applications mapping and scheduling on hardware resources. In this paper, we propose an automatic DNN mapping framework named AutoMap given the hardware backend information. Firstly, a computational graph representation called Extended Directed Weighted Graph (EDWG) is proposed, which realizes unified expression for both spatial and temporal network inter-layer connections. Secondly, an associated partitioner is implemented for splitting an EDWG into subEDWGs, which incorporates the on-chip memory constraint and facilitates weight data reuse on chip. Lastly, a dynamic memory allocation strategy is utilized to alleviate the feature storing burden introduced by the multivarious network sizes and connections. Compared to the baseline mapping methods, experimental results show that our proposed automatic mapping framework can help to speedup the execution of several DNNs on state-of-the-art DLAs, ranging from 1.27x to 3.45x. The utilization of the PE array can increase from 20% to 64%.

Operand-Oriented Virtual Memory Support for Near-Memory Processing

Virtual memory support is one of the major challenges of near-memory processing (NMP). Many previous works focused on this issue, but there are practical limitations that conventional CPU hardware or memory allocation schemes should be modified. Another technique uses a specialized page table for NMP to avoid such limitations. However, the previous work proposed NMP-specific page table that has static page table walk latency regardless of data size. This causes unnecessarily long address translation time for relatively small data. In this paper, we propose an operand-oriented technique for virtual memory support. Our scheme does not pre-determine the size of shared space; rather, it allocates shared space depending on the size of operands data for NMP. Then, we significantly reduce page table walk latency by using our flexible page table, which adapts the page table hierarchy to the size of shared spaces. To prove our concept, we implement our scheme in a full-system simulator and an FPGA-based verification platform. We then compared it with CPU's page table and the previous NMP-specific page table. The experimental results show that our technique outperforms page table walk latency by 69.3 percent and 43.8 percent compared to the CPU's page table and the comparison, respectively.

PEzoNG: Advanced Packer For Automated Evasion On Windows

The ability to evade Antivirus analyses is a highly coveted goal in the cybersecurity field, especially in the case of Red Team operations where advanced external threats against a target infrastructure are performed. In this paper we present the design and implementation of PEzoNG, a framework for automatically creating stealth binaries that target a very low detection rate in a Windows environment. PEzoNG features a custom loader for Windows binaries, polymorphic obfuscation, a payload decryption process and a number of anti-sandbox and anti-analysis evasion mechanisms, including a novel user space unhooking technique. In addition, the custom loader supports a large amount of Windows executable files, and features stealth and advanced memory allocation schemes. We evaluate the effectiveness of PEzoNG by testing various malicious payloads against up to 29 commercial Antivirus solutions, and we highlight and discuss the assets and differences of PEzoNG with respect to similar tools.

Memory-Efficient CNN Accelerator Based on Interlayer Feature Map Compression

Existing deep convolutional neural networks (CNNs) generate massive interlayer feature data during network inference. To maintain real-time processing in embedded systems, large on-chip memory is required to buffer the interlayer feature maps. In this paper, we propose an efficient hardware accelerator with an interlayer feature compression technique to significantly reduce the required on-chip memory size and off-chip memory access bandwidth. The accelerator compresses interlayer feature maps through transforming the stored data into frequency domain using hardware-implemented <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$8\times 8$ </tex-math></inline-formula> discrete cosine transform (DCT). The high-frequency components are removed after the DCT through quantization. Sparse matrix compression is utilized to further compress the interlayer feature maps. The on-chip memory allocation scheme is designed to support dynamic configuration of the feature map buffer size and scratch pad size according to different network-layer requirements. The hardware accelerator combines compression, decompression, and CNN acceleration into one computing stream, achieving minimal compressing and processing delay. A prototype accelerator is implemented on an FPGA platform and also synthesized in TSMC 28-nm COMS technology. It achieves 403GOPS peak throughput and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.4\times \sim 3.3\times $ </tex-math></inline-formula> interlayer feature map reduction by adding light hardware area overhead, making it a promising hardware accelerator for intelligent IoT devices.

Engineering In-place (Shared-memory) Sorting Algorithms

We present new sequential and parallel sorting algorithms that now represent the fastest known techniques for a wide range of input sizes, input distributions, data types, and machines. Somewhat surprisingly, part of the speed advantage is due to the additional feature of the algorithms to work in-place, i.e., they do not need a significant amount of space beyond the input array. Previously, the in-place feature often implied performance penalties. Our main algorithmic contribution is a blockwise approach to in-place data distribution that is provably cache-efficient. We also parallelize this approach taking dynamic load balancing and memory locality into account. Our new comparison-based algorithm In-place Parallel Super Scalar Samplesort ( IPS 4 o ) , combines this technique with branchless decision trees. By taking cases with many equal elements into account and by adapting the distribution degree dynamically, we obtain a highly robust algorithm that outperforms the best previous in-place parallel comparison-based sorting algorithms by almost a factor of three. That algorithm also outperforms the best comparison-based competitors regardless of whether we consider in-place or not in-place, parallel or sequential settings. Another surprising result is that IPS 4 o even outperforms the best (in-place or not in-place) integer sorting algorithms in a wide range of situations. In many of the remaining cases (often involving near-uniform input distributions, small keys, or a sequential setting), our new In-place Parallel Super Scalar Radix Sort ( IPS 2 Ra ) turns out to be the best algorithm. Claims to have the – in some sense – “best” sorting algorithm can be found in many papers which cannot all be true. Therefore, we base our conclusions on an extensive experimental study involving a large part of the cross product of 21 state-of-the-art sorting codes, 6 data types, 10 input distributions, 4 machines, 4 memory allocation strategies, and input sizes varying over 7 orders of magnitude. This confirms the claims made about the robust performance of our algorithms while revealing major performance problems in many competitors outside the concrete set of measurements reported in the associated publications. This is particularly true for integer sorting algorithms giving one reason to prefer comparison-based algorithms for robust general-purpose sorting.

Adaptive Layered Segregated Fit Scheme for Dynamic Memory Allocation

Embedded applications are becoming more complex and are required to utilize computing platform resources more efficiently. Existing dynamic memory allocation (DSA) schemes cannot adaptively perform memory management according to the environment in which they are located or integrate various memory allocation strategies, making it impossible to guarantee a constant execution time. Efficient memory utilization is a crucial challenge for developers, especially in embedded OSs (operating systems). In this paper, we propose an adaptive layered segregated fit (ALSF) scheme for DSA. The ALSF scheme combines dynamic two-dimensional arrays and bitmaps, completes the allocation and freeing of memory blocks within constant execution time, and uses memory splitting technology to reduce internal fragmentation. The proposed scheme also adjusts the number of segregated lists by analyzing the system’s allocation of different memory sizes, which improves the matching accuracy of memory blocks. We conducted a comparative experimental analysis and investigation of the ALSF and two-level segregated fit (TLSF) schemes in the Zephyr OS. Experiments show that the average memory utilization of the proposed ALSF scheme reaches 94.95%. Compared with the TLSF scheme, our scheme has a 12.99% higher allocation success rate in the memory-scarce environment, and the execution speeds of the two are similar.

A Neighborhood Aware Caching and Interest Dissemination Scheme for Content Centric Networks

Content-Centric Networking (CCN) is a promising framework for the next generation Internet architecture that exploits ubiquitous in-network caching to minimize content delivery latency and reduce network traffic. In this paper, we introduce a neighborhood aware mechanism for content caching, named Neighborhood Aware Caching and Interest Dissemination (NACID) that accounts for the popularity of contents and how close the content copies are in the neighborhood. We use a very low-overhead, Bloom Filter based dissemination of caching information in the neighborhood. Given the neighborhood cached contents, the proposed scheme decides when and how to handle the additional caching of content and its eviction. Simulation results show that NACID performs substantially better than the existing CCN caching policies. We also study different heterogeneous cache memory allocation strategies and show that the simpler homogeneous allocation strategies work almost as well.

Estrategias computacionales para la implementación de modelado elástico 2D sobre GPU

El modelado de onda elástico presenta un reto de implementación debido a que es un procedimiento computacionalmente costoso. En la actualidad, debido al incremento en la potencia en GPU junto con el desarrollo de la computación HPC, es posible ejecutar modelado elástico con mejores tiempos de ejecución y uso de memoria. Este estudio evalúa el desempeño de 2 estrategias para implementar modelado elástico usando diferentes diseños para ejecución de kernel, estrategias de asignación de memoria para el cálculo de CPML y administración del almacenamiento del campo de onda. Las mediciones de desempeño muestran que el algoritmo que incluye diseño de ejecución de kernel 2D, la estrategia de memoria reducida CPML y el almacenamiento en memoria global de GPU del campo de onda alcanza un máximo de 88.4% mejor tiempo de ejecución y utiliza un 13.3 veces menos memoria para obtener los mismos resultados de modelado elástico. Existe también una creciente tendencia de mejora de tiempo de ejecución y ahorro de memoria cuando se trabaja con modelos de tamaños más grandes con esta estrategia.

Breaking down memory walls

Log-Structured Merge-trees (LSM-trees) have been widely used in modern NoSQL systems. Due to their out-of-place update design, LSM-trees have introduced memory walls among the memory components of multiple LSM-trees and between the write memory and the buffer cache. Optimal memory allocation among these regions is non-trivial because it is highly workload-dependent. Existing LSM-tree implementations instead adopt static memory allocation schemes due to their simplicity and robustness, sacrificing performance. In this paper, we attempt to break down these memory walls in LSM-based storage systems. We first present a memory management architecture that enables adaptive memory management. We then present a partitioned memory component structure with new flush policies to better exploit the write memory to minimize the write cost. To break down the memory wall between the write memory and the buffer cache, we further introduce a memory tuner that tunes the memory allocation between these two regions. We have conducted extensive experiments in the context of Apache AsterixDB using the YCSB and TPC-C benchmarks and we present the results here.

A Dynamic Memory Allocation Optimization Mechanism Based on Spark

Spark is a distributed data processing framework based on memory. Memory allocation is a focus question of Spark research. A good memory allocation scheme can effectively improve the efficiency of task execution and memory re... | Find, read and cite all the research you need on Tech Science Press

GBCNN: A Full GPU-Based Batch Multi-Task Cascaded Convolutional Networks

Recently, the face detection and alignment is so popular and widely used in many research and application fields. Many superior face detection algorithms such as multi-task cascade convolutional network have been presented. However, it has difficulty in predicting faces among the big scale images in real time due to its three stages cascade architecture with less optimization. In this paper, we propose a full GPU-based batch multi-task cascade convolutional network which is carefully designed and optimized in each step to gain a superior speed performance. In addition, we present a novel parallel memory allocation strategy, which further enables our algorithm to support the batch operation, so that the system throughput increases significantly. In the experiment, our method achieves up to 300fps, over 600% speedup with an equal accuracy over the state-of-the-art methods on the face detection benchmarks.

Lightweight and Accurate Memory Allocation in Key-Value Cache

The use of key-value caches in modern web servers is becoming more and more ubiquitous. Representatively, Memcached as a widely used key-value cache system, originally intended for speeding up dynamic web applications by alleviating database load. One of the key factors affecting the performance of Memcached is the memory allocation among different item classes. How to obtain the most efficient partitioning scheme with low time and space consumption is a focus of attention. In this paper, we propose a lightweight and accurate memory allocation scheme in Memcached, by sampling access patterns, analyzing data locality, and reassigning the memory space. One early study on optimizing memory allocation is LAMA, which uses footprint-based MRC to optimize memory allocation in Memcached. However, LAMA does not model deletion operations in Memcached and its spatial overhead is quite large. We propose a method that consumes only 3% of LAMA space and can handle read, write and deletion operations. Moreover, evaluation results show that the average stable-state miss ratio is reduced by 15.0% and the average stable-state response time is reduced by 12.3% when comparing our method to LAMA.

Hi-DMM: High-Performance Dynamic Memory Management in High-Level Synthesis

High-level synthesis (HLS) of field programmable gate array (FPGA)-based accelerators has been proposed in order to simplify accelerator design process with respect to design time and complexity. However, modern HLS tools do not consider dynamic memory allocation constructs in high-level programming languages like C and limit themselves to static memory allocation. This paper proposes a dynamic memory allocation and management scheme, called Hi-DMM, for inclusion in commercial HLS design flows. Hi-DMM performs source-to-source transformation of user C code with dynamic memory constructs into C-source code with the dynamic memory allocator and management scheme developed in this paper. The transformed C-source code is amenable to synthesis by commercial tools like Vivado HLS. Relying on buddy tree-based allocation schemes and efficient hardware implementation of the allocators, Hi-DMM achieves 4x speed-up in both fine-grained and coarse-grained memory allocation compared to previous works. Experimental results obtained by including Hi-DMM with Vivado-HLS show that dynamic memory allocation of FPGA memory resources can be achieved at a much lower latency with minimal resource overhead, paving the way for synthesis of dynamic memory constructs in commercial HLS flows.

50 million atoms scale molecular dynamics modelling on a single consumer graphics card

This paper presents a dynamic cell-list method for realizing large scale molecular dynamics (MD) simulations with more than 50 million atoms on a single consumer graphics card. It adapts the cell-list algorithm by introducing an efficient two-step atom location scheme and a dynamic memory allocation scheme such that only those cells containing atoms consume device memory. In addition, a large amount of memory is saved since it does not use the neighbour list. The computational efficiency is improved by reducing the memory loading times and maximizing coalesced memory access as compared to methods utilizing neighbour lists, since memory bandwidth is becoming the bottle-neck of the latest GPUs. As a result, MD simulations with more than 50 million atoms utilizing advanced three-body interaction potential are made possible on a consumer graphics card with just 11 GB of graphics memory. The proposed framework is designed to run totally on the graphics card, with all the data stored in the graphics memory to avoid the time-consuming data transfer between host and device. It achieves 2.5 times the speed and 20 times the atom number of the latest Lammps GPU package on the NVIDIA GTX 1080Ti GPU. The proposed framework is expected to help adapt existing MD packages for supporting large scale MD simulations on personal desktops and thereby extend MD to a wider range of researchers and engineers.

ReDRAM: A Reconfigurable DRAM Cache for GPGPUs

Hardware-based DRAM cache techniques for GPGPUs propose to use GPU DRAM as a cache of the host (system) memory. However, these approaches do not exploit the opportunity of allocating store-before-load data (data that is written before being read by GPU cores) on GPU DRAM that would save multiple CPU-GPU transactions. In this context, we propose ReDRAM, a novel memory allocation strategy for GPGPUs which re-configures GPU DRAM cache as a heterogeneous unit. It allows allocation of store-before-load data directly onto GPU DRAM and also utilizes it as a cache of the host memory. Our simulation results using a modified version of GPGPU-Sim show that ReDRAM can improve performance for applications that use store-before-load data by 57.6 percent (avg.) and 4.85x (max.) when compared to the existing proposals on state-of-the-art GPU DRAM caches.