Memory Access Mode Research Articles

Extension VM: Interleaved Data Layout in Vector Memory

While vector architecture is widely employed in processors for neural networks, signal processing, and high-performance computing; however, its performance is limited by inefficient column-major memory access. The column-major access limitation originates from the unsuitable mapping of multidimensional data structures to two-dimensional vector memory spaces. In addition, the traditional data layout mapping method creates an irreconcilable conflict between row- and column-major accesses. Ideally, both row- and column-major accesses can take advantage of the bank parallelism of vector memory. To this end, we propose the Interleaved Data Layout (IDL) method in vector memory, which can distribute vector elements into different banks regardless of whether they are in the row- or column-major category, so that any vector memory access can benefit from bank parallelism. Additionally, we propose an Extension Vector Memory (EVM) architecture to achieve IDL in vector memory. EVM can support two data layout methods and vector memory access modes simultaneously. The key idea is to continuously distribute the data that needs to be accessed from the main memory to different banks during the loading period. Thus, EVM can provide a larger spatial locality level through careful programming and the extension ISA support. The experimental results showed a 1.43-fold improvement of state-of-the-art vector processors by the proposed architecture, with an area cost of only 1.73%. Furthermore, the energy consumption was reduced by 50.1%.

A parallel particle swarm optimization algorithm based on GPU/CUDA

Parallel computing is the main way to improve the computational efficiency of metaheuristic algorithms for solving high-dimensional, nonlinear optimization problems. Previous studies have typically only implemented local parallelism for the particle swarm optimization (PSO) algorithm. In this study, we proposed a new parallel particle swarm optimization algorithm (GPU-PSO) based on the Graphics Processing Units (GPU) and Compute Unified Device Architecture (CUDA), which uses a combination of coarse-grained parallelism and fine-grained parallelism to achieve global parallelism. In addition, we designed a data structure based on CUDA features and utilized a merged memory access mode to further improve data-parallel processing and data access efficiency. Experimental results show that the algorithm effectively reduces the solution time of PSO for solving high-dimensional, large-scale optimization problems. The speedup ratio increases with the dimensionality of the objective function, where the speedup ratio is up to 2000 times for the high-dimensional Ackley function.

Acceleration of a Production-Level Unstructured Grid Finite Volume CFD Code on GPU

Due to the complex topological relationship, poor data locality, and data racing problems in unstructured CFD computing, how to parallelize the finite volume method algorithms in shared memory to efficiently explore the hardware capabilities of many-core GPUs has become a significant challenge. Based on a production-level unstructured CFD software, three shared memory parallel programming strategies, atomic operation, colouring, and reduction were designed and implemented by deeply analysing its computing behaviour and memory access mode. Several data locality optimization methods—grid reordering, loop fusion, and multi-level memory access—were proposed. Aimed at the sequential attribute of LU-SGS solution, two methods based on cell colouring and hyperplane were implemented. All the parallel methods and optimization techniques implemented were comprehensively analysed and evaluated by the three-dimensional grid of the M6 wing and CHN-T1 aeroplane. The results show that using the Cuthill–McKee grid renumbering and loop fusion optimization techniques can improve memory access performance by 10%. The proposed reduction strategy, combined with multi-level memory access optimization, has a significant acceleration effect, speeding up the hot spot subroutine with data races three times. Compared with the serial CPU version, the overall speed-up of the GPU codes can reach 127. Compared with the parallel CPU version, the overall speed-up of the GPU codes can achieve more than thirty times the result in the same Message Passing Interface (MPI) ranks.

Architecture Support for Bitslicing

The bitsliced programming model has shown to boost the throughput of software programs. However, on a standard architecture, it exerts a high pressure on register access, causing memory spills and restraining the full potential of bitslicing. In this work, we present architecture support for bitslicing in a System-on-Chip. Our hardware extensions are of two types; internal to the processor core, in the form of custom instructions, and external to the processor, in the form of direct memory access module with support for data transposition. We present a comprehensive performance evaluation of the proposed enhancements in the context of several RISC-V ISA definitions (RV32I, RV64I, RV32B, RV64B). The proposed 14 new custom instructions use 1.5× fewer registers compared to the equivalent functionality expressed using RISC-V instructions. The integration of those custom instructions in a 5-stage pipelined RISC-V RV32I core incurs 10.21% and 12.72% overhead respectively in area and cell count using the SkyWater 130 nm standard cell library. The proposed bitslice transposition unit with DMA provides a further speedup, changing the quadratic increase in execution time of data transposition to linear. Finally, we demonstrate a comprehensive performance evaluation using a set of benchmarks of lightweight and masked ciphers.

Caching Hybrid Rotation: A Memory Access Optimization Method for CNN on FPGA

Custom computing architectures on field programmable gate array (FPGA) platforms are a viable solution to further accelerate convolutional neural network (CNN) inference. However, due to the large size feature map matrix data, the optimization of CNN feature maps storage computing on FPGA remains a challenge. To overcome these challenges, a FPGA-oriented memory access optimization method for CNN is proposed. Firstly, the feature map partition strategy is used to group the feature map efficiently. Second, the input and the output caching rotation methods are employed in adaptive memory access mode. Third, a caching hybrid rotation method is proposed to optimize memory access performance and can effectively reduce the access time of the CNN feature map. Experimental results based on SkyNet and VGG16 show that the inference speed of the proposed model is accelerated by 7.1 times compared with the previous conventional memory access optimization for CNN on FPGA. Through the evaluation of computational energy efficiency, our method can be improved by 6.4 times compared to the current typical accelerators.

Unsharp masking image enhancement the parallel algorithm based on cross-platform

In view of the low computational efficiency and the limitations of the platform of the unsharp masking image enhancement algorithm, an unsharp masking image enhancement parallel algorithm based on Open Computing Language (OpenCL) is proposed. Based on the analysis of the parallel characteristics of the algorithm, the problem of unsharp masking processing is implemented in parallel. Making use of the characteristics of data reuse in the algorithm, the effective allocation and optimization of global memory and constant memory are realized according to the access attributes of the data and the characteristics of the OpenCL storage model, and the use efficiency of off-chip memory is improved. Through the data storage access mode, the fast computing local memory access mode is discovered, and the logical data space transformation is used to convert the storage access mode, so as to improve the bandwidth utilization of the on-chip memory. The experimental results show that, compared with the CPU serial algorithm, the OpenCL accelerated unsharp masking image enhancement parallel algorithm greatly reduces the execution time of the algorithm while maintaining the same image quality, and achieves a maximum speedup of 16.71 times. The high performance and platform transplantation of the algorithm on different hardware platforms are realized. It provides a reference method for real-time processing of a large amount of data of high-resolution images for image enhancement.

An Efficient Dual-Channel Data Storage and Access Method for Spaceborne Synthetic Aperture Radar Real-Time Processing

With the development of remote sensing technology and very large-scale integrated circuit (VLSI) technology, the real-time processing of spaceborne Synthetic Aperture Radar (SAR) has greatly improved the ability of Earth observation. However, the characteristics of external memory have led to matrix transposition becoming a technical bottleneck that limits the real-time performance of the SAR imaging system. In order to solve this problem, this paper combines the optimized data mapping method and reasonable hardware architecture to implement a data controller based on the Field-Programmable Gate Array (FPGA). First of all, this paper proposes an optimized dual-channel data storage and access method, so that the two-dimensional data access efficiency can be improved. Then, a hardware architecture is designed with register manager, simplified address generator and dual-channel Double-Data-Rate Three Synchronous Dynamic Random-Access Memory (DDR3 SDRAM) access mode. Finally, the proposed data controller is implemented on the Xilinx XC7VX690T FPGA chip. The experimental results show that the reading efficiency of the data controller proposed is 80% both in the range direction and azimuth direction, and the writing efficiency is 66% both in the range direction and azimuth direction. The results of a comparison with the recent implementations show that the proposed data controller has a higher data bandwidth, is more flexible in its design, and is suitable for use in spaceborne scenarios.

Memory access optimization of molecular dynamics simulation software Crystal-MD on Sunway Taihulight

The radiation damage effect of key structural materials is one of the main research subjects of the numerical reactor. From the perspective of experimental safety and feasibility, Molecular Dynamics (MD) in the materials field is an ideal method for simulating the radiation damage of structural materials. The Crystal-MD represents a massive parallel MD simulation software based on the key material characteristics of reactors. Compared with the Large-scale Atomic/Molecular Massively Parallel Simulator (LAMMPS) and ITAP Molecular Dynamics (IMD) software, the Crystal-MD reduces the memory required for software operation to a certain extent, but it is very time-consuming. Moreover, the calculation results of the Crystal-MD have large deviations, and there are also some problems, such as memory limitation and frequent communication during its migration and optimization. In this paper, in order to solve the above problems, the memory access mode of the Crystal-MD software is studied. Based on the memory access mode, a memory access optimization strategy is proposed for a unique architecture of China's supercomputer Sunway TaihuLight. The proposed optimization strategy is verified by the experiments, and experimental results show that the running speed of the Crystal-MD is increased significantly by using the proposed optimization strategy.

An Efficient FPGA-Based Implementation for Quantized Remote Sensing Image Scene Classification Network

Deep Convolutional Neural Network (DCNN)-based image scene classification models play an important role in a wide variety of remote sensing applications and achieve great success. However, the large-scale remote sensing images and the intensive computations make the deployment of these DCNN-based models on low-power processing systems (e.g., spaceborne or airborne) a challenging problem. To solve this problem, this paper proposes a high-performance Field-Programmable Gate Array (FPGA)-based DCNN accelerator by combining an efficient network compression scheme and reasonable hardware architecture. Firstly, this paper applies the network quantization to a high-accuracy remote sensing scene classification network, an improved oriented response network (IORN). The volume of the parameters and feature maps in the network is greatly reduced. Secondly, an efficient hardware architecture for network implementation is proposed. The architecture employs dual-channel Double Data Rate Synchronous Dynamic Random-Access Memory (DDR) access mode, rational on-chip data processing scheme and efficient processing engine design. Finally, we implement the quantized IORN (Q-IORN) with the proposed architecture on a Xilinx VC709 development board. The experimental results show that the proposed accelerator has 88.31% top-1 classification accuracy and achieves a throughput of 209.60 Giga-Operations Per Second (GOP/s) with a 6.32 W on-chip power consumption at 200 MHz. The comparison results with off-the-shelf devices and recent state-of-the-art implementations illustrate that the proposed accelerator has obvious advantages in terms of energy efficiency.

Implementation and optimization of GPU‐based parallel one‐step leapfrog ADI‐FDTD for far‐field scattering problems

The one-step leapfrog alternative-direction-implicit finite-difference time-domain (ADI-FDTD), free from the Courant-Friedrichs-Lewy (CFL) stability condition and sub-step computations, is efficient when dealing with fine grid problems. However, solution of the numerous tridiagonal systems still imposes a great computational burden and makes the method hard to execute in parallel. In this paper, we proposed an efficient graphic processing unit (GPU)-based parallel implementation of the one-step leapfrog ADI-FDTD for the far-field EM scattering simulation of objects, in which we present and analyze the manners of calculation area division and thread allocation and a data layout transformation of z components is proposed to achieve better memory access mode, which is a key factor affecting GPU execution efficiency. The simulation experiment is carried out to verify the accuracy and efficiency of the GPU-based implementation. The simulation results show that there is a good agreement between the proposed one-step leapfrog ADI-FDTD method and Yee's FDTD in solving the far-field scattering problem and huge benefits in performance were encountered when the method was accelerated using GPU technology.

Risk assessment for sustainability in e-waste recycling in circular economy

E-waste is a hazardous concept for human health, environment and businesses, and therefore, risk assessment is essential to eliminate or reduce the negative effects of e-waste in a circular economy. Decision-making plays an important role during the risk assessment in e-waste recycling. This study aims to develop a decision tool under uncertain and risky conditions for achieving sustainability in electronic waste (e-waste) recycling in circular economy. Prospect theory and its aspects are integrated with the sustainability risk assessment in e-waste recycling. In order to evaluate the irrationality and risk attitudes of decision makers in a risky and uncertain environment, the prospect theory-based TODIM (acronym in Portuguese for interactive and multicriteria decision-making, i.e. Tomada de Decisao Interativa Multicriterio) method for a previous computer disassembly problem is used. Using prospect theory, the relationship between loss aversion, reference point, framing and two selves effect, and sustainability dimensions is presented with a sustainability risk assessment point of view. Further, tasks of computer disassembly processes are prioritized by considering risk factors. The results showed that random access memory modules, motherboard and power supply are the highest priority risks based on the evaluation of listed twelve sustainability risks. In this study, it is suggested that prospect theory is suitable for decisions under risk and uncertainty, and it is applicable to integrate sustainability risk assessment and prospect theory in order to fulfil the gap of knowledge. Relationship between prospect theory and sustainability risk assessment.

Hardware-software implementation of HEVC decoder on Zynq

This paper presents an efficient implementation of the High Efficiency Video Coding (HEVC) decoder using Hardware/Software (HW/SW) co-design approach on the Zynq System on Chip (SoC) Platform. The reference software decoder HM 10.0 has been implemented under embedded Linux Operating System (OS). For real-time decoding, we provide hardware acceleration for the most computationally intensive parts of the HEVC decoder, which are the interpolation filters. The proposed design improves the processing throughput targeting on the resolution of 3840 × 2160 at a frame rate of 60 fps. HW/SW validation is achieved and examined in terms of resource utilization, throughput and power consumption. In order to improve the total decoding time, we propose to enable the Direct Memory Access (DMA) mode that can help speed page access and minimize the transfer time between the processor and hardware accelerators.

Hybrid OCS/OBS interconnect in intra-data-center network

We report on a data center network (DCN) architecture based on hybrid optical circuit switching (OCS) and optical burst switching (OBS) interconnect for dynamic DCN connectivity provisioning. With the combination of the centralized and distributed control of the software-defined optical networks, the proposed interconnect can achieve unprecedented flexibility in dealing with both mice and elephant flow in the DCN. Numerical simulation is employed to investigate the performance of the proposed architecture. The results show that the OBS module has preferable performance in dealing with a larger burst packet, and the throughput is constrained by the capacity of the server random access memory module.

The methodology for active testing of electronic devices under the radiations

The methodology, developed for active testing of electronic devices under the radiations, is presented. The test set-up includes a gamma-ray facility, the hardware board/fixtures and the software tools purposely designed and realized. The methodology is so wide-ranging to allow us the verification of different classes of electronic devices, even if only application examples for static random access memory modules are reported.

FPGA Implementation of an Algorithm for Automatically Detecting Targets in Remotely Sensed Hyperspectral Images

Timely detection of targets continues to be a relevant challenge for hyperspectral remote sensing capability. The automatic target-generation process using an orthogonal projection operator (ATGP-OSP) has been widely used for this purpose. Hyperspectral target-detection applications require timely responses for swift decisions, which depend upon (near) real-time performance of algorithm analysis. Reconfigurable field-programmable gate arrays (FPGAs) are promising platforms that allow hardware/software codesign and the potential to provide powerful onboard computing capabilities and flexibility at the same time. In this paper, we present an FPGA implementation for the ATGP-OSP algorithm. Our system includes a direct memory access module and implements a prefetching technique to hide the latency of the input/output communications. The proposed method has been implemented on a Virtex-7 XC7VX690T FPGA and tested using real hyperspectral data collected by NASA’s Airborne Visible Infra-Red Imaging Spectrometer (AVIRIS) over the Cuprite mining district in Nevada and the World Trade Center in New York. Experimental results demonstrate that our hardware version of the ATGP-OSP algorithm can significantly outperform a software version, which makes our reconfigurable system appealing for onboard hyperspectral data processing.

Spincaloric properties of epitaxialCo2MnSi/MgO/Co2MnSimagnetic tunnel junctions

The electronic transport and spincaloric properties of epitaxial magnetic tunnel junctions with half-metallic ${\mathrm{Co}}_{2}\mathrm{MnSi}$ Heusler electrodes, MgO tunneling barriers, and different interface terminations are investigated by using first-principles calculations. An approach to spincaloric properties is presented that circumvents the linear response approximation inherent in the Seebeck coefficient and compared to the method of Sivan and Imry. This approach supports two different temperatures in the two electrodes and provides the exact current and/or voltage response of the system. Moreover, it accounts for temperature-dependent chemical potentials in the electrodes and finite-bias effects. We find that especially the former are important for obtaining qualitatively correct results, even if the variations of the chemical potentials are small. It is shown how the spincaloric properties can be tailored by the choice of the growth conditions. We find a large effective and spin-dependent Seebeck coefficient of $\ensuremath{-}65\phantom{\rule{4pt}{0ex}}\ensuremath{\mu}\mathrm{V}/\mathrm{K}$ at room temperature for the purely Co-terminated interface. We suggest to use such interfaces in thermally operated magnetoresistive random access memory modules, which exploit the magneto-Seebeck effect, to maximize the thermally induced readout voltage.

Designing of Soft Core Processor System with Direct Memory Access (DMA) Mode

A soft core processor system is constructed using embedded design techniques and it is configured on Field Programmable Gate Arrays (FPGAs). The system is accommodated to act with Direct Memory Access (DMA) mode using suitable Xilinx Intellectual Property (IP) core. A dual data rate synchronous dynamic random access memory (DDR_SDRAM) with 64 Mbyte capacity is introduced to the system and accessed by the DMA controller.The controller is performed to transfer programmable quantity of data from source address to destination address without intervention of the processor. Spartan-3E slice is used and programmed using Xilinx Platform Studio (XPS)which is provided by Xilinx integrated software environment at (ISE 10.1). The system performance is tested by transferring data from matlab media to the DDR_SDRAM and vice-versa, mat lab 2012a version software is used for this type of data transfer.

The S3C2440’s Camera Interface Driver Development Based on Embedded Linux

In order to realize video capture based on the S3C2440 processor on the platform of embedded Linux, the paper adopts the V4L2 as the driver model and explains in detail the implementation progress of V4L2 driver model on the Linux platform. On the basis of the existing V4L2 model and interface standard, using direct memory access mode, design the driver program of S3C2440 camera interface, the drivers are tested through the LCD display and the single frame capture, the results show that the design meets the practical need.

NUMA Computing with Hardware and Software Co-Support on Configurable Emulated Shared Memory Architectures

The emulated shared memory (ESM) architectures are good candidates for future general purpose parallel computers due to their ability to provide an easy-to-use explicitly parallel synchronous model of computation to programmers as well as avoid most performance bottlenecks present in current multicore architectures. In order to achieve full performance the applications must, however, have enough thread-level parallelism (TLP). To solve this problem, in our earlier work we have introduced a class of configurable emulated shared memory (CESM) machines that provides a special non-uniform memory access (NUMA) mode for situations where TLP is limited or for direct compatibility for legacy code sequential computing and NUMA mechanism. Unfortunately the earlier proposed CESM architecture does not integrate the different modes of the architecture well together e.g. by leaving the memories for different modes isolated and therefore the programming interface is non-integrated. In this paper we propose a number of hardware and software techniques to support NUMA computing in CESM architectures in a seamless way. The hardware techniques include three different NUMA shared memory access mechanisms and the software ones provide a mechanism to integrate and optimize NUMA computation into the standard parallel random access machine (PRAM) operation of the CESM. The hardware techniques are evaluated on our REPLICA CESM architecture and compared to an ideal CESM machine making use of the proposed software techniques.

스마트무인기 비행운용프로그램 개발

스마트무인기의 비행제어컴퓨터는 탑재장비와의 입/출력 신호처리, 비행제어법칙 연산 그리고 고장진단 및 이중화 기능 등이 구현된 비행운용프로그램이 탑재되어 있다. 비행운용프로그램은 PowerPC 755 프로세서와 VxWorks 5.5 실시간운영체제 환경에서 개발되었다. 비행운용프로그램은 메모리 참조 모듈, 탑재장비 입/출력 신호처리 모듈 그리고 비행제어법칙 모듈로 구성되었고 각각의 모듈은 계층 구조로 설계되었다. 메모리 참조 모듈과 신호처리 모듈은 벤치 테스트를 통해 검증되었고, 비행제어법칙 모듈은 시뮬레이션 시험, 지상통합시험, 안전줄 시험 그리고 비행시험을 통해 검증되었다. 본 논문에서는 비행운용프로그램의 개발환경, 소프트웨어 구조 그리고 검증 및 관리방법에 대해서 기술하였다. The operational flight program(OFP) which has the functions of I/O processing with avionics, flight control logic calculation, fault diagnosis and redundancy mode is embedded in the flight control computer of Smart UAV. The OFP was developed in the environment of PowerPC 755 processor and VxWorks 5.5 real-time operating system. The OFP consists of memory access module, device I/O signal processing module and flight control logic module, and each module was designed to hierarchical structure. Memory access and signal processing modules were verified from bench test, and flight control logic module was verified from hardware-in-the-loop simulation(HILS) test, ground integration test, tethered test and flight test. This paper describes development environment, software structure, verification and management method of the OFP.