Medium-scale Integration Research Articles

Neuromorphic sensorimotor loop embodied by monolithically integrated, low-voltage, soft e-skin

Artificial skin that simultaneously mimics sensory feedback and mechanical properties of natural skin holds substantial promise for next-generation robotic and medical devices. However, achieving such a biomimetic system that can seamlessly integrate with the human body remains a challenge. Through rational design and engineering of material properties, device structures, and system architectures, we realized a monolithic soft prosthetic electronic skin (e-skin). It is capable of multimodal perception, neuromorphic pulse-train signal generation, and closed-loop actuation. With a trilayer, high-permittivity elastomeric dielectric, we achieved a low subthreshold swing comparable to that of polycrystalline silicon transistors, a low operation voltage, low power consumption, and medium-scale circuit integration complexity for stretchable organic devices. Our e-skin mimics the biological sensorimotor loop, whereby a solid-state synaptic transistor elicits stronger actuation when a stimulus of increasing pressure is applied.

Organic Field‐Effect Transistors: Challenges and Emerging Opportunities in High‐Mobility and Low‐Energy‐Consumption Organic Field‐Effect Transistors (Adv. Energy Mater. 29/2020)

Low-energy-consumption organic field-effect transistors (OFETs) with high-mobility are the basic elements of organic circuits towards flexible, printable electronics. After 30 years of development, OFETs have progressed rapidly, from field-effect materials to devices, and from individual device to medium scale integration. In article number 2000955, Wenping Hu and co-workers provide a brief overview of the OFETs' development over the past decades. Emerging opportunities and challenges are also highlighted.

Wideband RF Filters Using Medium-Scale Integration of Lithium Niobate Laterally Vibrating Resonators

This letter presents wideband spurious-free microelectromechanical systems (MEMSs) filters based on shear horizontal (SH0) mode Lithium Niobate (LiNbO3) laterally vibrating resonators. The filters, monolithically fabricated on the same chip, have center frequencies at 400 and 750 MHz. The measured performance exhibits in-band ripple-free response, a low insertion loss (IL) of 1.7 dB, a 30-dB shape factor of 1.41, and a 3-dB fractional bandwidth (FBW) of 9.6 %-the largest reported for MEMS-resonator-based filters. The high performance was collaboratively enabled by the LiNbO3 material and filter design. The excellent piezoelectric coupling and low acoustic loss in LiNbO3 thin film ensure the low IL and large FBW, while the medium-scale integration of 200 spurious mode-free resonators fully harnesses the potential of LiNbO3 material without introducing spurious response. The filters have a device footprint less than $360 \times 350\,\,\mu \text{m}^{2}$ , thus suitable for RF frontends in handheld wireless devices.

Progress in hybrid-silicon photonic integrated circuit technology

Progress in hybrid-silicon photonic integrated circuit technology Martijn J. R. Heck, Michael L. Davenport, and John E. Bowers Adding III-V materials to the silicon-on-insulator platform enables increasingly complex devices, making it well-positioned to address energy-efficient, compact, and low-cost photonic applications. Photonic integration is the technology that allows the combi- nation of different optical components, such as lasers, modula- tors, and photodetectors, on a single photonic chip. Such devices are known as photonic integrated circuits (PICs). The prospect of medium- and large-scale integration, with tens to hundreds of components on a single chip, is a major driver for research on silicon photonics in the silicon-on-insulator (SOI) platform. The SOI fabrication infrastructure is compatible with the mature and high-quality CMOS technology, which is robust and repro- ducible and has high yield. It is possible to make PICs in the SOI platform on large 200mm-diameter wafers, and this allows for low cost and high volumes. Since these PICs can operate at wavelengths of 1.3 and 1.55 m, prime application candidates are telecommunication and interconnects. 1 The SOI platform offers an almost complete suite of pho- tonic components, including filters, (de)multiplexers, splitters, modulators, and photodetectors. However, electrically pumped efficient sources on silicon remain a challenge due to this substance’s indirect bandgap. The integration of III-V materials, such as indium phosphide (InP), gives the SOI platform access to the complete suite of high-speed and efficient III-V-based photonic components. The hybrid-silicon complex heterogeneously incorporates III-V func- tionality on the SOI platform by means of molecular wafer bonding. 2 Hybrid-silicon III-V waveguides have the proper- ties of the III-V material, such as gain, high-speed modulation, and photodetection, but are still located on an SOI circuit (see Figure 1). We can use tapered-mode converters to change a hy- brid mode into a mode that resides fully in the silicon wave- guide. We can also fabricate the active III-V components with Figure 1. Diagram showing a hybrid-silicon III-V optical amplifier in- tegrated with a silicon waveguide (bottom) and the hybrid waveguide cross section (top). Tapered-mode converters form the interface between the silicon and hybrid waveguide. The optical mode (white) overlaps with both the silicon waveguide and the III-V quantum wells (red). The top p-contact and the lateral n-contacts (yellow) provide electrical current. The device achieves current confinement by ion implanting the p-mesa (dashed). SOI: Silicon on insulator. lithographic precision and alignment accuracy, thereby enabling large-scale integration. This is done in a back-end process af- ter the SOI fabrication, which means we avoid contamination of a CMOS foundry and that the III-V manufacturing is in prin- ciple fully compatible with the SOI-CMOS fabrication proce- dure. The hybrid-silicon platform combines the maturity and scale of CMOS processing and SOI photonics with essential III-V functionality and, as such, is unique and well-positioned for medium-scale photonic integration. The timeline of Figure 2 shows the success of the hybrid- silicon technology, which we developed in collaboration with Continued on next page

The Design of High Performance Asynchronous Pipelines with Quasi Delay-Insensitive

VLSI Design looking towards to solve design constructions that arises when using clock pulses. The majority of the constrains can be overcome by using asynchronous logic, additionally synchronous circuits has some inherent advantages over synchronous counterparts. This paper demonstrates the design of efficient asynchronous pipelines for some standard logic circuits and medium scale integration (MSI) circuits. The performance analysis of various templates is designed for different standard logics and MSI circuits. The QDI templates are highly tolerant of process variations due to the up and down transitions are sensed. QDI circuits are quite robust in terms of process variations and design tolerances. In this work, expose a timing assumption used in staticizers for QDI logic and apply it to other parts of circuits. Goal of this work is to optimize circuits with respect to area and power while maintaining the robustness.

Teaching Discrete and Programmable Logic Design Techniques Using a Single Laboratory Board

Programmable logic devices (PLDs) are used at many universities in introductory digital logic laboratories, where kits containing a single high-capacity PLD replace “standard” sets containing breadboards, wires, and small- or medium-scale integration (SSI/MSI) chips. From the pedagogical point of view, two problems arise in these laboratories. First, students have some difficulties in understanding the link between discrete and programmable design techniques. Second, using only a single PLD, students are not automatically forced to learn modular design skills, which is one of the required learning outcomes in electrical engineering (EE) curricula. To overcome these problems, an innovative laboratory is proposed in this paper. Each training board contains four complex PLDs (CPLDs) and peripherals. In the initial sessions, students implement designs in which CPLDs are programmed as standard SSI/MSI chips and interconnected to construct the target circuit. Then, an active learning technique is used: Students form groups of any size and can set themselves more complex problems and choose their design approach. The proposed laboratory was set up at the Technical University of Lodz, Lodz, Poland, and the first classes were given in the 2008–2009 academic year. The instructors' insights and design reports and feedback from students were gathered and analyzed. The results showed the effectiveness of the novel approach. Students were deeply involved in solving self-imposed problems. They learned “engineering imagination,” modular design, and teamwork skills. Some groups went far beyond the requirements set by the instructor. However, an additional conclusion is that the “standard” approach should not be completely eliminated.

High-Speed and Compact Quenching Circuit for Single-Photon Avalanche Diodes

In this paper, an innovative active-quenching and recharging circuit for single-photon avalanche diodes is presented. The proposed driver is very fast and extremely compact. It is based on a novel quenching paradigm that heavily reduces dead time, which now is only limited by the sensor rather than the circuit itself. To test speed performance, we designed the circuit with a dielectrically insulated 2-mum technology supplied by ST Microelectronics and carried out postlayout simulations using SPECTRE. Moreover, the functionality of the circuit was also validated with experimental measurements on a medium scale integration (MSI) discrete implementation.

RECENT PROGRESS IN 40- TO 100-GBIT/S-CLASS OPTICAL COMMUNICATIONS ICS USING INP-BASED HBT TECHNOLOGIES

This paper describes our InP-based heterojunction bipolar transistor (HBT) technologies and circuit design techniques for small-scale-integration (SSI) and medium-scale-integration (MSI) circuits for 40- to 100-Gbit/s-class optical communications systems. The circuits include a sub-4-ps emitter-coupled logic (ECL) gate, 100-Gbit/s selector circuit, 90-Gbit/s decision circuit, 50-Gbit/s 4:1 multiplexer (MUX) and 1:4 demultiplexer (DEMUX) ICs, aver-40-Gbit/s 16:1 MUX IC, and 40-Gbit/s full-clock-rate DEMUX with a clock and data recovery (CDR) circuit. This paper demonstrates that InP-based HBT technologies and our circuit design techniques are attractive for fabricating ultrahigh-speed SSI circuits with data rates approaching 100 Gbit/s and low-power MSI circuits with data rates of over 40 Gbit/s.

K-maps: a vehicle to an optimal solution in combinational logic design problems using digital multiplexers

Application of Karnaugh maps (K-Maps) for the design of combinational logic circuits and sequential logic circuits is a subject that has been widely discussed. However, the use of K-Maps in the design of combinational logic circuits using medium scale integration (MSI) devices has not yet been widely explored. The techniques discussed in this paper, were devised, and implemented by the author as an attempt to resolve the problem of not having a criterion to determine an optimal design solution, when students presented several different designs. The devised method entails the designer to solve three distinct problems. First is an assignment problem, i.e. assigning input variables to select lines of the multiplexer. Each assignment results in a different assignment K-Map. Secondly, is a simplification problem i.e. finding the most simplified solution of each of the assignment maps. Lastly, is an optimization problem. Key Words: Karnaugh maps (K-Maps), combinational logic circuits, optimal design solution, multiplexer, simplified solution Botswana Journal of Technology Vol.13(2) 2004: 29-34

Over 40 Gbit/s 16:1 multiplexer IC using InP/InGaAs HBT technology

A low-power 16:1 multiplexer (MUX) IC using undoped-emitter InP/InGaAs heterojunction bipolar transistors (HBTs) has been successfully designed and fabricated. To minimise power consumption, the collector current density of each HBT was optimised taking into account the required operating speed and the number of fan-outs. Up to 47 Gbit/s error-free operation was confirmed with low power consumption of about 3.2 W. These results demonstrate that InP/InGaAs HBT technology is attractive for fabricating over 40 Gbit/s, low-power medium-scale-integration (MSI) circuits.

Encoder circuit for inverse differential Manchester code operating at any frequency

The inverse differential Manchester is a new code that has the same spectral efficiency as the differential Manchester code. Here, a modified encoder circuit that operates at any frequency is presented. It utilises few digital components, thus lending it for fabrication as a single medium-scale integration or part of a large-scale integration (LSI)/very LSI chip.

Optical power and intelligent sensors

The possibilities of optically powered intelligent sensors are studied by means of a model realized using medium-scale integration (MSI) CMOS ICs. Proposals are made for simplified communication protocols that allow the power budget to be optimized. Measurements are made under control of commands transmitted along the optical power line and digital data returned. This is achieved with an electrical power at the sensor head of less than 100 μW, enabling the system to operate with an optical power of order 1 mW.

Si-Ge heterojunction bipolar technology for high-speed integrated circuits

This review discusses the fundamentals of SiGe epitaxial base heterojunction bipolar transistor (HBT) technology that have been developed for use in analog and mixed-signal applications in the 1–20 GHz range. The basic principles of operation of the graded base SiGe HBT are reviewed. These principles are then used to explore the design optimization for analog applications. Device results are presented that illustrate some important trade-offs in device design. A discussion of the use of UHV/CVD for the deposition of the epitaxial base profile is followed by an overview of the integrated process. This process, which has been installed on 200 mm wafers in IBM's Advanced Semiconductor Technology Center in Hopewell Junction, N.Y., also includes a full range of support devices. The process has demonstrated SiGe HBT performance, reliability, and yield in a CMOS fabrication with the addition of only one tool for UHV/CVD deposition of the epi-base and, with minimal additional process steps, can be used to fabricate full BiCMOS designs. This paper concludes with a discussion of high-performance circuits fabricated to date, including ECL ring'oscillators, power amplifiers, low-noise amplifiers, voltage-controlled oscillators, and finally a 12-bit DAC that features nearly 3000 SiGe HBT devices demonstrating medium-scale integration.

Superconducting niobium and niobium nitride processes for medium-scale integration applications

A 10 layer circuit process is described that is based on relatively reproducible, high quality, all-niobium (Nb) and niobium nitride (NbN) Josephson junctions. The junctions are fabricated from in-situ trilayer films of S/M-MOx/S using a selective niobium etching process (SNEP), where S is superconducting Nb or NbN and M is aluminium (Al) to form the barrier for Nb junctions, or magnesium (Mg) to form the barrier for NbN junctions. These junctions have been incorporated into a 10 level process that has been used to fabricate numerous analogue and digital circuits. This paper describes this superconducting process and its application to circuit fabrication for demonstrating superconducting circuits of medium-scale complexity.

UHVCVD growth of Si/SiGe heterostructures and their applications

The era of integrated circuits based on SiGe heterojunction bipolar transistors arrived with the announcement of a 12-bit digital to analogue converter (DAC) fabricated using an analogue optimization of IBM's SiGe HBT technology. Medium-scale integration was employed, the circuit consisting of approximately 3000 transistors and 2000 passive elements (resistor and capacitors). Operable at 1 GHz, this converter consumes approximately 0.75 W, thus yielding power-delay performance a decade superior to prior devices. It is significant that this DAC was fabricated employing the same technology and toolset as found on a standard silicon-based CMOS product line. In addition to the CMOS toolset, only one unique tool is required to support this technology, a commercial (Leybold-AG) ultrahigh vacuum chemical vapour deposition system for SiGe deposition. It is of interest to note, however, that the processing of these integrated circuits was no different from that employed in fabricating high-performance SiGe high electron mobility transistors (HEMTs), as well as the first N-type SiGe-based resonant tunnelling devices (RTDs), all functional at room temperature. This enables one to combine a wafer-scale manufacturable SiGe-based heterojunction technology with devices that utilize quantum phenomena, made accessible by the use of band offsets and strain-induced band splitting in the Si/SiGe materials system. This new ability to incorporate leading edge developments in SiGe device physics into a standard technology line opens up a host of new areas for exploration.

SILICON:GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTORS: FROM EXPERIMENT TO TECHNOLOGY

Recent advances in thin film growth techniques, notably the maturation of low temperature silicon epitaxy, have enabled the routine fabrication of highly controlled dopant and silicon:germanium alloy profiles. These capabilities, combined with refinements in heterojunction bipolar transistor designs, have led to the first integrated circuits in the silicon:germanium materials system. Utilizing a commercial (Leybold-AG) UHVCVD tool for SiGe epitaxy on a standard 8" CMOS line, medium scale integration has been achieved, with the first IC components being SiGe HBT based 1 Ghz, 12 bit, digital to analog converters.

A 20-Gb/s flip-flop circuit using direct-coupled FET logic

A new type of direct-coupled FET logic (DCFL) flip-flop called the memory cell type flip-flop (MCFF) is presented. The MCFF operates faster than conventional DCFL flip-flops and enhances the DCFL's advantages, such as low power consumption and high packing density. A D-flip-flop IC and a 1/8 divider IC were developed using the MCFF. These ICs were fabricated using 0.2- mu m-gate pseudomorphic inverted HEMTs. The D-flip-flop IC is confirmed to operate up to 20 Gb/s. The 1/8 divider is toggled up to a maximum frequency of 25 GHz. These results prove that the MCFF enables DCFL circuits applicable not only to large-scale integration but to small-scale and medium-scale integration operating up to 20 Gb/s as well.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Computing perspectives: the rise of the VLSI processor

Around 1970 Intel discovered it could put 2,000 transistorsor perhaps a few moreon a single NMOS chip. In retrospect, this may be said to mark the beginning of very large-scale integration (VLSI), ...

A multichannel minimum-seeking analog-to-digital converter

A special-purpose analog to digital (A/D) circuit using medium-scale integration ICs on a printed circuit board is developed. The circuit determines which of the eight input analog signals is the lowest and provides an 8-b magnitude and 3-b address output of this minimum input signal at a 0.5-MHz conversion rate. The circuit utilizes a successive approximation register, adder registers, CMOS D/A (digital/analog), parallel comparators, and a priority encoder connected in closed loop. Control is accomplished using simple flip-flop logic. Several important signal-processing applications are mentioned for this circuit as a feedback component in optical and electronic systems, utilizing associative self-organizing memory.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

GaAs Ultra-High-Speed Prescaler/Phase Frequency Comparator Using LSCFL (Short Paper)

A high-speed, low-power prescaler/phase frequency comparator (PFC) medium scale integration (MSI) circuit for a phase-locked stable oscillator is designed and fabricated using GaAs MESFET low-power source-coupled FET logic (LSCFL) circuitry. The construction of the 1/64 frequency divider prescaler/PFC is designed to obtain high-speed and low-power operation. The fabrication process used is buried p-layer SAINT with a 0.5-µm gate length. The fabricated prescaler/PFC MSI circuit, mounted on a newly developed high-frequency package, operates up to 7.6 GHz with a power dissipation of 730 mW.