Maze Routing Research Articles

Incremental 3-D Global Routing Considering Cell Movement and Complex Routing Constraints

Placement and routing are two critical problems in VLSI physical design. However, there may be out-of-sync between the two problems considering congestion and wirelength. Therefore, it is desirable to design an efficient and highly coupled placement and routing engine to narrow the gap and minimize the mismatch between placement and routing. This paper proposes an incremental 3D global routing engine considering cell movement and complex routing constraints to relocate cells and reroute nets. We first apply a queue-based congestion-aware 3D maze routing with routing height restriction to improve the initial routing solution. Efficient multi-net-based location estimation is then presented to find the best location for each cell in multiple cell movement rounds. In each step of cell movement, we reroute nets for all candidate cell locations in parallel using a guided stack-based 3D routing algorithm while considering the routing constraints. Finally, we adopt an edge-adjusting technique to improve the routed wirelength further. Compared with the champion of the 2020 CAD Contest at ICCAD hu2020iccad and the state-of-the-art works, experiment results based on the contest benchmarks show that our proposed algorithm achieves the best routing wirelength and competitive runtime without maximum cell movement constraint.

Interactive Visualization of the Printed Circuits Tracing Algorithms for Educational Purposes

A software module that allows interactive demonstration of maze routing algorithms for tracing printed conductors, which, during their operation, use a grid representation of a discrete working space of a printed circuit board has been developed. The main difference between the developed module and the software of similar purpose is the possibility of step-by-step annotated execution of various algorithms for tracing printed conductors with the possibility of changing the order of routing user-specified conductors. The interrelation of algorithms for finding the shortest paths on graphs and algorithms for tracing printed conductors and the influence of the order of making connections between pairs of contact pads on the length of printed electrical connections are considered. An analysis of the advantages and disadvantages of the wave algorithm (Lee algorithm) and the heuristic algorithm A* was carried out with a description of their step-by-step operation. The use of the development is justified when giving lectures and conducting laboratory research on the theoretical foundations of automation systems for the design of radio electronic equipment and contributes to solving the complex problem of digitalization of the educational process with the help of visualization programs that allow you to observe the results of the algorithms they implement on various sets of initial data.

NCTUcell: A DDA- and Delay-Aware Cell Library Generator for FinFET Structure With Implicitly Adjustable Grid Map

For the 7-nm technology node, cell placement with a drain-to-drain abutment (DDA) requires additional filler cells, increasing the placement area. This is the first work to fully automatically synthesize a DDA-aware cell library with the optimized number of drains on cell boundary based on ASAP 7-nm PDK. We propose a DDA-aware dynamic programming-based transistor placement. Previous works ignore the use of the M0 layer in cell routing. We first propose an ILP-based M0 routing planning. With M0 routing, the congestion of M1 routing can be reduced and the pin accessibility (PA) can be improved due to the diminished use of M2 routing. We also present a quadratic-programming based-coupling-capacitance-aware initial routing to optimize cell delay, cell area, and M2 usage. To improve the routing resource utilization, we propose an implicitly adjustable grid map, making the maze routing able to explore more routing solutions. The experimental results show that block placement using the DDA-aware cell library requires fewer filler cells than that using the traditional cell library by 25.1%, which achieves a block area reduction rate of 0.97%.

Via-Avoidance-Oriented Interposer Routing for Layer Minimization in 2.5-D IC Designs

It is well known that interposer-based 2.5-D integrated circuit (IC) designs have become one of the most promising solutions for providing yield improvement, enhancing system performance, decreasing power consumption, and supporting heterogeneous integration. In this article, given a set of nets including some inter-chip or through-silicon buses between chips and package, inside a silicon interposer, a via-avoidance-oriented routing algorithm can be proposed to minimize the number of the used layers by satisfying the noncrossing constraint between two nets and the constraint of using no via on the inter-chip sub-nets and no vertical detour on the through-silicon sub-nets in multiple-layer interposer routing. The routing process in our proposed algorithm can be divided into two sequential steps: iterative routing step and refinement step. In the iterative routing step, the routing process of all the given nets can be completed for layer minimization in a top-down layer-by-layer manner. In each iteration, based on the definition of the obstacle-aware routing pattern for the inter-chip sub-net on one given net, the assignment of the obstacle-aware routing patterns can be firstly obtained in single-layer routing. Furthermore, the routing paths of some inter-chip sub-nets and the partial or full routing paths of some through-silicon sub-nets can be assigned and routed onto the available layer by using a maze routing process under the detour constraints. In the refinement step, based on the routing result of the given nets on the used layers, the detoured inter-chip or through-silicon sub-nets can be firstly reassigned and rerouted for the detour reduction of the given nets. Furthermore, a set of zigzag paths can be inserted onto some nets inside the given inter-chip or through-silicon buses for skew minimization. Compared with the combination of the iterative routing using Cadence’s automatic router and the detouring-path insertion on the number of the used layers, the experimental results show that our proposed routing algorithm can use reasonable CPU time and shorter wirelength to decrease 19.3% of the number of the used layers for eight tested examples on the average.

SAT-Based On-Track Bus Routing

In modern integrated circuit design, bus routing is a challenge because of complex design rules and wiring constraints. Despite extensive research, state-of-the-art in bus routing is not effective when nonuniform tracks, various obstacles, wire width constraints, and multiple spacing rules should be handled simultaneously. A new bus routing framework proposed in this article is based on maze routing and Boolean satisfiability. It produces high-quality results quickly and allows for additional optimizations, such as minimizing wire length on the critical paths. A number of challenging bus routing benchmarks appeared in 2018 ICCAD Contest. Experiments on these benchmarks not only show that the framework is faster than the winners of the competition and previous work but also produces better results, improving the overall cost by 12% while at the same time minimizing the number of spacing violations.

Postrouting Optimization of the Working Clock Frequency of Single-Flux-Quantum Circuits

With the emergence of large-scale single-flux-quantum (SFQ) circuits, it is desirable to offload heavy routing tasks to automated electronic design automation (EDA) tools. The unique characteristic of SFQ circuits is that large clock distribution networks are generally required to pass the clock signal to clocked cells subject to limited fanout drive capability of the intervening clock buffers. This scenario results in a huge challenge to control the clock skew and minimize the signal path delays in an SFQ circuit during the routing step. Values of the clock skew and path delays determine not only the maximum working frequencies but also whether or not there are hold time violations. However, it is not necessary to develop a timing-driven routing tool specifically for SFQ circuits from scratch because the number of the paths that set the maximum clock frequencies or give rise to hold time violations is generally very small. Thus, we present a novel postrouting optimization framework that augments standard maze routing tools by adding the capability of reducing path lengths to maximize the working frequency of the chip and meandering paths to avoid hold time violations. A framework is developed in which machine learning is applied to analyze wire distributions and a maze routing algorithm is used to reroute targeted paths. Based on the MIT-LL SFQ5ee process technology, we demonstrate that our framework can improve the minimum working frequency by 7$\%$ on average over the state-of-the-art EDA routing tool for a suite of 14 SFQ circuits while fixing all hold time violations.

Single-Layer Obstacle-Aware Substrate Routing via Iterative Pin Reassignment and Wire Assignment

It is known that single-layer obstacle-aware substrate routing is necessary for modern IC/Package designs. In this article, given a set of two-pin nets and a set of rectangular obstacles inside a single-layer routing plane, a two-phase routing algorithm including an iterative routing phase and a rip-up-and-reroute phase can be proposed to maximize the number of the routed nets in single-layer obstacle-aware substrate routing. In the iterative routing phase, based on the pin and path distribution of the routing nets and the locations of the obstacles inside a single-layer routing plane, the start or target pins on some routing nets inside dense obstacle regions may be firstly reassigned to complete the partial wiring paths on the nets. Based on the region extraction of two intersected nets in single-layer routing, the private regions of some routing nets inside sparse obstacle regions can be extracted and the nets inside the extracted regions can be further routed by using maze routing. In the rip-up-and-reroute phase, the routability of the routing nets can be improved by ripping up some routed nets and rerouting the unrouted nets. Compared with Liu's modified algorithm and Yan's flow-based algorithm in single-layer obstacle-aware substrate routing, the experimental results show that the proposed algorithm can use less CPU time to increase 3.4% and 1.8% of the routability on the routing nets for eight tested examples on the average. Additionally, the percentage of the tested examples with the 100% routability of the routing nets on the eight tested examples has been improved from 25% to 62.5%.

An Efficient Rectilinear and Octilinear Steiner Minimal Tree Algorithm for Multidimensional Environments

The rectilinear/octilinear Steiner problem is the problem of connecting a set of terminals $Z$ using orthogonal and diagonal edges with minimum length. This problem has many applications, such as the EDA, VLSI circuit design, fault-tolerant routing in mesh-based broadcast, and Printed Circuit Board (PCB). This paper proposes an obstacle-avoiding 4/8/10/26-directional heuristic algorithm for this problem based on the Areibi’s concept, Higher Geometry Maze Routing, and Sollin’s minimal spanning tree algorithm. The major contributions of this paper are (1) our work is the first report for the octilinear SMTs in the multidimensional environments, (2) we provide an optimal point-to-point routing without any refinement, and (3) the proposed algorithm has higher adaptability to deal with any irregular environment, and can be extended to the $\lambda $ -geometry without any extra work, where $\lambda =2$ , 4, 8 and $\infty $ corresponding to rectilinear, 45°, 22.5° and Euclidean geometries respectively.

QGDR: A Via-Minimization-Oriented Routing Tool for Large-Scale Superconductive Single-Flux-Quantum Circuits

Single-flux-quantum (SFQ) circuit technologies are promising digital circuit technologies with high-speed and extremely low-power characteristics. However, heavy wire routing tasks are finished either by considerable human effort or by commercial routing tools with few physical considerations for the SFQ circuits. In this paper, we present an integrated global and detailed router for the SFQ circuits, qGDR, which aims at reducing the impedance mismatch during signal transfer by minimizing the total number of used vias. The global router allocates routing resources while minimizing the via usage by a dynamic layer assignment algorithm. The detailed router follows the global routing results to complete the routing task by resorting to a maze routing algorithm. Following the MIT-LL SFQ5ee process technology, qGDR can use only two routing layers to route an 8-bit integer divider with more than 40 000 Josephson junctions in less than one hour.

A Maze Routing-Based Methodology With Bounded Exploration and Path-Assessed Retracing for Constrained Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Construction

Owing to existing intellectual properties, prerouted nets, and power/ground wires, the routing of a system on chip design demands to detour around multilayer obstacles. Traditional approaches for the multilayer obstacle-avoiding rectilinear Steiner tree (ML-OARST) problem are thus nonmaze routing-based approaches for runtime issues, yet they cannot be directly applied to deal with additional constraints such as variant edge weights on a routing layer. In this article, we propose the maze routing-based methodology with bounded exploration and path-assessed retracing to reduce runtime and routing cost for the constrained ML-OARST construction problem. The exploration of maze routing is bounded to reduce the runtime; the costs of connecting pins are computed to select Steiner points in the retracing phase. To further reduce the routing cost, we develop a Steiner point-based ripping-up and rebuilding scheme for altering tree topology. Experimental results on industrial and randomly generated benchmarks demonstrate that the proposed methodology can provide a solution with good quality in terms of routing cost and has a significant speedup compared to traditional maze routing. A commercial tool is also used to show the effectiveness of the proposed methodology.

12. Solving a Maze Using DNA Computing

DNA computing allows us to design linear time algorithms for problems that are intractable for conventional computing methods. The high degree of parallelism provided by DNA computing allows us to create simpler algorithms for solving computational problems. In this study, a DNA computing algorithm is proposed to solve the maze routing problem – finding the optimal path through a maze. Performing the algorithm in a biology laboratory would be impractical and would exceed the scope of this project since the experimentation itself would take days. To demonstrate the steps involved in the algorithm, a simulation was developed on a conventional computer to display the in vitro techniques that would need to be performed in order to solve a maze using DNA computing in a biology lab environment. However the simulation in silico is limited in the size of problem since the processes that would occur in parallel in vitro with DNA computing, occurs sequentially with conventional computers (in silico), causing larger problems to take exponentially longer to compute. Thus, the in silico simulation is confined to smaller, more manageable problems. This serves an example of the power of DNA computing over conventional methods. Our algorithm is the first to solve a maze routing problem using DNA computing

A stochastic evolution algorithm based 2D VLSI global router

In this work we present a global router that uses the features of the Stochastic Evolution (StocE) algorithm to perform the rip-up and re-route (R&R) process. The unique features of the proposed global router are its simple design and ability to produce good results. It has two main components: (i) maze routing with framing (MRF) that act as a means of routing the nets; and (ii) a StocE algorithm that controls the R&R process and adjusts the parameters of the MRF method. This work shows that the StocE algorithm can perform the net selection in the R&R process and also adjust the parameter values of the MRF method in order to successfully solve 2D global routing problems. The performance of the proposed global router on the ISPD98 and ISPD2008 benchmarks was found to be better than some of the existing global routers.

XGRouter: high-quality global router in X-architecture with particle swarm optimization

This paper presents a high-quality very large scale integration (VLSI) global router in X-architecture, called XGRouter, that heavily relies on integer linear programming (ILP) techniques, partition strategy and particle swarm optimization (PSO). A new ILP formulation, which can achieve more uniform routing solution than other formulations and can be effectively solved by the proposed PSO is proposed. To effectively use the new ILP formulation, a partition strategy that decomposes a large-sized problem into some small-sized sub-problems is adopted and the routing region is extended progressively from the most congested region. In the post-processing stage of XGRouter, maze routing based on new routing edge cost is designed to further optimize the total wire length and mantain the congestion uniformity. To our best knowledge, XGRouter is the first work to use a concurrent algorithm to solve the global routing problem in X-architecture. Experimental results show that XGRouter can produce solutions of higher quality than other global routers. And, like several state-of-the-art global routers, XGRouter has no overflow.

Obstacle-Avoiding Rectilinear SteinerMinimum Tree: A Survey

Rectilinear Steiner Minimum Tree (RSMT) is one of the global routing techniques in VLSI design, where the tree spans a given set of pins by reaching each of them either vertically or horizontally.While constructing such RSMTs, there can be many obstacles.There are many research works done in order to construct RSMTs which aredevoid of obstacles. Some of the recent research works are considered in this paper to understand the problem and to learn the available solutions.It covers and compares different approaches and methodologies which are used to find OARSMT. Some of the different approaches discussed here are Geo-Steiner approach, Maze routing method, Top-down partitioning approach and Greedy heuristic method.Comparison of these algorithms in accordance with their speed, efficiency, resources used and other pros and cons are also listed as a part of this work. A table listing the experimental results ismadeto realize the actual performance of different algorithms.

Effects of Injection of Carbon Nanotubes on EEG and Results of a Behavioral Test in Rats

We examined the biocompatibility of carbon nanotubes (CNTs) injected i.p. into rats (1 mg/kg body mass) by recording EEG from the frontal and occipital cortex and performing the water maze router test before and after such injection. For EEG, the energy and average power spectral density of wavelet coefficients in the β, α, and θ bands were considered the features. In the water maze router experiment, the distance, time, and speed of rats were investigated as behavioral factors. Comparison of EEG signals before and after injection showed that introduction of CNTs exerted no significant effect on electrophysiological brain indices. A comparison of behavioral factors before and after injection, however, showed that injections of CNTs increased the pacing distance and time to find the desired platform and decreased somewhat the speed in the water maze router experiment. A possible reason of this phenomenon is the possible influence of CNTs on ion fluxes in brain neurons.

A Game Theory-Based Heuristic for the Two-Dimensional VLSI Global Routing Problem

In this work we propose a game theory (GT)-based global router. It works in two steps: (i) Initial routing of all nets using maze routing with framing (MRF) and (ii) GT-based rip-up and reroute (R&R) process. In initial routing, the nets are divided into several small subsets which are routed concurrently using multithreading (MT). The main task of the GT-based R&R process is to eliminate congestion. Nets are considered as players and each player employs two pure strategies: (attempt to improve its spanning tree, and, do not attempt to improve its spanning tree). The nets also have mixed strategies whose values act as probabilities for them to select any particular pure strategy. The nets which select their first strategy will go through the R&R operation. We also propose an algorithm which computes the mixed strategies of nets. The advantage of using GT to select nets is that it reduces the number of nets and the number of iterations in the R&R process. The performance of the proposed global router was evaluated on ISPD'98 benchmarks and compared with two recent global routers, namely, Box Router 2.0 (configured for speed) and Side-winder. The results show that the proposed global router with MT has a shorter runtime to converge to a valid solution than that of Box Router 2.0. It also outperforms Side-winder in terms of routability. The experimental results demonstrated that GT is a valuable technique in reducing the runtime of global routers.

Route planning and cost analysis for travelling through the Arctic Northeast Passage using public 3D GIS

To plan undeveloped optimal routes between Asia and Europe via the Arctic Northeast Passages using a 3D geographic information system (GIS), voyage paths are simulated in a 3D visual form. This ensures that the distances are calculated accurately, and that other voyage data such as water depths, sea ice distribution, and seashore topology are also easily deciphered, giving a more direct and clear demonstration compared to simplified presentations on an Electronic Chart Display & Information System (ECDIS). This article also implements a higher-geometry maze router in ice zone areas to obtain the optimal path in relation to safety and costs. This article compares the optimal Arctic Northeast Passages with traditional routes through the Suez Canal for dynamic analyses of the cost efficiency (including time costs, fuel costs, and other factors) of travel between major ports in Asia and Europe. The average benefit assessment is around 30–45% in a bulk carrier comparison. Thus, a 3D GIS can easily obtain and demonstrate safe navigation routes, providing a very convenient tool for initial planning.

Physical-Level Synthesis for Digital Lab-On-a-Chip Considering Variation, Contamination, and Defect

Microfluidic lab-on-a-chips have been widely utilized in biochemical analysis and human health studies due to high detection accuracy, high timing efficiency, and low cost. The increasing design complexity of lab-on-a-chips necessitates the computer-aided design (CAD) methodology in contrast to the classical manual design methodology. A key part in lab-on-a-chip CAD is physical-level synthesis. It includes the lab-on-a-chip placement and routing, where placement is to determine the physical location and the starting time of each operation and routing is to transport each droplet from the source to the destination. In the lab-on-a-chip design, variation, contamination, and defect need to be considered. This work designs a physical-level synthesis flow which simultaneously considers variation, contamination, and defect of the lab-on-a-chip design. It proposes a maze routing based, variation, contamination, and defect aware droplet routing technique, which is seamlessly integrated into an existing placement technique. The proposed technique improves the placement solution for routing and achieves the placement and routing co-optimization to handle variation, contamination, and defect. The simulation results demonstrate that our technique does not use any defective/contaminated grids, while the technique without considering contamination and defect uses 17.0% of the defective/contaminated grids on average. In addition, our routing variation aware technique significantly improves the average routing yield by 51.2% with only 3.5% increase in completion time compared to a routing variation unaware technique.

Algorithms for Maze Routing With Exact Matching Constraints

Exact route matching is an important constraint for analog and mixed signal designs with nonuniform metal stacks. In this paper, we propose a constrained-path-based maze routing algorithm that can handle exact matching constraints for multiple nets. We also propose a scalable framework that utilizes the proposed maze routing algorithm for realistic problem sizes. Compared to the pattern routing algorithms proposed recently , our algorithms allow a more thorough exploration of the solution space by allowing bends to be inserted to avoid congested regions. Furthermore, we propose an ILP-based model to explore the impact of the initial routing topologies on the final solutions. Our experimental study demonstrates that the proposed algorithm leads to significant reductions in congestion costs compared to the previous algorithm.

MANA: A Shortest Path Maze Algorithm Under Separation and Minimum Length NAnometer Rules

Due to process limitations, wiring rules are imposed on chip layout by foundries. Under nanometer wiring rules, the required separation between two wire ends is dependent on their surrounding wires, and there is a limit on the minimum length of each wire segment. However, traditional shortest path algorithms are not properly designed for these rules. In the paper, we propose a maze routing algorithm, called MANA, capable of finding legal shortest paths under these rules. Experiments with seven industrial cases show that by handling these rules during maze routing, 94% of the violations are prevented on average, and the overall runtime of a commercial router is reduced by 71%. In addition, the total wire length is also reduced by 3% on average.