Maximum Unity Research Articles

A local positive feedback loop-reused technique for enhancing performance of folded cascode amplifier

A current-reused folded cascode operational transconductance amplifier (OTA) using a local positive feedback (LPFB) technique has been proposed in previous literature, which does not achieve maximum unity gain-bandwidth (GBW). Besides, the stability of LPFB in the LPFB-OTA is limited by local common mode feedback (LCMFB) resistors. Based on the analysis, a local positive feedback loop-reused (LPFBR) technique is proposed to improve the performance of conventional LPFB OTA. For a fair comparison, both conventional and proposed OTAs working at saturation region are designed and simulated in SMIC 0.18μm process. The simulated results demonstrate that the proposed LPFBR-OTA has almost 10.5 times the bandwidth and maintains stability compared to that of the conventional LPFB-OTA under the condition that LCMFB resistors are increased by a factor of 10.

Study of analog performance of common source amplifier using rectangular core–shell based double gate junctionless transistor

A new state of the art double gate junctionless transistor (DGJLT) namely the rectangular core–shell DGJLT (RCS-DGJLT) based common source amplifier circuit is designed to investigate the performance. An RCS-DGJLT device is designed using a visual technology computer aided design tool and look up table-based Verilog-A model has been designed to carry out spice simulation of the circuit. Device simulation of RCS-DGJLT shows the extraordinary performance when compared to conventional DGJLT. The RCS-DGJLT exhibits an OFF current (Ioff ) ∼10−14 A, ON current (Ion ) ∼10−5 A, ON/OFF current ratio (Ion /Ioff ) ∼109, subthreshold slope ∼68.9 mV decade−1 and drain induced barrier lowering ∼52.6 mV V−1. Also, the AC response of RCS-DGJLT exhibits good performance like lower miller capacitances of order 10–16 F, maximum unity gain frequency of 138.8 GHz, transconductance generation efficiency of 40 V−1, and gain-bandwidth product of 25.4 GHz. The common source amplifier circuit using RCS-DGJLT provides the amplification up to 3.3 times which implies gain (Av ) to be 3.3. The low leakage power of 10.4 pW and average power of 31.2 µW of common source amplifier circuit based on RCS-DGJLT shows the greater potential of using the proposed device in analog applications. Also, the complete flow chart of the process used to design an analog circuit based on proposed RCS-DGJLT is discussed. The result shows the potential of using the RCS-DGJLT device in designing high-frequency applications.

Saturation Velocity Measurement of Al0.7Ga0.3N-Channel High Electron Mobility Transistors

Gate length dependent (80 nm–5000 mm) radio frequency measurements to extract saturation velocity are reported for Al0.85Ga0.15N/Al0.7Ga0.3N high electron mobility transistors fabricated into radio frequency devices using electron beam lithography. Direct current characterization revealed the threshold voltage shifting positively with increasing gate length, with devices changing from depletion mode to enhancement mode when the gate length was greater than or equal to 450 nm. Transconductance varied from 10 mS/mm to 25 mS/mm, with the 450 nm device having the highest values. Maximum drain current density was 268 mA/mm at 10 V gate bias. Scattering-parameter characterization revealed a maximum unity gain bandwidth (fT) of 28 GHz, achieved by the 80 nm gate length device. A saturation velocity value of 3.8 × 106 cm/s, or 35% of the maximum saturation velocity reported for GaN, was extracted from the fT measurements.

ISA ISMAYILZADE AS A REPRESENTATIVE OF ASSOCIATIVE POETRY

The article deals with the poetic evolution of I.Ismayilzade as a prominent representative of Azerbaijani free rhymed poetry. It is mentioned that many young people who started their creativity in the mid-50s came to poetry with new individual stylistic colour and strengthened the position of free rhymed poetry. One of them was I.Ismilzade. The poetic research of the poet, which started in the 1960s, enriched associative poetry in form and content. It can be seen that, free rhymed poem underwent a certain way of different stages in I. Ismayilzade's poetry and he is considered one of the creators of associative poetry. His poetry and poems also enriched and imoroved the development of this genre in terms of various components. . In his free rhymed poems, he strives for the maximum unity of form and content, and skilfully uses new artistic imagery and expressive means .Phonetic sounds of I.Ismayilzade's poetry originated from the content and essence, enhanced its imagery effectiveness. All this has opened wide opportunities for free rhymed poetry to enter into a new stage.

Simulation study of hetero dielectric tri material gate tunnel FET based common source amplifier circuit

Tunneling Field Effect Transistor (TFET) has emerged as an alternative device to MOSFET for designing low power analog and digital integrated circuits. This paper investigates the performance of a common source amplifier circuit designed using Gate-All-Around Hetero Dielectric Tri Material Gate TFET device. HD-TMGTFET device is designed on Visual TCAD tool and a look up table-based Verilog A model has been designed to perform SPICE circuit simulations. The performance of the HD-TMGTFET based CS amplifier circuit is compared with the MOSFET based amplifier designed using 65 nm MOSFET device. Device simulation results show that HD-TMGTFET device exhibits steep subthreshold slope of 21.2 mV/decade, high ON current of 7.5 × 10−6 A/µm and extremely low OFF state current of the order of 10−19 A/µm. The device also exhibits extremely low values of miller capacitances and has maximum unity gain frequency of 124 GHz at gate voltage of 0.9 V. HD-TMGTFET device based amplifier can provide amplification of up to 3 times within the frequency range of 100 KHz to 0.1 GHz and on the other hand MOSFET based amplifier circuit provides amplification up to 1.58 times over limited frequency range of 1 MHz, clearly showing the potential of using HD-TMGTFET device in high frequency applications.

Design & Optimization of Gate-All-Around Tunnel FET for Low Power Applications

This paper investigates the performance of tri material gate tunnel field effect transistor (TMGTFET) device designed in gate all around (GAA) configuration. The device performance is analyzed by varying various device related parameters like: drain doping, oxide thickness and radius of silicon core. Simulations are performed using technology computer-aided design (TCAD) tool at 60 nm gate length. Simulation results show that the performance of TMGTFET device can be optimized by proper selection of device parameters so as to achieve improvements in the ON current, OFF current, sub-threshold swing and ambipolar current. The silicon based TMGTFET device demonstrates good performance which makes it a suitable candidate for low power applications with ON current of 0.386 µA/µm, average sub-threshold swing of 32.06 mV/decade, maximum current gain cut off frequency of 41.4 GHz and extremely low OFF current value of the order of 10-20A/µm. We have performed the device optimization to boost the ON current and improve the sub-threshold slope in order to make sure that this device configuration becomes suitable for both low power and high performance applications. The proposed hetero dielectric tri material gate tunnel FET device (HD-TFET) designed in gate all around configuration achieves 19.7 times improvement in ON current as compared to TMGTFET device and excellent average sub-threshold swing of 21.2 mV/decade. The maximum unity current gain frequency is also improved by 3 times indicating its potential for deployment in high frequency applications.

Structural Safety Assessment of Ocean‐Floating Photovoltaic Structure Model

AbstractIn designing photovoltaic (PV) structures made to float in oceans through use of a buoyant system, one must consider wave load and mooring load in addition to the load applied in PV generation systems installed on land. It is also necessary to study the safety of such floating structures during high tide and low tide, focusing on aspects such as mooring conditions caused by large differences in reservoir depth between low and high water levels. This study focuses on finite element analysis and strength assessment of an ocean‐floating PV structure. The aims of this study are to suggest a structure for a floating PV buoy with a tidal power plant to be installed in Sihwaho Lake, to analyze its safety, and to propose a suitable structure model for an ocean‐floating PV system. As a result of structural analysis and safety assessment of the proposed unit structure, the maximum unity check (UC) value of allowable stress design (ASD) for load conditions with maximum stress was found to be much smaller than the reference value, indicating a sufficient degree of safety. In the structural design of floating PV generation systems, wind and wave loads must be considered in the detailed design of the overall and local structure. A 20 kW ocean‐floating PV system was developed in November 2013 based on this study.

IJARCCE - Computer and Communication Engineering

The demand of power system continuously increases day by day. So many problems are incurred also, like flow violation in transmission lines, voltage depression in busses, static/dynamic instabilities, voltage collapse and so on. The solution adopted by the maximum unity is the Flexible AC Transmission Systems (FACTS) devices. Most of the problem faces by us are minimized by the FACT devices but how we utilize the power of FACT devices is now a days a matter of concern. Because optimization is needed for control and efficient utilization of FACT devices. Therefore in this paper an analysis based on the previous research is being presented.

A Fast Low Dropout Regulator with High Slew Rate and Large Unity-Gain Bandwidth

A low dropout regulator (LDO) with fast transient responses is presented. The proposed LDO eliminates the trade-off between slew rate and unity gain bandwidth, which are the key parameters for fast transient responses. In the proposed buffer, by changing the slew current path, the slew rate and unity gain bandwidth can be controlled independently. Implemented in 0.18- ㎛ high voltage CMOS, the proposed LDO shows up to 200 ㎃ load current with 0.2V dropout voltage for 1㎌ output capacitance. The measured maximum transient output voltage variation, minimum quiescent current at no load condition, and maximum unity gain frequency are 24 ㎷, 7.5㎂, and higher than 1 ㎒, respectively.

Comparative analysis of unity gain frequency of top and bottom-contact organic thin film transistors

This work shows that placement of source/drain contacts on top of organic semiconductor film in top-contact organic thin film transistors (OTFT) can offer significant improvement in device speed as compared to bottom-contact devices. 2D numerical simulations and analytical models for unity gain frequency are used to quantify the differences between the top and bottom-contact devices. It is shown that while transconductance is lower in top-contact devices, the gate–drain capacitance is significantly lower as well resulting in improved frequency performance. It is also shown that there is an optimum semiconductor film thickness at which maximum unity gain frequency in top-contact OTFT is obtained.

High-performance noise-tolerant circuit techniques for CMOS dynamic logic

Dynamic CMOS gates are widely exploited in high-performance designs because of their speed. However, they suffer from high noise sensitivity. The main reason for this is the sub-threshold leakage current flowing through the evaluation network. This problem becomes more and more severe with continuous scaling of the technology. A new circuit technique for increasing the noise tolerance of dynamic CMOS gates is studied. A comparison with previously reported schemes is presented. Simulations proved that, when 90 nm CMOS technology is used to realise wide fan-in gates, the proposed design technique can achieve the highest level of noise robustness. A 16 bits OR gate designed as proposed here shows a maximum unity noise gain of 675 mV, a computational delay of ∼115 ps and an energy dissipation of ∼33 fJ. Moreover, at the parity of energy-delay product (EDP), the novel approach achieves a noise robustness 10% higher than the most efficient technique existing in the literature, whereas, at the parity of noise robustness, it exhibits an EDP 33% lower.

Investigation of scaling of InSb MOSFETs through drift–diffusion simulation

Models needed for drift–diffusion simulation of InSb MOSFETs in commercially available simulator are presented and applied to the problem of scaling of the exclusion/extraction InSb MOSFETs. Non-parabolicity, degeneracy, mobility and Auger recombination/generation are explained and modeled. Leakage current and maximum unity current gain frequency of the exclusion/extraction MOSFET are examined and its scaling properties down to 0.15μm are analyzed. Because of its high mobility and saturation velocity, InSb shows promise as a material for THz active devices operating at very low voltages, despite its low bandgap and resulting leakage currents.

A Si bipolar 5-Gb/s 8:1 multiplexer and 4.2-Gb/s 1:8 demultiplexer

Conventionally, ultrahigh-speed 2:1 multiplexers and 1:2 demultiplexers have been demonstrated with HBTs, MESFETs, and Si BJTs. Multiplexers and demultiplexers with a high number of bits are desirable to simplify a system. Si bipolar circuits and package design technology for a 5-Gb/s 8:1 multiplexer and a 4.2 Gb/s 1:8 demultiplexer are described. These multigigabit LSIs have been achieved mainly by switching current optimization within the limit of keeping a maximum unity unilateral gain frequency (f/sub max/), by careful circuit and layout design considering accurate parasitic capacitance modeling, and by using a high-speed Si bipolar technology. These LSIs are housed in a newly developed 56-pin six-layer ceramic package with chip resistors for ECL termination and chip capacitors for good RF grounding. >