Maximum Toggle Frequency Research Articles

Improvement of RCA transistor using RTA annealing after the formation of interfacial oxide

A polysilicon emitter RCA transistor (an ultra-thin interfacial oxide layer exists between polysilicon and silicon emitter) is presented which can operate at 77 K for the first time. An ultra-thin (1.5 nm) interfacial oxide layer is grown deliberately between polysilicon and silicon emitter using RCA oxidation and excellent device stability is obtained after rapid thermal annealing (RTA) treatment in nitrogen atmosphere. The RCA transistor exhibits good electrical performance at very low temperature for an emitter area of 3 /spl times/ 8 /spl mu/m/sup 2/. The maximum toggle frequency of a 1:2 static divider is 1.2 GHz and 732 MHz at 300 K and 77 K, respectively.

1.2-Gb/s true PECL 100K compatible I/O interface in 0.35-μm CMOS

This paper describes the design and the implementation of input-output (I/O) interface circuits for serial data links in the gigabit-per-second range. The cells were implemented in a 3.3-V 0.35-/spl mu/m CMOS technology in a couple of test chips. The transmitter is fully compatible (DC coupling) with 100K positive emitter-coupled logic (PECL) systems and it is based on the voltage-switching principle in order to allow different termination schemes besides the canonical ECL termination, i.e., 50-/spl Omega/ toward (V/sub DD/-2) V. The addition of some circuit techniques such as dynamic biasing and strobed current switching boosts the dynamic performance of the basic voltage-switching scheme and relaxes the requirements for a high bias current and large-size output devices at the same time. Moreover, thanks to the developed reference circuit, using both feedforward and feedback controls, the output levels are within the 100K tolerance over the full range of process, supply voltage, and temperature (PVT) variations without resorting to external components or on-chip trimming. The receiver cell is based on a complementary-differential architecture providing high speed and low error on the duty cycle of the CMOS output signal. The integrated receiver-transmitter chain exhibits a maximum toggle frequency of 1 GHz, while a chip-to-chip transmission link using the developed I/O interface was tested up to 1.2 Gb/s.

SMALL-SCALE InGaP/GaAs HETEROJUNCTION BIPOLAR TRANSISTORS FOR HIGH-SPEED AND LOW-POWER INTEGRATED-CIRCUIT APPLICATIONS

Small-scale InGaP/GaAs heterojunction bipolar transistors (HBTs) with high-speed as well as low-current operation are demonstrated. To reduce the emitter size SE and the base-collector capacitance CBC simultaneously, the HBTs are fabricated by using WSi/Ti as the base electrode and by burying SiO 2 in the extrinsic collector region. WSi/Ti metals simplify and facilitate processing to fabricate small base electrodes, and the buried SiO 2 reduces the parasitic CBC under the base electrode. The cutoff frequency fT of 156 GHz and the maximum oscillation frequency f max of 255 GHz were obtained at a collector current Ic of 3.5 mA for the HBT with SE of 0.5 μ m ×4.5 μ m , and fT of 114 GHz and f max of 230 GHz were obtained at IC of 0.9 mA for the HBT with SE of 0.25 μ m ×1.5 μ m . A 1/8 static frequency divider operated at a maximum toggle frequency of 39.5 GHz with a power consumption per flip-flop of 190 mW. A transimpedance amplifier provides a gain of 46.5 dB·Ω with a bandwidth of 41.6 GHz at a power consumption of 150 mW. These results indicate the great potential of our HBTs for high-speed. low power integrated circuit applications.

High-speed small-scale InGaP/GaAs HBT technology and its application to integrated circuits

We have developed the advanced performance, small-scale InGaP/GaAs heterojunction bipolar transistors (HBTs) by using WSi/Ti base electrode and buried SiO/sub 2/ in the extrinsic collector. The base-collector capacitance C/sub BC/ was further reduced to improve high-frequency performance. Improving the uniformity of the buried SiO/sub 2/, reducing the area of the base electrode, and optimizing the width of the base-contact enabled us to reduce the parasitic capacitance in the buried SiO/sub 2/ region by 50% compared to our previous devices. The cutoff frequency f/sub T/ of 156 GHz and the maximum oscillation frequency f/sub max/ of 255 GHz were obtained at a collector current I/sub C/ of 3.5 mA for the HBT with an emitter size S/sub E/ of 0.5/spl times/4.5 /spl mu/m/sup 2/, and f/sub T/ of 114 GHz and f/sub max/ of 230 GHz were obtained at I/sub C/ of 0.9 mA for the HBT with S/sub E/ of 0.25/spl times/1.5 /spl mu/m/sup 2/. We have also fabricated digital and analog circuits using these HBTs. A 1/8 static frequency divider operated at a maximum toggle frequency of 39.5 GHz with a power consumption per flip-flop of 190 mW. A transimpedance amplifier provides a gain of 46.5 dB/spl middot//spl Omega/ with a bandwidth of 41.6 GHz at a power consumption of 150 mW. These results indicate the great potential of our HBTs for high-speed, low-power circuit applications.

80 GHz 4:1 frequency divider IC using non-self-aligned InP/InGaAs heterostructure bipolar transistors

80 GHz operation has been attained for a divide-by-four frequency divider IC fabricated with non-self-aligned InP/InGaAs heterostructure bipolar transistors. To the authors' knowledge, this is the fastest digital frequency divider IC reported to date. The measured maximum toggle frequency of 80 GHz was the upper limit of the measurement setup.

Ultra-low-power and high-speed SiGe base bipolar transistors for wireless telecommunication systems

Ultra-low-power and high-speed SiGe base bipolar transistors that can be used in RF sections of multi-GHz telecommunication systems have been developed. The SiGe base and a poly-Si/SiGe base-contact were formed by selective growth in a self-aligned manner. The transistors have a very small base-collector capacitance (below 1 fF for an emitter area of 0.2/spl times/0.7 /spl mu/m) and exhibit a high maximum oscillation frequency (30-70 GHz) at low current (5-100 /spl mu/A). The power-delay product of an ECL ring oscillator is only 5.1 fJ/gate for a 250-mV voltage swing. The maximum toggle frequency of a one-eighth static divider is 4.7 GHz at a switching current of 68 /spl mu/A/FF.

Over-60-GHz design technology for an SCFL dynamic frequency divider using InP-based HEMTs

A toggle operation of 39-63.5 GHz without tuning has been achieved by a digital dynamic frequency divider (DFD). The DFD employs a pair of clocked inverters (CIs) with source-coupled FET logic (SCFL) and uses 0.1-/spl mu/m-gate InAlAs/InGaAs/InP high electron-mobility transistors (HEMTs) of good uniformity and high performance. On a 2-in wafer, the frequency divider showed a maximum toggle frequency (f/sub tog,max/) of 59.1/spl plusmn/3.3 GHz and a fabrication yield of 89%. This is the highest operation frequency ever reported for a broad-band digital frequency divider. Comparison of the DFD and the static frequency divider (SFD) showed that the ratio of f/sub tog,max/ for the DFD to that for the SFD is much higher than the value expected from the linear-response theory. The comparison also showed that the ratio of the measured f/sub tog,max/ for the DFD to that for the SFD is 1.7, in contrast with the value of two expected from the circuit simulation. Delay-time analysis revealed that this 15% decrease of the ratio is due to the transmission delay of interconnections and charging time for stray capacitance.

High-yield design technologies for InAlAs/InGaAs/InP-HEMT analog-digital ICs

Sixty-GHz-band two-stage monolithic low-noise amplifiers and ultrahigh-speed SCFL static frequency dividers have been fabricated using the same InAlAs/InGaAs/InP HEMT process. This process assures uniformity by taking advantage of a 0.1-/spl mu/m T-shaped gate and an InP recess-etch stopper. Circuits are designed with priorities on stable operation, high yield, and uniformity. For the low-noise amplifier, the stabilization is optimized so as to minimize noise for the design gain while maintaining stability at all frequencies. The resultant amplifiers show a fabrication yield of 75% and at 62 GHz have a noise figure of 4.3/spl plusmn/0.19 dB and a gain of 11.8/spl plusmn/0.25 dB. For the frequency divider, the load resistance is set to be large enough to assure stable operation (circuit simulation shows that increasing the load resistance has little effect on the maximum toggle frequency). Frequency dividers designed with the optimum load resistance for stable and high-speed operation show a fabrication yield of 63% and have a maximum toggle frequency of 36.7/spl plusmn/0.55 GHz. These results demonstrate the feasibility of using this HEMT process to monolithically integrate analog and digital circuits on one chip.

Novel high-speed flip-flop circuit with low power consumption using GaAs junction FETs

A novel flip-flop circuit configuration is proposed for very high speed GaAs LSIs. A T-connected flip-flop circuit was fabricated using 0.5 μm GaAs junction FETs. It operates at a maximum toggle frequency of 7.0 GHz with a power consumption of 10.8 mW.

An analytical maximum toggle frequency expression and its application to optimizing high-speed ECL frequency dividers

A novel method is used to analyze static and regenerative frequency dividers by relating their performance to that of the constituent EXCLUSIVE-OR (XOR) gates. It is found that the behavior of the propagation delay of XOR gates is quite linear, and this allows the derivation of a propagation delay expression for XOR gates using a sensitivity analysis. The validity of the expression is checked by comparison with SPICE simulations and with results from the literature, and agreement to 10% is obtained. It has been found that this expression can be used to accurately predict the maximum toggle frequency of frequency dividers. Using this expression, it has also been verified that the maximum toggle frequency of regenerative frequency dividers is about twice as high as that of static frequency dividers. In order to optimize frequency dividers, figures of merit for frequency dividers realized in silicon and AlGaAs-GaAs technologies are proposed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

0.15 μm GaAs MESFETs applied to ultrahigh-speed static frequency dividers

0.15 μm gate-length FETs fabricated by SAINT using photolithography are applied to ultrahigh-speed static frequency dividers. Short channel effects are suppressed by a buried p-layer and shallow active layers formed by low energy implantations and rapid thermal annealing. The maximum cutoff frequency of the 0.15 μm gate-length FETs was 80.6 GHz. The maximum toggle frequency of the LSCFL one-quarter frequency divider is 26.8 GHz with a power dissipation of 263 mW.

CMOS-Compatible bipolar and I2L technology using three-level epitaxial layers for analog/Digital VLSI's

A high-performance bipolar/I2L/CMOS on-chip technology has been developed. To combine all devices, three-level epitaxial layers Were used. Both n-p-n and lateral p-n-p bipolar transistors, and p-channel MOSFET's were fabricated on the top level epitaxial layer. I2L and n-channel MOSFET's were fabricated on the middle and bottom levels, respectively. Using a thin epitaxial layer and simultaneously reducing the level of regions for n-channel MOSFET's and bi-polar isolation grooves, the process sequence was designed to be as simple as possible. Bipolar n-p-n transistors with a maximum cutoff frequency of 5 GHz, I2L circuits having 40-MHz maximum toggle frequency, and CMOS devices operating at a minimum propagation delay time of 300 ps/gate were developed compatibly. This technology has feasibility for application to multifunctional analog/digital VLSI's.

A high-speed frequency divider using n+-Ge Gate AlGaAs/GaAs MISFET's

A high-speed divide-by-four static frequency divider is fabricated using n+ -Ge gate AlGaAs/GaAs heterostructure MISFET's. The divider circuit consists of two master-slave T-type flip-flops (T-FF's) and an output buffer based on source-coupled FET logic (SCFL). A maximum toggle frequency of 11.3 GHz with a power dissipation of 219 mW per T-F/F is obtained at 300 K using 1.0-µm gate FET's.

High-speed frequency dividers using self-aligned AlGaAs/GaAs heterojunction bipolar transistors

A divide-by-four frequency divider and ring oscillators have been fabricated employing self-aligned AlGaAs/GaAs heterojunction bipolar transistors (HBT's). Maximum toggle frequency of 13.7 GHz and propagation delay time of 17.2 ps are achieved in ECL gate circuitry. These values are the highest and the lowest in ECL circuits and in bipolar circuits, respectively, ever reported.

22 GHz 1/4 frequency divider using AlGaAs/GaAs HBTs

A divide-by-four frequency divider using AIGaAs/GaAs HBTs with GalnAs/GaAs emitter cap layers was designed and fabricated. A maximum toggle frequency of 22.15 GHz was obtained at a power supply voltage of 9 V and a total power dissipation of 712 mW. The minimum input signal power was under 0dBm and the free-running frequency was as high as 20 GHz.

An 11-GHz GaAs frequency divider using source-coupled FET Logic

A GaAs one-fourth frequency divider is fabricated to evaluate the ultrahigh-speed performance of source-coupled FET logic (SCFL) having normally-on FET's with small negative V th values. High-transconductance (240 ms/mm) 1/2-µm gate-length FET's and an air-bridge interconnection line technology are successfully developed. A maximum toggle frequency F <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</inf> of 11 GHz is achieved with a power dissipation of 149 mW. Furthermore, 9.7-GHz F <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</inf> with low power dissipation of 52 mW was also obtained.

New type of dynamic frequency divider for microwave systems operation

A new type of dynamic frequency divider has been demonstrated successfully: a maximum dividing frequency of 8 GHz at room temperature was achieved. As a result of the new proposed design, a maximum toggle frequency of 30 GHz could be obtained after optimisation of various technological parameters. The design and the first experimental results are described and discussed.

High-speed IIL circuits using a sidewall base contact structure

New high-speed self-aligned IIL structures with 3 µm × 3 µm collectors that produce minimum gate delays of 290 ps/gate(fanout is 1) and power delay products of 15 fJ/gate at low injector current levels are described. Maximum toggle frequency in an IIL T-type flip-flop is measured at 5 mW and found to be up to 315 MHz.

High-Speed IIL Circuits Using a Sidewall Base Contact Structure

New high-speed self-aligned IIL structures with 3 /spl mu/m X 3 /spl mu/m collectors that produce minimum gate delays of 290 ps/gate(fanout is 1) and power delay products. of 15 fJ/gate at low injector current levels are described. Maximum toggle frequency in an IIL T-type flip-flop is measured at 5 mW and found to be up to 315 MHz.

10K Gate I2L and 1K component analog compatible bipolar VLSI technology—HIT-2

An advanced analog/digital bipolar VLSI technology that combines on the same chip 2-ns 10K I <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> L gates with 1K analog devices is proposed. The new technology, called high-density integration technology-2 (HIT-2), is based on a new structure concept that consists of three major techniques: shallow grooved-isolation, I <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> L active layer etching, and I <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> L current gain increase. I <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> L circuits with 80-MHz maximum toggle frequency have developed compatibly with n-p-n transistors having a BV <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CEO</inf> of more than 10 V and an f <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> of 5 GHz, and lateral p-n-p transistors having an f <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> of 150 MHz.