Maximum IR-drop Research Articles

IR-drop modeling and reduction for high-performance printed circuit boards

In this paper, IR drop reduction of high-performance printed circuit boards (PCBs) is discussed. The IR drop of multilayer PCB is analyzed by using model decomposition and adaptive mesh. It is shown that both the via contact of voltage regulator module (VRM) and the copper planes produce significant IR drop. A star topology is proposed for IR drop reduction, which can significantly reduce the resistance introduced by the via contact of VRM and the copper planes. Star topology can reduce the IR drop by about 50%. Furthermore, the efficiency of through via design on the IR drop reduction for multi-plane structures is analyzed. Through via design rules and radial via array are presented for maximum IR drop reduction. With proper design of through vias, the IR drop of N planes can be reduced to 1/N of that of a single plane. Using star topology in multi-plane structure, the IR drop of PCBs with current demand of 100+A can be kept within a few tens of millivolt.

A Physical-Location-Aware X-Bit Redistribution for Maximum IR-Drop Reduction

To guarantee that an application-specific integrated circuit (ASIC) meets its timing requirement, at-speed scan testing becomes an indispensable procedure for verifying the performance of ASIC. However, at-speed scan test suffers the test-induced yield loss. Because the switching-activity in test mode is much higher than that in normal mode, the switching-induced large current drawn causes severe IR drop and increases gate delay. X-filling is the most commonly used technique to reduce IR-drop effect during at-speed test. However, the effectiveness of X-filling depends on the number and the characteristic of X-bit distribution. In this paper, we propose a physical-location-aware X-identification which redistributes X-bits so that the maximum switching-activity is guaranteed to be reduced after X-filling. We estimate IR-drop using RedHawk tool and the experimental results on ITC'99 show that our method has an average of 9.42% more reduction of maximum IR-drop as compared to a previous work which redistributes X-bits evenly in all test vectors.

IR-Drop Management in FPGAs

This paper presents novel computer-aided design (CAD) techniques for mitigating IR-drops in field-programmable gate arrays (FPGAs). The proposed placement and routing relies on reducing the switching activities in local regions in the FPGA fabric to improve the profile of the supply voltage distribution. The proposed techniques reduce IR-drops and the variance of the supply voltage distribution across all the nodes in the power grid network. The proposed CAD techniques are efficient as they do not require solving the power grid model at every placement and routing iteration. A reduction of up to 53% in maximum IR-drop and up to 66% reduction in standard deviation of is obtained from the design techniques proposed in this paper with an average impact of 3% on circuit delay.

A Physical-Location-Aware X-Filling Method for IR-Drop Reduction in At-Speed Scan Test

The IR-drop problem during test mode exacerbates delay defects and results in false failures. In this paper, we take the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">X-filling</i> approach to reduce the IR-drop effect during an at-speed test. The main difference between our approach and the previous X-filling approaches lies in two aspects. The first one is that we take the spatial information into consideration in our approach. The second one is how X-filling is performed. We propose a backward-propagation technique instead of a forward-propagation approach taken in previous work. The experimental results show that our approach can reduce 21.1% of the maximum IR-drop in the best case and 9.1% on the average as compared to previous work.

Reconfigurable ECO Cells for Timing Closure and IR Drop Minimization

Unused spare cells occur inevitably in traditional engineering change order (ECO) design flow. It results in inefficient area usage, more leakage, and more IR drop impacts. To tackle these problems, a reconfigurable cell is proposed, which serves the dual purposes of decoupling capacitance and spare cell in this paper. Before ECO is applied, these cells are preplaced as decoupling capacitors. When ECO is applied, these cells are configured as functional cells. To demonstrate the efficiency of our configurable cell, we propose an algorithm for timing closure and IR drop minimization. Compared with traditional ECO flow, our method shows 15% reduction in maximum IR drop and 9% reduction in leakage before applying ECO, and 7% reduction in maximum IR drop after applying ECO, with 10% area of spare cells. In addition, we show that there remain less unsolved timing-violation paths after applying our ECO timing optimization flow due to less IR drop and free selection of ECO gate type.