Massive Parallel Processing Research Articles

Natural biomaterials for sustainable flexible neuromorphic devices

Neuromorphic electronics use neural models in hardware to emulate brain-like behavior, and provide power-efficient, extremely compact, and massively-parallel processing, so they are ideal candidates for next-generation information-processing units. However, traditional rigid neuromorphic devices are limited by their unavoidable mechanical and geometrical mismatch with human tissues or organs. At the same time, the rapid development of these electronic devices has generated a large amount of electronic waste, thereby causing severe ecological problems. Natural biomaterials have mechanical properties compatible with biological tissues, and are environmentally benign, ultra-thin, and lightweight, so use of these materials can address these limitations and be used to create next-generation sustainable flexible neuromorphic electronics. Here, we explore the advantages of natural biomaterials in simulating synaptic behavior of sustainable neuromorphic devices. We present the flexibility, biocompatibility, and biodegradability of these neuromorphic devices, and consider the potential applicability of these properties in wearable and implantable bioelectronics. Finally, we consider the challenges of device fabrication and neuromorphic system integration by natural biomaterials, then suggest future research directions.

Modern approaches to data storage: comparison of relational and cloud data warehouses using etl and elt methods

The paper analyses various aspects of the use of relational and cloud data warehouses as well as methods of integrating ETL and ELT data. A comparative analysis of these approaches, their advantages and disadvantages are provided. A central relational data warehouse is proposed that provides a single version of truth (SVOT), which allows standardising and structuring data, avoiding differences and providing the access to the same information for all users of an organisation. It is analysed the methodological approaches to implementing a data warehouse: top-down, bottom-up, and from middle. It is described cloud data warehouses that use cloud technologies to provide scalability, availability and fault tolerance, which is important for the companies with huge amounts of data. The advantages and disadvantages of ETL and ELT are analysed: ETL transforms data before it is loaded into the warehouse, which makes it easier to maintain data confidentiality. ELT performs transformation after loading, which allows for more flexible data processing directly in the warehouse. In the article, we deal with the approaches to implementing a data warehouse: top-down is suitable for strategic planning, bottom-up allows for faster results, and the middle approach combines both methods to achieve optimal efficiency. We considered cloud data storage: compared to relational storage, cloud storage is more flexible, scalable and efficient, providing speed and reducing infrastructure costs. It is described cloud storage architectures: massive parallel processing, hybrid architectures, lambda architectures, and multi-structured architectures. They provide high performance and flexibility in data processing. It is described data storage technologies: Data Lake, Polyglot Persistence, Apache Iceberg, Apache Parquet, and columnar databases that provide efficient storage and processing of large amounts of data

Chip-Level Defect Analysis with Virtual Bad Wafers Based on Huge Big Data Handling for Semiconductor Production

Semiconductors continue to shrink in die size because of benefits like cost savings, lower power consumption, and improved performance. However, this reduction leads to more defects due to increased inter-cell interference. Among the various defect types, customer-found defects are the most costly. Thus, finding the root cause of customer-found defects has become crucial to the quality of semiconductors. Traditional methods involve analyzing the pathways of many low-yield wafers. Yet, because of the extremely limited number of customer-found defects, obtaining significant results is difficult. After the products are provided to customers, they undergo rigorous testing and selection, leading to a very low defect rate. However, since the timing of defect occurrence varies depending on the environment in which the product is used, the quantity of defective samples is often quite small. Unfortunately, with such a low number of samples, typically 10 or fewer, it becomes impossible to investigate the root cause of wafer-level defects using conventional methods. This paper introduces a novel approach to finding the root cause of these rare defective chips for the first time in the semiconductor industry. Defective wafers are identified using rare customer-found chips and chip-level EDS (Electrical Die Sorting) data, and these newly identified defective wafers are termed vBADs (virtual bad wafers). The performance of root cause analysis is dramatically improved with vBADs. However, the chip-level analysis presented here demands substantial computing power. Therefore, MPP (Massive Parallel Processing) architecture is implemented and optimized to handle large volumes of chip-level data within a large architecture infrastructure that can manage big data. This allows for a chip-level defect analysis system that can recommend the relevant EDS test and identify the root cause in real time even with a single defective chip. The experimental results demonstrate that the proposed root cause search can reveal the hidden cause of a single defective chip by amplifying it with 90 vBADs, and system performance improves by a factor of 61.

GAZE DIRECTION MONITORING MODEL IN COMPUTER SYSTEM FOR ACADEMIC PERFORMANCE ASSESSMENT

This paper focuses on the research and application of eye movement and gaze direction analysis in online testing systems. The practical novelty of the proposed model of monitoring the direction of gaze in a computer-based knowledge control system lies in the possibility of automated remote control over a large audience of students. The practical significance lies in creating the same conditions for computer testing for all students and increasing the correspondence of knowledge level to the received test results. The implemented and tested system is relevant and necessary in higher educational institutions, particularly in Ukraine, where remote education has emerged as the safest means of acquiring knowledge. This is especially true for fields of study where practical tasks and laboratory work do not necessitate a student's physical presence at the institution. That is why the application of the latest information technologies is extremely important. The dynamic authentication based on the sequence of eye movements proposed in the model allows error-free user's eye area detection for further analysis of the test subject's behavior. The proposed authentication method excludes the need to enter passwords or CAPTCHAs, ensures the speed of determining the user's presence. Further analysis of the user's direction of vision includes responding to the information received, such as skipping a question or the need for re-authorization. Question skipping occurs when the system decides that the user has not been looking at the screen for an extended period (looking sideways, down, up for more than 30 seconds). Re-authentication becomes necessary if the user exits the test or if there is a user replacement. Real-time gaze control capability is implemented by using massive parallel processing system (NVIDIA GeForce GTX 1650 graphics card) for calculations. The analysis of the results obtained shows that the proposed approach allows gaze detection at different illumination ranges (from 0.3 lux to 10,000 lux), as well as to detect states of the user's eyes that violating test rules for further system response (skipping a question or re-authentication request).

Site-Specific Emulation of Neuronal Synaptic Behavior in Au Nanoparticle-Decorated Self-Organized TiOx Surface.

Neuromorphic computing is a potential approach for imitating massive parallel processing capabilities of a bio-synapse. To date, memristors have emerged as the most appropriate device for designing artificial synapses for this purpose due to their excellent analog switching capacities with high endurance and retention. However, to build an operational neuromorphic platform capable of processing high-density information, memristive synapses with nanoscale footprint are important, albeit with device size scaled down, retaining analog plasticity and low power requirement often become a challenge. This paper demonstrates site-selective self-assembly of Au nanoparticles on a patterned TiOx layer formed as a result of ion-induced self-organization, resulting in site-specific resistive switching and emulation of bio-synaptic behavior (e.g., potentiation, depression, spike rate-dependent and spike timing-dependent plasticity, paired pulse facilitation, and post tetanic potentiation) at nanoscale. The use of local probe-based methods enables nanoscale probing on the anisotropic films. With the help of various microscopic and spectroscopic analytical tools, the observed results are attributed to defect migration and self-assembly of implanted Au atoms on self-organized TiOx surfaces. By leveraging the site-selective evolution of gold-nanostructures, the functionalized TiOx surface holds significant potential in a multitude of fields for developing cutting-edge neuromorphic computing platforms and Au-based biosensors with high-density integration.

Weighted spin torque nano-oscillator system for neuromorphic computing

Neuromorphic computing is a promising strategy to overcome fundamental limitations, such as enormous power consumption, by massive parallel data processing, similar to the brain. Here we demonstrate a proof-of-principle implementation of the weighted spin torque nano-oscillator (WSTNO) as a programmable building block for the next-generation neuromorphic computing systems (NCS). The WSTNO is a spintronic circuit composed of two spintronic devices made of magnetic tunnel junctions (MTJs): non-volatile magnetic memories acting as synapses and non-linear spin torque nano-oscillator (STNO) acting as a neuron. The non-linear output based on the weighted sum of the inputs is demonstrated using three MTJs. The STNO shows an output power above 3 µW and frequencies of 240 MHz. Both MTJ types are fabricated from a multifunctional MTJ stack in a single fabrication process, which reduces the footprint, is compatible with monolithic integration on top of CMOS technology and paves ways to fabricate more complex neuromorphic computing systems.

Minimum complexity integrated photonic architecture for delay-based reservoir computing.

Reservoir computing is an analog bio-inspired computation scheme for efficiently processing time-dependent signals, the photonic implementations of which promise a combination of massive parallel information processing, low power consumption, and high-speed operation. However, most of these implementations, especially for the case of time-delay reservoir computing, require extensive multi-dimensional parameter optimization to find the optimal combination of parameters for a given task. We propose a novel, largely passive integrated photonic TDRC scheme based on an asymmetric Mach-Zehnder interferometer in a self-feedback configuration, where the nonlinearity is provided by the photodetector, and with only one tunable parameter in the form of a phase shifting element that, as a result of our configuration, allows also to tune the feedback strength, consequently tuning the memory capacity in a lossless manner. Through numerical simulations, we show that the proposed scheme achieves good performance -when compared to other integrated photonic architectures- on the temporal bitwise XOR task and various time series prediction tasks, while greatly reducing hardware and operational complexity.

Orbital-angular-momentum-based optical clustering via nonlinear optics

Machine learning offers a convenient and intelligent tool for a variety of applications in the fields ranging from fundamental research to financial analysis. With the explosive growth of data streams, i.e., “big data,” optical machine learning with the inherent capacity for massive parallel processing is gradually attracting attention. Despite significant experimental and theoretical progress in this area, limited by the coherent manipulation of multibeams, high dimensional optical vector or matrix operation is still challenging. Here, by using the second harmonic generation of high dimensional orbital angular momentum superposition states, we present a compact and robust optical clustering machine, which is the crucial component in machine learning. In experiment, we conduct supervised clustering for classification of three- and eight-dimensional vectors and unsupervised clustering for text mining of 14-dimensional texts both with high accuracies. The presented optical clustering scheme could offer a pathway for constructing high speed and low energy consumption machine learning architectures.

Efficient Point-to-Point Resistance Distance Queries in Large Graphs

We describe a method to efficiently compute point-to-point resistance distances in a graph, which are notoriously difficult to compute from the raw graph data. Our method is based on a relatively compact hierarchical data structure which ''compresses'' the resistance distance data present in a graph, constructed by a nested bisection of the graph using compact edge-cuts. Built and stored in a preprocessing step (which is amenable to massive parallel processing), efficient traversal of a small portion of this data structure supports efficient and exact answers to resistance distance queries. The size of the resulting data structure for a graph of $n$ vertices is $O(nk\log n)$, where $k$ is the size of a balanced edge-cut of the graph. Exact queries then require $O(k\log n)$ worst-case time and $O(k)$ average-case time. Approximate values may be obtained significantly faster by applying standard dimension reduction techniques to the ''coordinates'' stored in the structure.

Robust massive parallel information processing environments in biology and medicine: case study

The current frontiers in the description and simulation of advanced physical and biological phenomena observed within all scientific disciplines are pointing toward the importance of the development of robust mathematical descriptions that are error resilient. Complexity research is lacking deeper knowledge of the design methodology of processes that are capable to recreate the robustness, which is going to be studied on massive-parallel computations (MPCs) implemented by cellular automata (CA). A simple, two-state cellular automaton having an extremely simple updating rule, which was created by John H. Conway called the ’Game of Life’ (GoL) is applied to simulate and logic gate using emergents. This is followed by simulations of a robust, generalized GoL, which works with nine states instead of two, that is called R-GoL (open-source). extra states enable higher intercellular communication. The logic gate is simulated by the GoL. It is destroyed by injection of random faulty evaluations with even the smallest probability. The simulations of the R-GoL are initiated with random values. several types of emergent structures, which are robust to injection of random errors, are observed for different setups of the R-GoL rule. The GoL is not robust. The R-GoL is capable to create and maintain oscillating, emergent structures that are robust under constant injection of random, faulty evaluations with up to 1% of errors. The R-GoL express long-range synchronization, which is together with robustness facilitated by designed intercellular communication.

G-tran

Graph transaction processing poses unique challenges such as random data access due to the irregularity of graph structures, low throughput and high abort rate due to the relatively large read/write sets in graph transactions. To address these challenges, we present G-Tran, a remote direct memory access (RDMA)-enabled distributed in-memory graph database with serializable and snapshot isolation support. First, we propose a graph-native data store to achieve good data locality and fast data access for transactional updates and queries. Second, G-Tran adopts a fully decentralized architecture that leverages RDMA to process distributed transactions with the massively parallel processing (MPP) model, which can achieve high performance by utilizing all computing resources. In addition, we propose a new multi-version optimistic concurrency control (MV-OCC) protocol with two optimizations to address the issue of large read/write sets in graph transactions. Extensive experiments show that G-Tran achieves competitive performance compared with other popular graph databases on benchmark workloads.

KmerKeys: a web resource for searching indexed genome assemblies and variants.

K-mers are short DNA sequences that are used for genome sequence analysis. Applications that use k-mers include genome assembly and alignment. However, the wider bioinformatic use of these short sequences has challenges related to the massive scale of genomic sequence data. A single human genome assembly has billions of k-mers. As a result, the computational requirements for analyzing k-mer information is enormous, particularly when involving complete genome assemblies. To address these issues, we developed a new indexing data structure based on a hash table tuned for the lookup of short sequence keys. This web application, referred to as KmerKeys, provides performant, rapid query speeds for cloud computation on genome assemblies. We enable fuzzy as well as exact sequence searches of assemblies. To enable robust and speedy performance, the website implements cache-friendly hash tables, memory mapping and massive parallel processing. Our method employs a scalable and efficient data structure that can be used to jointly index and search a large collection of human genome assembly information. One can include variant databases and their associated metadata such as the gnomAD population variant catalogue. This feature enables the incorporation of future genomic information into sequencing analysis. KmerKeys is freely accessible at https://kmerkeys.dgi-stanford.org.

Estimate the Performance of Cloudera Decision Support Queries

Hive and Impala queries are used to process a big amount of data. The overwriting amount of information requires an efficient data processing system. When we deal with a long-term batch query and analysis Hive will be more suitable for this query. Impala is the most powerful system suitable for real-time interactive Structured Query Language (SQL) query which are added a massive parallel processing to Hadoop distributed cluster. The data growth makes a problem with SQL Cluster because the execution processing time is increased. In this paper, a comparison is demonstrated between the performance time of Hive, Impala and SQL on two different data models with different queries chosen to test the performance. The results demonstrate that Impala outperforms Hive and SQL cluster when it comes to analyze data and processing tasks. Using two benchmark datasets, TPC-H and statistical computing, we compare the performance of Hive, Impala, and SQL clusters 2009 Statistical Graphics Data Expo.

Multi-GPU Efficient Indexing For Maximizing Parallelism of High Dimensional Range Query Services

Numerous research efforts have been proposed for efficient processing of range queries in high-dimensional space by either redesigning R-tree access structure for exploring massive parallelism on single GPU or exploring distributed framework of R-tree. However, none of the existing efforts explores the integration of the parallelization of the R-tree on a single GPU with a distributed framework for the R-tree. The problem of designing an efficient multi-GPU indexing method, which can effectively combine the parallelism maximization with distributed processing of the R-tree, remains an open challenge. In this article, we present a novel multi-GPU efficient parallel and distributed indexing method, called LBPG-tree. The rationale of the LBPG-tree is to combine the advantages of an instruction pipeline in CPU with the massive parallel processing potential of multiple GPUs by introducing two new optimization strategies: First, we exploit the GPU L2 cache for accelerating both index search and index node access on GPUs. Second, we further improve utilization of L2 cache on GPUs by compacting and sorting candidate nodes called Compact-and-Sort. Our experimental results show that the LBPG-tree outperforms G-tree, the previous representative GPU index method and effectively support multiple GPUs for providing efficient high dimensional range query service.

Parallel Analog Computing Based on a 2×2 Multiple-Input Multiple-Output Metasurface Processor With Asymmetric Response

We present a polarization-insensitive metasurface processor to perform spatial asymmetric filtering of an incident optical beam, thereby allowing for real-time parallel optical processing. To enable massive parallel processing, we introduce a novel Multi Input-Multi Output (MIMO) computational metasurface with an asymmetric optical response that can perform spatial differentiation on two distinct input signals regardless of their polarization. In our scenario, two distinct signals set in x and y directions, parallel and perpendicular to the incident plane, illuminate simultaneously the metasurface processor, and the resulting differentiated signals are separated from each other via appropriate Spatial Low Pass Filters (SLPF). By leveraging Generalized Sheet Transition Conditions (GSTCs) and surface susceptibility tensors, we design an asymmetric meta-atom augmented with normal susceptibilitiesto reach asymmetric optical response at normal beam illumination. Proof-of-principle simulations are also reported along with the successful realization of signal processing functions. The proposed metasurface overcomes major shortcomings imposed by previous studies such as large architectures arising from the need of additional subblocks, slow responses, and most importantly, supporting only a single input with a given polarization. Our results set the path for future developments of material-based analog computing using efficient and easy-to-fabricate MIMO processors for compact, fast, and integrable computing elements without any Fourier lens.

Neural Network Optimization Method and Its Application in Information Processing

Neural network theory is the basis of massive information parallel processing and large-scale parallel computing. Neural network is not only a highly nonlinear dynamic system but also an adaptive organization system, which can be used to describe the intelligent behavior of cognition, decision-making, and control. The purpose of this paper is to explore the optimization method of neural network and its application in information processing. This paper uses the characteristic of SOM feature map neural network to preserve the topological order to estimate the direction of arrival of the array signal. For the estimation of the direction of arrival of single-source signals in array signal processing, this paper establishes a uniform linear array and arbitrary array models based on the distance difference vector to detect DOA. The relationship between the DDOA vector and the direction of arrival angle is regarded as a mapping from the DDOA space to the AOA space. For this mapping, through derivation and analysis, it is found that there is a similar topological distribution between the two variables of the sampled signal. In this paper, the network is trained by uniformly distributed simulated source signals, and then the trained network is used to perform AOA estimation effect tests on simulated noiseless signals, simulated Gaussian noise signals, and measured signals of sound sources in the lake. Neural network and multisignal classification algorithms are compared. This paper proposes a DOA estimation method using two-layer SOM neural network and theoretically verifies the reliability of the method. Experimental research shows that when the signal-to-noise ratio drops from 20 dB to 1 dB in the experiment with Gaussian noise, the absolute error of the AOA prediction is small and the fluctuation is not large, indicating that the prediction effect of the SOM network optimization method established in this paper does not vary. The signal-to-noise ratio drops and decreases, and it has a strong ability to adapt to noise.

TMA: Tera‐MACs/W neural hardware inference accelerator with a multiplier‐less massive parallel processor

SummaryComputationally intensive inference tasks of deep neural networks have brought about a revolution in accelerator architecture, aiming to reduce power consumption as well as latency. The key figure‐of‐merit in hardware inference accelerators is the number of multiply‐and‐accumulation operations per watt (MACs/W); the state‐of‐ the‐art MACs/W, so far, has been several hundreds Giga‐MACs/W. We propose a Tera‐ MACS/W neural hardware inference accelerator (TMA) with 8‐bit activations and scalable integer weights less than 1‐byte. The architecture's main feature is a configurable neural processing element for matrix‐vector operations. The proposed neural processing element uses a multiplier‐less massive parallel processor that works without multipliers, which makes it attractive for energy efficient high‐performance neural network applications. We benchmark our system's latency, power, and performance using Alexnet trained on ImageNet. Finally, we compared our accelerator's throughput and power consumption to that of the prior works. The proposed accelerator outperforms the state‐of‐the‐art counterparts, in terms of the energy and area efficiency, achieving 2.3 TMACs/W@1.0 V on a 28‐nm Virtex‐7 FPGA chip.

HETEROGENEOUS COMPUTING TO ACCELERATE THE SEARCH OF SUPER K-MERS BASED ON MINIMIZERS

The k-mers processing techniques based on partitioning of the data set on the disk using minimizer-type seeds have led to a significant reduction in memory requirements; however, it has added processes (search and distribution of super k-mers) that can be intensive given the large volume of data. This paper presents a massive parallel processing model in order to enable the efficient use of heterogeneous computation to accelerate the search of super k-mers based on seeds (minimizers or signatures). The model includes three main contributions: a new data structure called CISK for representing the super k-mers, their minimizers and two massive parallelization patterns in an indexed and compact way: one for obtaining the canonical m-mers of a set of reads and another for searching for super k-mers based on minimizers. The model was implemented through two OpenCL kernels. The evaluation of the kernels shows favorable results in terms of execution times and memory requirements to use the model for constructing heterogeneous solutions with simultaneous execution (workload distribution), which perform co-processing using the current search methods of super k -mers on the CPU and the methods presented herein on GPU. The model implementation code is available in the repository: https://github.com/BioinfUD/K-mersCL.

Modification and hardware implementation of cortex‐like object recognition model

Object recognition in the visual cortex of mammals and humans has inspired many computational object recognition models. Hierarchical model and X (HMAX) is a well-known biologically motivated object recognition model with scale and position tolerance and high accuracy. Due to the computational intensive nature, hardware implementation with massive parallel processing is suggested for real-time applications. However, it is important to explore algorithmic trade-offs when mapping an algorithm to are configurable hardware. A direct conversion of the software implementation of an algorithm generally results inefficient hardware resource usage. In this study, the authors propose a novel modification into the HMAX model which makes it suitable for hardware implementation. More precisely, to reduce the number of memory blocks and multipliers of the S2 layer of HMAX produces, they replace the first norm by the second norm, which critically affects the silicon area in an application-specific integrated circuit implementation or the required resources in field-programmable gate array (FPGA). To evaluate the proposed model, they implement a pipelined version of the revised model on a mid-range commercial Xilinx FPGA, i.e. XC6VLX240T platform from a Virtex 6 family of Xilinx using ISE. Compared to the recent hardware implementation of HMAX, the proposed model offers 83% resource degradation in DSP48 slices and 3% in memory blocks.

A 703.4-GOPs/W Binary SegNet Processor With Computing-Near-Memory Architecture for Road Detection

This article proposes a deep learning accelerator with computing-near-memory (CNM) architecture for road detection, which is widely used in driving assistance and automotive driving. The work demonstrates an integrated software/hardware co-design approach. At the algorithm level, a 20-layer binary SegNet is developed. At the hardware level, the accelerator has an optimized CNM architecture with massive bit-level parallel processing elements and pipelines for low latency of the critical path.