Mass Reflow Research Articles

Brittle Fracture Behavior of Sn-Ag-Cu Solder Joints with Ni-Less Surface Finish via Laser-Assisted Bonding.

In this study, we investigated the brittle fracture behavior of Sn-3.0Ag-0.5Cu (SAC305) solder joints with a Direct Electroless Gold (DEG) surface finish, formed using laser-assisted bonding (LAB) and mass reflow (MR) techniques. Commercial SAC305 solder balls were used to ensure consistency. LAB increases void fractions and coarsens the primary β-Sn phase with higher laser power, resulting in a larger eutectic network area fraction. In contrast, MR produces solder joints with minimal voids and a thicker intermetallic compound (IMC) layer. LAB-formed joints exhibit higher high-speed shear strength and lower brittle fracture rates compared to MR. The key factor in the reduced brittle fracture in LAB joints is the thinner IMC layer at the joint interface. This study highlights the potential of LAB in enhancing the mechanical reliability of solder joints in advanced electronic packaging applications.

Thermo-compression Bonding Assembly Technology

With the slowing of Moore’s law heterogeneous integration and assembly became important drivers of the performance of semiconductor packaging. This “More than Moore” approach enables higher functional density and higher bandwidth packages. At the same time, heterogeneous integration drives an aggressive interconnect pitch roadmap, pushing the limits of Advanced Packaging technologies. Flip chip with mass reflow has been the main assembly technology for fine pitch interconnect. However, the need for even finer pitch and higher packaging density was not compatible with the limitations imposed by the mass reflow process, therefore requiring new interconnect technologies. Local reflow flip chip via thermocompression bonding (TCB) overcomes limitations due to CTE-mismatch and warpage. Meanwhile, TCB based on solder micro-bumps became a well-established and cost effective fine-pitch interconnect process and Cu to Cu Hybrid Bonding is emerging as a technology for the future. Normal TCB typically requires the application of flux and post-bond flux cleaning as any flux residue can result in post mold package reliability issues, even for ‘no-clean’ flux materials. Post-bond flux cleaning, however, becomes more and more difficult for increasing die size and with bump pitch and stand-off height shrinking even further. K&S has developed and demonstrated a flux-less TCB process for large and high-density interconnect die that utilizes in-situ Formic Acid (FA) vapor application for copper and solder oxide reduction. This process eliminates the need for flux and, therefore, there is no need for the tedious and time-consuming cleaning of the post bond flux residue. The FA process delivers nearly the same productivity as a conventional flux based TCB process. The FA delivery system can be integrated on our high-accuracy C2S and C2W TCB tools, leveraging the existing HVM TCB infrastructure and extending its application space from ~35µm towards ultra-fine pitch applications around 10µm. Hybrid bonding created a lot of attention over the last years as this bump-less technology allows for long-term pitch scalability, possibly even down to 1µm. Hybrid bonding, however, requires a more complex process flow which relies on pristine die and target wafer surfaces as well as front-end level cleanliness conditions. Accordingly, the advantages and cost of Flux-less TCB as compared to Hybrid bonding should be explored in more detail. TCB can be viewed as an extension of flip chip. Using the existing assembly and metrology infrastructure as well as the existing die and substrate design layouts will be attractive to subcons. As a result, the overall cost and time to market should be much lower. An activity-based cost model has been developed along with SavanSys comparing flux-less TCB and Hybrid bonding. We present results on the process cost as well as the overall package cost as a function of die size and yield. In summary, flux-less thermo-compression bonding should be considered for ultra-fine pitch applications. We have demonstrated pitch capability below 30µm and believe that a pitch of 10µm may be possible. Other applications that formic acid vapor TCB enables are large module bonding (50 X 50 mm, 70 X 70 mm) and Cu to Cu interconnects.

Solder Flux Evolution for Heterogeneous Integration

Advanced packaging techniques continue to evolve within the semiconductor industry. Within advanced packaging, heterogeneous integration has become a solution for those wishing to integrate distinct and complex dies into smaller packages. Many application trends are emerging to meet the challenges of heterogeneous integration which are causing the assembly process to become more intricate, with these trends requiring soldering material technology, especially that of solder flux, to be up to date and cutting-edge. In this paper, three assembly processes that necessitate advanced solder flux will be discussed: flip-chip assembly, BGA ball-attach assembly, and assemblies which have advanced to necessitate fluxless component attach. First, flip-chip assembly methods will be discussed and how different assembly technologies, such as standard mass reflow, thermocompression bonding (TCB), and laser assisted bonding (LAB), require differently formulated fluxes. This paper will then discuss the ball grid array assembly process, first outlining common process steps which negatively affect the solderability of ball-grid array pads, such as flip-chip reflow and molding compound applications, then discuss advancements in ball-attach fluxes which help eliminate these extra process steps, or ‘prefluxing’ steps. Finally, this paper will then discuss assembly trends which have led to fluxless component attach, and will discuss materials designed for fluxless processes, such as formic acid reflow, and how these fluxless processes tie into flip-chip assembly.

Recent Advances and Trends in Advanced Packaging

In this study, advanced packaging is defined. The kinds of advanced packaging are ranked based on their interconnect density and electrical performance, and are grouped into 2-D, 2.1-D, 2.3-D, 2.5-D, and 3-D IC integration, which will be presented and discussed. Chiplet design and heterogeneous integration packaging provide alternatives to the system on chips (especially for advanced nodes) will be discussed. Different substrates, such as size, pin-count, and metal linewidth and spacing for advanced packaging, are examined. The lateral communication between chiplets, such as the silicon bridges embedded in organic build-up package substrate and fan-out epoxy molding compound, as well as flexible bridges, will be presented. Fan-in packaging, such as the six-side molded wafer-level chip-scale package (WLCSP) and its comparison with the ordinary WLCSP, are presented. Fan-out packaging, such as the chip-first with die face-up, chip-first with die face-down, and chip-last and their difference, will be provided. Low-loss dielectric materials for high-speed and high-frequency applications in advanced packaging will be presented. Flip-chip assembly by mass reflow, thermocompression bonding, and bumpless hybrid bonding will be briefly mentioned first.

Mechanical properties and microstructural evolution of solder alloys fabricated using laser-assisted bonding

The mass reflow (MR) process is widely used in electronic packaging interconnection. However, the conventional MR process can cause thermal damage to components and requires a long process time. The laser-assisted bonding (LAB) process is considered as an alternative soldering process for overcoming these limitations due to its extremely fast process time and high thermal selectivity. The LAB process causes low thermal damage; hence, it can be used to fabricate flexible and stretchable applications. This study investigates the mechanical properties, microstructural variation, and intermetallic reaction between the SAC 305 solder and Cu electrodes. The mechanical properties are investigated using shear tests, while the microstructure is analyzed using scanning electron microscopy and X-ray scans. Furthermore, the reliability of the LAB- and MR-produced SAC 305 solders is assessed using a high-temperature storage test. As a result, the intermetallic compound layer is found to be considerably thinner, and the volume of voids in the solder matrix is lower in the LAB-produced solder than that in the MR-produced solder. The mechanical properties of the LAB-produced solders are enhanced by these microstructural advantages.

Development and optimization of the laser-assisted bonding process for a flip chip package

In a fine pitch flip chip package, a laser-assisted bonding (LAB) technology has recently been developed to overcome several reliability and throughput issues in the conventional mass reflow (MR) and thermal compression bonding technology. This study investigated the LAB process for a flip chip package with a copper (Cu) pillar bump using numerical heat transfer and thermo-mechanical analysis. During the LAB process, the temperature of the silicon die was uniform across the entire surface and increased to 280 °C within a few seconds; this was high enough to melt the solder. The heat in the die was quickly conducted to the substrate through the Cu pillar bumps. Meanwhile, the substrate temperature was low and remained constant. Therefore, a stable solder interconnection was quickly achieved with minimal stress and thermal damage to the package. The substrate thickness, the number of Cu bumps, and the bonding stage temperature were found to be important factors affecting the heat transfer behavior of the package. The temperature of the die decreased when a thinner substrate, a higher number of Cu bumps, and a lower bonding stage temperature were used. If the temperature of the die was not sufficiently high, insufficient heat was transferred to the solder to melt it, resulting in incomplete solder joint formation. Thermo-mechanical analysis also showed that the LAB process produced lower warpage and thermo-mechanical strain than the conventional MR process. These results indicated that a LAB process using a selective local heating method would be beneficial in reducing thermo-mechanical stress and increasing throughput for the fine pitch flip chip packages.

Ultraminiaturized Three-Dimensional IPAC Packages With 100 μm Thick Glass Substrates for Radio Frequency Front-End Modules

This paper presents innovative compact three-dimensional integrated passive and active components (3D IPAC) packages with ultrathin glass substrates for radio frequency (RF) long-term evolution (LTE) front-end modules (FEMs). High component density was achieved through double-side integration of substrate-embedded passives for impedance matching networks and three-dimensional (3D) double-side assembly of filters onto glass substrates. Glass with 100 μm thickness formed the core of the package, while four build-up layers with 15 μm thickness each were used to embed passives and form redistribution layers (RDLs). Advanced panel-scale double-side assembly processes were developed with low-cost mass reflow. Board-level assembly was realized with paste-printed solder balls and reflow on printed circuit board (PCB) with no intermediate substrates. Electrical performance of filters with substrate-embedded impedance matching networks was characterized and compared to simulations.

Speed and Accuracy Optimization for Fan-Out Die Placement

Die placement accuracy requirements for fan-out wafer level packaging vary widely based on the process flow selected. Each process flow has attributes that define the challenges and requirements for die placement accuracy. Different fan-out process flows can require die placement to be done face-up or face-down. Alignment schemes for die placement can include global alignment, local alignment or a combination of both methods. Heat may be required for the carrier or die and placement force must be carefully controlled. Predictable placement of die prior to reconstitution is a key enabling technology for advanced fan-out products requiring fine line and space redistribution layers but it has the potential to improve yield in any of the fan-out processes. Accuracy requirements are driven by the photolithography done after reconstitution. Steppers are used with the assumption die to die spacing is repeatable within a given field area, however die spacing will inevitably be somewhat irregular due normal proces...

Rotational solder self-alignment mechanics modeling for a flip chip in the presence of a viscous fluid

Advent of 2.5/3Dimensional (2.5/3D) integration using through-silicon vias (TSVs) enables the formation of high signal bandwidth, fine pitch, and short-distance interconnections in stacked dies but the new package configuration poses technical challenges in package assembly process. To pace industry demands, a new alternative, Thermal Compression Bonding (TCB), to the conventional Flip Chip on Board (FCOB) process has been being developed for the 3D stacking. Among process materials, epoxy flux (or no-flow underfill) draws high attention again due to its technical advantages in both TCB and mass reflow process. The conventional mass reflow with epoxy flux could provide outstanding benefits to 2.5D package assembly process. The new Low Cost High Throughput Flip Chip Assembly process is one such process requiring fewer processing steps, lower cycle times, and lower cost. In this new process, underfill is dispensed prior to chip placement, and solder reflow and underfill cure occur simultaneously. This reduces the cycle time required for manufacture; however, the presence of a viscous underfill affects the chips' capacity for self-alignment. In a companion study, self-alignment for a flip chip undergoing rectilinear translation was analyzed. This paper applies an equivalent analysis process to a flip chip undergoing rotation in the presence of a viscous underfill. Details of the modeling process are presented along with parametric studies and contrasted against pure translation case. Conditions and process parameters which are more conducive to realignment and those hampering realignment are presented.

CPI Parametric Investigation of UBM-Al Interface for Cu Pillar Flip-Chip Application

Under bump metallization (UBM)–Al delamination is a high-value chip-package interaction reliability problem in flip-chip Cu pillar packaging. We devised a test vehicle for quick reliability assessment. We demonstrate that preclean is a critical step to ensure reliable UBM-Al adhesion and achieve bump shear strength >12 g/mil2 for 15- $\mu \text{m}$ polymer opening. Key parameters affecting bump shear strength, such as UBM critical dimension (CD), polyimide (PI) CD, SiN CD, and PI thickness, were reviewed from both simulation and experimental standpoints and good agreement was achieved between the two. Based on the observed failure mode, a 1-D model was also proposed to correctly predict the experimental trend. Optimum design rules for Cu pillar were outlined. Chip-substrate assembly was demonstrated on 80- $\mu \text{m}$ bump pitch with staggered bump configuration using mass reflow. Progressive thermal cycling was performed to evaluate package performance. Failure mode was found to be solder crack, verifying the improvement in UBM-Al adhesion.

TCB Process Options to Achieve the Lowest Cost

Thermocompression bonding enables the next generation fine pitch, 2.5D and 3D assembly technologies using Cu pillar interconnects, but to achieve widespread adoption the cost of TCB must become competitive with mass reflow processes. Stacked memory products drive the commercial volume today using TSV structures and TCB since it is the only technology able to achieve the desired stacked die construction and improved performance, but reducing the cost of assembly is still a key goal for those suppliers. In non-memory applications the choice of TCB can be driven by the bump pitch of the device or the requirement to control warpage of large die on laminate during assembly, but cost is still a key factor in the decision. The cost of a TCB process is largely driven by the UPH of the process where cost calculations are based on the cost per unit of material produced. As the UPH of a TCB process approaches 1400, the differential cost of the TCB process as compared to mass reflow becomes negligible. In the choice of a potential TCB process, special attention must be given to those processes that enable the highest UPH and the lowest cost. Processes used for TCB today can be grouped into two main categories; processes that use a pre-applied underfill and those that apply underfill after the bonding process. Underfills applied prior to bonding can be in the form of a non-conductive paste (TC-NCP) applied to a substrate or a non-conductive film applied to the wafer before dicing (TC-NCF). If underfill is applied after the bonding process, it is done as a Capillary Underfill (TC-CUF). In this case the die is underfilled in much the same way as in standard flip chip processes, but the process can be more challenging because of flux cleaning requirements and the narrower bondline of a typical TCB device. UPH is primarily driven by two factors; the range of temperature required by the bond head and the temperature ramp rate of the bond head. A process with less temperature range will have higher UPH and bond heads designed for the fastest cooling and heating rates will provide higher UPH processes. Two process options have been developed to minimize the temperature excursions required by the bond head and maximize the throughput. TC- NCF processes targeting stacked die and interposer products have been developed with throughputs approaching 2000 UPH. Substrate flux TC-CUF processes targeting assembly on laminate have been developed with throughputs that approach 2500 UPH. These two processes are expected to dominate TCB volume production moving forward as TCB enters mainstream production. This presentation will describe the methods used to achieve high throughput for both processes and the product application space appropriate for each one.

Advancements in Flip Chip Assembly Equipment and Processes

High I/O devices such as microprocessors, applications processors and field programmable gate arrays have transitioned from wire bonding to flip chip interconnect as the I/O densities have increased above 2000. As the bump pitch shrinks the standard process flow for production flip chip processes is challenged. As the bump pitch continues to shrink the accuracy of standard flip chip bonders is not adequate for the fine pitch packages of tomorrow. The options to resolve this issue are extending the accuracy for standard flip chip bonders or moving the assembly of these packages to the inherently more accurate thermo-compression bonders. This paper will discuss the pros and cons of each approach along with showing data which indicates what accuracies are actually required. Although substrate manufacturers have developed low CTE designs which mitigate the warpage caused by the mismatch between the Si die and the substrate as the assembled package travels through the reflow oven, warpage at finer pitches is becoming more and more difficult to control in flip chip processes. Thermocompression (TC) bonding is seen as the next-generation packaging technology that will resolve this issue through local reflow of the solder and elimination of the reflow oven. Despite the tremendous technical and quality advantages of TC bonding, adoption has been limited by the relatively low throughput of the first generation thermocompression bonders. In this paper we describe bonding results obtained with an innovative flip chip bonding method to optimize the process to dramatically improve the throughput by applying flux directly to the substrate rather than dipping the pillars in a bath. A study of this process and comparison of various methods of accomplishing it along with their related costs are discussed in the paper. A second large productivity improvement that is promising by eliminating the need for cooling the die before transferring die that has pre-applied underfill film laminated to it is also studied with productivity models developed. Finally a unique equipment concept for managing the transition from mass reflow to thermo-compression bonding will be presented.

Cost Analysis of Flip Chip Assembly Processes: Mass Reflow with Capillary Underfill and Thermocompression Bonding with Nonconductive Paste

Many factors affect the selection of the assembly and interconnect processes used to package a die. For example, the size of the die and package, the type of substrate, and the number of IOs all must be considered. In this paper, two processes are compared: a flip chip process using mass reflow with capillary underfill versus a flip chip thermocompression bonding process using nonconductive paste. Activity based cost modeling is used for the analysis. Both of the process flows are presented in detail, then multiple cost comparisons are presented. Examples of the variables that will change are package size, material cost, and equipment cost. In most cases, the bonding and material portions of the process flows are focused on rather than the entire assembly and substrate processes—this allows for a better analysis of particular details. Conclusions are drawn about which design scenarios are suitable for each process flow. Key cost drivers that may affect future cost comparisons as the technologies advance are also indicated.

Design of Filled One Step Chip Attach Materials (OSCA) for Conventional Mass Reflow Processing: Rheology Considerations for Jet Dispensing and Die Placement

One step chip attach materials (OSCA) are dispensable polymeric materials for flip chip assembly, which are designed to flux metallic interconnections and subsequently turn into an underfill upon curing. OSCA materials enable a drastic simplification of the assembly process by combining the reflow, flux residue cleaning and capillary underfilling steps used in traditional die attach processing into a single step. A key challenge when designing filled OSCA materials for conventional mass reflow processing (OSCA-R) is to ensure that the materials have a process-friendly rheological design allowing seamless integration with jet dispensing equipment and allowing for accurate die placement. This paper presents research results and design concepts for OSCA-R materials focused on understanding the impact of filler loading, size, type and surface chemistry on rheology and the relationships with jet dispensing performance, die placement and reliability performance for test vehicles constructed with silicon and organic substrates.

Challenges of Scalable 2.5D IC Assembly

Driven by key metrics, including higher computing performance, lower power consumption, smaller form factor, increased bandwidth, and reduced latency (interconnect delay), the semiconductor interconnect technology is transitioning to 2.5D and gaining acceptance in the industry, as an increasing number of products are beginning to enter volume manufacturing. To transition from today's low volumes to high volume manufacturing (HVM), the concerns of warpage control, thermal dissipation, cost (yield and throughput), and overall technology scalability for future generations need to be addressed rapidly. The solutions in these relatively new packaging technologies encompass design/layout, material, process, and integration choices. With these concerns as a backdrop, our article will discuss our approach to optimizing 2.5D assembly for HVM. This article starts with a review of our test vehicle and our overall choices of substrate, interposer, and die dimensions. Three different 2.5D assembly approaches that have been investigated for warpage control, ease of process, and impact on yield and reliability will be discussed in detail. It is our finding that for achieving high yield and reliability, in the design stage of the system detailed considerations must be given to not only the electrical performance and signal integrity but also the thermal and mechanical behavior of the system in operation as well as the entire process history. This article reports our results from critical areas including temporary bonding, thermocompression bonding, mass reflow, thin wafer/die handling, flux, underfill, and molding. This article also presents our understanding of the underlying principles governing the technology bottlenecks in advanced packaging and the three flows will be compared with an assessment of their advantages and disadvantages. In the last portion of this article, recommendations are made for an optimized assembly process flow.

Design of Filled One Step Chip Attach Materials (OSCA) for Conventional Mass Reflow Processing: Curing Kinetics and Solder Reflow Aspects

One step chip attach materials (OSCA) are dispensable polymeric materials for flip chip assembly, which are designed to flux metallic interconnections and subsequently turn into an underfill upon curing. OSCA materials enable a drastic simplification of the assembly process by combining the reflow, flux residue cleaning and capillary underfilling steps used in traditional die attach processing into a single step. A key challenge when designing OSCA materials for conventional mass reflow processing (identified as OSCA-R) is timing the cure kinetics with the fluxing and soldering sequences during reflow processing. OSCA-R materials must also have a process-friendly rheological design that integrates seamlessly with standard dispensing equipment and enables the filler loading levels required for customized thermal conductivities. The consideration of the interactions between the filler particles and the organic portion of OSCA materials is critical for first achieving fluxing and interconnection during reflow and second curing the material to develop target thermo mechanical properties for reliability such as Tg, TC, CTE modulus and adhesion after reflow. This paper presents research focused on understanding the impact of filler loading, size, type and surface chemistry on curing, fluxing and interconnection kinetics during reflow processing measured by thermal and rheological methods. Preliminary results indicate the presence of chemical interactions between the filler and organic formulations, as well as complex physical interactions which need to be considered in the design of OSCA-R materials for a device assembly using conventional mass reflow processing.

Assembly and Scaling Challenges for 2.5D IC

2.5D technology is gaining acceptance in the industry and an increasing number of products are beginning to enter volume manufacturing. As with all interconnect technologies, the key metrics driving the transition include higher computing performance, lower power consumption, smaller form factor, increased bandwidth and reduced latency (interconnect delay). In order to transition from today's low volumes to High Volume Manufacturing (HVM), the concerns of warpage control, thermal dissipation, cost (yield and throughput) and overall technology scalability for future generations need to be addressed rapidly. The solutions in these relatively new packaging technologies encompass design/layout, material, process and integration choices. With these concerns as a backdrop, our paper will discuss our approach to optimizing 2.5D assembly for HVM. We will begin with a review of our test vehicle and our overall choices of substrate, interposer and die dimensions. Three different 2.5D assembly approaches that have been investigated at Invensas for warpage control, ease of process, and impact on yield and reliability will be discussed in detail. We will present our results from critical areas including temporary bonding, thermo-compression bonding, mass reflow, thin wafer/die handling, flux, underfill and molding. This paper will present our understanding of the underlying principles governing the technology bottlenecks in advanced packaging and the three flows will be compared with an assessment of their advantages and disadvantages. In addition, we will also provide the results of our cost modeling work. We will finish by making recommendations for an optimized assembly process flow.

High Productivity Thermo-Compression Flip Chip Bonding

Advancements in electronic packaging performance and cost have historically been driven by higher integration primarily provided by fab shrinks that has followed the well-known Moore's law. However, due to the tremendous and continuously increasing cost of building new fabs, the performance/cost improvements achieved via node shrinks are negated. This leaves packaging innovation as the vehicle to achieve future cost-performance improvements. This has initiated a More-than-Moore idea that has led to vigorous R&D in packaging. Advanced packages which employ ultra-fine pitch flip chip technology for chip-to-substrate, chip-to-chip, or chip-to-interposer for the first level interconnect have been developed as an answer to obtaining higher performance. However, the costs are too high as compared to traditional wire bonding. The status today is that the fundamental technical hurdles of manufacturing the new advanced packages have been solved, but cost reduction and yield improvements have to be addressed for large-scale adoption into high volume manufacturing. In traditional flip chip assembly silicon chips are tacked onto a substrate and then the solder joints are melted and mass reflowed in an oven. This mass reflow technique is troublesome as the pitch of the solder bumps become finer. This is due to the large differences in the thermal expansion coefficient of the die and the substrate, which creates stress at the solder joints and warpage of the package when the die and substrate are heated and cooled together. To mitigate and resolve this issue, thermo-compression bonders have been developed which locally reflow the solder without subjecting the entire substrate to the heating and cooling cycle. This requires that the bondhead undergo heating past the melting point of solder and then cooling down to a low enough temperature to pick the next die from the wafer that is mounted to tape. Machines in the market today can accomplish this temperature cycle in 7 to 15 seconds. This is substantially slower than the standard flip chip process which leads to high cost and is delaying the introduction of these new packages. This paper shows a flip chip bonder with a new heating and cooling concept that will radically improve the productivity of thermo-compression bonding. Data and productivity cycles from this new bond head with heating rates of over 200°C/sec and cooling of faster than 100°C/sec are revealed. Experimental results are shown of exceptional temperature accuracy across the die of 5°C throughout the cycle and better than 3°C at the final heating stage. The high speed thermo-compression bonds are analyzed and the efficacy of the new concept is proven. Excellent temperature uniformity while heating rapidly is an absolute necessity for enabling good solder joints in a fast process. Without good temperature uniformity, additional dwell times need to be incorporated to allow heat to flow to all of the joints, negating any benefits from rapid heating. Whereas the current state-of-that-art is often to program temperature in steps, this bonder can be commanded and accurately follows more complex temperature profiles with great accuracy. Examples of how this profiling can be used to enhance the uniformity and integrity of the joints with non-conductive pastes, film, and without underfill along with the associated productivity improvements will be shown. Tests that show portability across platforms that will lead to set up time and yield improvements and are identified and quantified. Additionally new ideas for materials and equipment development to further enhance productivity and yield are explored.

Fine pitch Copper Pillar interconnection with C4 (Mass Reflow) Processing

Flip chip interconnection design and process capability has been extended with the use of copper pillar, specially for finer pitches, beyond what was possible with area array and standard C4 reflow and solder bumps. Many trends in device packaging are fueling this trend, specially the needs for thin packaging, increased function integration, challenging thermal, mechanical and physical specifications. In terms of processing, devices using Cu Pillar are most commonly assembled using thermo-compression bonding due to sizable challenges in extending the conventional mass reflow solution, typical for solder bumps. TC is specially recommended for handling very thin die in sparse or peripheral bump layouts, which are a predominant share of all devices converting to Cu pillar, where a bonding head is used to both hold the die flat and in true alignment with the substrate while supplying the thermal energy necessary to complete the interconnection. This process most often also requires the use of a non-conductive paste/film for stress absorption in recognition to the fact that underfill materials have great limitations in filling the underdie cavity. In this paper, we explore avenues to extend the current processing envelope for Cu pillar bumped devices using C4 reflow. Benefits of this approach are shown as decreased cost of ownership for materials, lower fixed costs due to using mostly depreciated equipment. Yet, challenges in defining new design rules, reformulating materials and extending process flows are among some of the barriers for further adoption of this solution in production

One Step Chip Attach Materials (OSCA) for Conventional Mass Reflow Processing

One step chip attach (OSCA) materials are dispensable polymeric materials for flip chip assembly, which are designed to flux metallic interconnections and subsequently turn into an underfill upon curing. OSCA materials enable a drastic simplification of the assembly process by combining the reflow (fluxing/soldering), defluxing and capillary underfilling steps used in traditional processing into a single step. One key challenge for the design of OSCA materials is timing the cure kinetics with fluxing activity and solder reflow during processing. A second key challenge is to factor a process-friendly rheological design into the formulation. The OSCA material rheology must allow for high filler loading levels, seamless integration with standard dispensing equipment, flow control during and after dispense (avoid keep out zones), flow during die placement (elimination of voids), after placement (fillet formation) and during reflow. The final key requirements for a functional device are defect-free interconnections combined with optimal thermo-mechanical and water resistant properties of the final underfill to guarantee the long-term reliability of the assembly in various environmental conditions. This paper presents the properties of materials designed by Kester for use in mass reflow processing (OSCA-R). The rheological design principles behind a seamless integration into customer-friendly processes will be presented In addition results illustrating the timing of cure kinetics with fluxing and soldering events during processing will be discussed. Preliminary device reliability results will also be presented for several types of test vehicles including; Si-Si and Si-FR4.