Margin Propagation Research Articles

Multiplierless MP-Kernel Machine for Energy-Efficient Edge Devices

We present a novel framework for designing multiplierless kernel machines that can be used on resource-constrained platforms such as intelligent edge devices. The framework uses a piecewise linear (PWL) approximation based on a margin propagation (MP) technique and uses only addition/subtraction, shift, comparison, and register underflow/overflow operations. We propose a hardware-friendly MP-based inference and online training algorithm that has been optimized for a field-programmable gate array (FPGA) platform. Our FPGA implementation eliminates the need for digital signal processor (DSP) units and reduces the number of Look-Up Tables (LUTs). By reusing the same hardware for inference and training, we show that the platform can overcome classification errors and local minima artifacts that result from MP approximation. The implementation of this proposed multiplierless MP-kernel machine on FPGA results in an estimated energy consumption of 13.4 pJ and power consumption of 107 mW with ~9 k LUTs and Flip Flops (FFs) each for a 256 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 32 sized kernel making it superior in terms of power, performance, and area compared with other comparable implementations.

Synthesis of Bias-Scalable CMOS Analog Computational Circuits Using Margin Propagation

Approximation techniques are useful for implementing pattern recognizers, communication decoders and sensory processing algorithms where computational precision is not critical to achieve the desired system level performance. In our previous work, we had proposed margin propagation (MP) as an efficient piecewise linear (PWL) approximation technique to a log-sum-exp function and had demonstrated its advantages for implementing probabilistic decoders. In this paper, we present a systematic and a generalized approach for synthesizing analog piecewise-linear (PWL) computing circuits using the MP principle. MP circuits use only addition, subtraction and threshold operations and hence can be implemented using universal conservation principles like the Kirchoff's current law. Thus, unlike the conventional translinear CMOS current-mode circuits, the operation of the MP circuits are functionally similar in weak, moderate, and strong inversion regimes of the MOS transistor making the design approach bias-scalable. This paper presents measured results from MP circuits prototyped in a 0.5 μm standard CMOS process verifying the bias-scalable property. As an example, we apply the synthesis approach towards designing linear classifiers and we verify its performance using measured results.

A 100 pJ/bit, (32,8) CMOS Analog Low-Density Parity-Check Decoder Based on Margin Propagation

One of the key factors underlying the popularity of low-density parity-check (LDPC) code is its iterative decoding algorithm which is amenable to efficient analog and digital implementation. However, different applications of LDPC codes (e.g. wireless sensor networks) impose different sets of constraints which include speed, bit error rates (BER) and energy efficiency. Our previous work reported an algorithmic framework for designing margin propagation (MP) based LDPC decoders where the BER performance can be traded off with its energy efficiency. In this paper we present an analog current-mode implementation of an MP-based (32,8) LDPC decoder. The implementation uses only addition, subtraction and threshold operations and hence is independent of transistor biasing. Measured results from prototypes fabricated in a 0.5 μm CMOS process verify the functionality of a (32,8) LDPC decoder and demonstrate the trade-off capability which is realized by adapting a system hyper-parameter. When configured as a min-sum LDPC decoder, the proposed implementation demonstrates superior BER performance compared to the state-of-the-art analog min-sum decoder at SNR greater than 3.5 dB. We show that an optimal configuration of the same MP-based decoder can also deliver up to 3 dB improvement in BER compared to the benchmark min-sum LDPC decoder.

Analog Iterative LDPC Decoder Based on Margin Propagation

A margin propagation (MP) algorithm that can be used for implementing analog decoders for low-density parity check (LDPC) codes is presented. Unlike conventional sum-product analog decoders that rely on translinear operation of transistors, MP decoders use addition, subtraction and threshold operations, and therefore can be mapped onto different analog circuit topologies (current-mode, charge-mode, or nonelectronic circuits). This brief describes salient properties of the MP decoding algorithm and compares its performance to the sum-product and the min-sum (MS) decoding algorithms. Simulation results demonstrate that MP based LDPC decoders achieve nearly an identical bit error rate performance as their sum-product counterparts and achieve superior performance as compared to the MS decoding algorithm. Results presented in this brief also demonstrate that, when messages in LDPC decoding are corrupted by additive noise, the MP decoding algorithm delivers superior performance compared to its sum-product and MS counterparts.