Many-core Chips Research Articles

Modeling and Analysis of Thermal Covert Channel Attacks in Many-core Systems

In a many-core chip, thermal flux and thermal correlation among the cores can be explored to create a thermal covert channel (TCC). In this paper, we provide an analytical model to quickly determine the key TCC performance metrics, in terms of bit error rate (BER), signal to noise ratio (SNR), and channel capacity, without going through lengthy computer simulation and/or physical experiments that are normally needed in current TCC performance studies. According to our model, the TCC’s BER is proportional to the square root of the transmission frequency, which can be explored quantitatively to boost the TCC’s transmission efficiency by letting the TCC’s thermal signal be transmitted at a higher frequency. In addition, our proposed model also links the jamming noise and application of Dynamic Voltage Frequency Scaling (DVFS) to TCC’s BER performance, a feature that can be explored to design/optimize the countermeasures against the TCC attacks. The TCC performance predicted by the proposed theoretical model is found in a good agreement with that obtained from computer simulations, with an average error lower than 7%.

An efficient multi-level cache system for geometrically interconnected many-core chip multiprocessor

<p><span lang="EN-US">Many-core chip multiprocessor offers high parallel processing power for big data analytics; however, they require efficient multi-level cache and interconnection to achieve high system throughput. Using on-chip first level L1 and second level L2 per core fast private caches is expensive for large number of cores. In this paper, for moderate number of cores from 16 to 64, we present a cost and performance efficient multi-level cache system with per core L1 and last level shared bus cache on each bus line of a cost-efficient geometrically bus-based interconnection. In our approach, we extracted cache hit and miss concurrencies and applied concurrent average memory access time to more accurately determine the cache system performance. We conducted least recently used cache policy-based simulation for cache system with L1, with L1/L2, and with L1/shared bus cache. Our simulation results show that an average system throughput improvement of 2.5x can be achieved by using system with L1/shared bus cache system compared to using only first level L1 or L1/L2. Further, we show that the throughput degradation for the proposed cache system is only within 5% for a single bus fault, suggesting a good bus fault tolerance.</span></p>

Optical Interconnects Finally Seeing the Light in Silicon Photonics: Past the Hype.

Electrical interconnects are becoming a bottleneck in the way towards meeting future performance requirements of integrated circuits. Moore’s law, which observes the doubling of the number of transistors in integrated circuits every couple of years, can no longer be maintained due to reaching a physical barrier for scaling down the transistor’s size lower than 5 nm. Heading towards multi-core and many-core chips, to mitigate such a barrier and maintain Moore’s law in the future, is the solution being pursued today. However, such distributed nature requires a large interconnect network that is found to consume more than 80% of the microprocessor power. Optical interconnects represent one of the viable future alternatives that can resolve many of the challenges faced by electrical interconnects. However, reaching a maturity level in optical interconnects that would allow for the transition from electrical to optical interconnects for intra-chip and inter-chip communication is still facing several challenges. A review study is required to compare the recent developments in the optical interconnects with the performance requirements needed to reach the required maturity level for the transition to happen. This review paper dissects the optical interconnect system into its components and explains the foundational concepts behind the various passive and active components along with the performance metrics. The performance of different types of on-chip lasers, grating and edge couplers, modulators, and photodetectors are compared. The potential of a slot waveguide is investigated as a new foundation since it allows for guiding and confining light into low index regions of a few tens of nanometers in cross-section. Additionally, it can be tuned to optimize transmissions over 90° bends. Hence, high-density opto-electronic integrated circuits with optical interconnects reaching the dimensions of their electrical counterparts are becoming a possibility. The latest complete optical interconnect systems realized so far are reviewed as well.

Power density aware application mapping in mesh-based network-on-chip architecture: An evolutionary multi-objective approach

In the era of many-core chips, the problem of power density is a serious challenge. This is particularly important in Network-on-Chip (NoC)-based systems, where application mapping determines the resulting power patterns and the workload distribution across the entire chip. Despite this fact, the majority of mapping algorithms focus on performance, and the resulting power patterns are largely ignored. This work investigates this problem. Three different power pattern metrics with different scopes are defined, namely, power peak, power range, and regional power density. The results of using them as mapping objectives together with communication cost using a multi-objective evolutionary mapping approach are investigated. Results show that employing power patterns results-in Pareto fronts with different power patterns and features. Results are analysed and discussed. Moreover, a case study of thermal analysis of the resulting power patterns is performed. Results show that using communication cost only results-in large hotspots which translates into higher peak and range of chip temperatures. The proposed mapping objectives are shown to significantly improve thermal balancing (up to 55%) and peak temperature (up to 7.77%). These results indicate the importance of considering power patterns in the design of NoC-based many-core systems and their direct impact on the reliability and performance of such systems.

TAMA

Nowadays, static power consumption in chip multiprocessor (CMP) is the most crucial concern of chip designers. Power-gating is an effective approach to mitigate static power consumption particularly in low utilization. Network-on-Chip (NoC) as the backbone of multi- and many-core chips has no exception. Previous state-of-the-art techniques in power-gating desire to decrease static power consumption alongside the lack of diminution in performance of NoC. However, maintaining the performance and utilization of the power-gating approach has not yet been addressed very well. In this article, we propose TAMA (Turn-Aware Mapping & Architecture) as an effective method to boost the performance of the TooT method that was only powering on a router during turning pass or packet injection. In other words, in the TooT method, straight and eject packets pass the router via a bypass route without powering on the router. By employing meta-heuristic approaches (Genetic and Ant Colony algorithms), we develop a specific application mapping that attempts to decrease the number of turns through interconnection networks. Accordingly, the average latency of packet transmission decreases due to fewer turns. Also, by powering on turn routers in advance with lightweight hardware, the latency of sending packets diminishes. The experimental results demonstrate that our proposed approach, i.e., TAMA achieves more than 13% reduction in packet latency of NoC in comparison with TooT. Besides the packet latency, the power consumption of TAMA is reduced by about 87% compared to the traditional approach.

An enhanced planned obsolescence attack by aging networks-on-chip

Despite of a controversial practice, having the key components of a product undergo accelerated aging has been a very effective approach for planned obsolescence. All previous studies on planned obsolescence merely focused on the aging process itself; however, if a malfunctioned product due to aging is still under its warranty, the manufacturer suffers from financial losses in the form of customer refund and/or product repair. In this paper, we reveal an enhanced planned obsolescence attack that takes the warranty issue into consideration. More specifically, aging of an NoC-based many-core chip is set to be slow before the warranty expires, and its aging process gets accelerated afterwards. Such controlled aging is achieved by manipulating the routing algorithm that influences the lifetime distribution of the NoC nodes. The routing-induced aging process is also integrated with a profit model to evaluate the profit gained from chip aging. Experimental results show that, with the proposed planned obsolescence attack and the profit model, the manufacturer can increase its profit margin by 15.54%, 25.69%, and 53.36%, respectively, compared to devices under a scheme without any attack, a scheme that aggressively accelerates chip aging, and a scheme that employs a measure to mitigate chip aging. Overall speaking, the proposed attack can give the manufacturer a clear advantage over customer who can barely notice the existence of such business practices, and consequently, some advanced countermeasure schemes need to be developed to balance the interests of the two parties.

HeM3D

Heterogeneous manycore architectures are the key to efficiently execute compute- and data-intensive applications. Through-silicon-via (TSV)-based 3D manycore system is a promising solution in this direction as it enables the integration of disparate computing cores on a single system. Recent industry trends show the viability of 3D integration in real products (e.g., Intel Lakefield SoC Architecture, the AMD Radeon R9 Fury X graphics card, and Xilinx Virtex-7 2000T/H580T, etc.). However, the achievable performance of conventional TSV-based 3D systems is ultimately bottlenecked by the horizontal wires (wires in each planar die). Moreover, current TSV 3D architectures suffer from thermal limitations. Hence, TSV-based architectures do not realize the full potential of 3D integration. Monolithic 3D (M3D) integration, a breakthrough technology to achieve “More Moore and More Than Moore,” opens up the possibility of designing cores and associated network routers using multiple layers by utilizing monolithic inter-tier vias (MIVs) and hence, reducing the effective wire length. Compared to TSV-based 3D integrated circuits (ICs), M3D offers the “true” benefits of vertical dimension for system integration: the size of an MIV used in M3D is over 100 × smaller than a TSV. This dramatic reduction in via size and the resulting increase in density opens up numerous opportunities for design optimizations in 3D manycore systems: designers can use up to millions of MIVs for ultra-fine-grained 3D optimization, where individual cores and routers can be spread across multiple tiers for extreme power and performance optimization. In this work, we demonstrate how M3D-enabled vertical core and uncore elements offer significant performance and thermal improvements in manycore heterogeneous architectures compared to its TSV-based counterpart. To overcome the difficult optimization challenges due to the large design space and complex interactions among the heterogeneous components (CPU, GPU, Last Level Cache, etc.) in a M3D-based manycore chip, we leverage novel design-space exploration algorithms to trade off different objectives. The proposed M3D-enabled heterogeneous architecture, called HeM3D , outperforms its state-of-the-art TSV-equivalent counterpart by up to 18.3% in execution time while being up to 19°C cooler.

Power Management of Monolithic 3D Manycore Chips with Inter-tier Process Variations

Voltage/frequency island (VFI)-based power management is a popular methodology for designing energy-efficient manycore architectures without incurring significant performance overhead. However, monolithic 3D (M3D) integration has emerged as an enabling technology to design high-performance and energy-efficient circuits and systems. The smaller dimension of vertical monolithic inter-tier vias (MIVs) lowers effective wirelength and allows high integration density. However, sequential fabrication of M3D layers introduces inter-tier process variations that affect the performance of transistors and interconnects in different layers. Therefore, VFI-based power management in M3D manycore systems requires the consideration of inter-tier process variation effects. In this work, we present the design of an imitation learning (IL)-enabled VFI-based power-management strategy that considers the inter-tier process-variation effects in M3D manycore chips. We demonstrate that the IL-based power-management strategy can be fine-tuned based on the M3D characteristics. Our policy generates suitable V/F levels based on the computation and communication characteristics of the system for both process-oblivious and process-aware configurations. We show that the proposed process-variation-aware IL-based VFI implementation for M3D manycore chips lowers the overall energy-delay-product (EDP) by up to 16.2% on average compared to an ideal M3D system with no M3D process variations.

A Brief Overview of On-Chip Voltage Regulation in High-Performance and High-Density Integrated Circuits

With the increase of density and complexity of high performance integrated circuits and systems, including many-core chips and system-on-chip (SoC), it is becoming difficult to meet the power delivery and regulation requirements with off-chip regulators. The off-chip regulators become a less attractive choice because of the higher overheads and complexity imposed by the additional wires, pins, and pads. The increased $I^{2}R$ loss makes it challenging to maintain the integrity of different voltage domains under a lower supply voltage environment in the smaller technology nodes. Fully integrated on-chip voltage regulators have proven to be an effective solution to mitigate power delivery and integrity issues. Recently, there has been a surge of interest among the academic and industrial research communities to explore and design different types of on-chip voltage regulators. This survey presents a brief overview of the on-chip power delivery system and the classification and working principles of on-chip voltage regulators. The main focus of this review paper is to provide a comprehensive study of two of the most promising on-chip voltage regulators – (i) the low-drop-out (LDO) regulator and (ii) the switched-capacitor (SC) regulator. This article elaborates on the design specifications, optimization techniques, advantages, and limitations of LDO and SC type on-chip voltage regulators.

NeuronLink: An Efficient Chip-to-Chip Interconnect for Large-Scale Neural Network Accelerators

Large-scale neural network (NN) accelerators typically consist of several processing nodes, which could be implemented as a multi- or many-core chip and organized via a network-on-chip (NoC) to handle the heavy neuron-to-neuron traffic. Multiple NoC-based NN chips are connected through chip-to-chip interconnection networks to further boost the overall neural acceleration capability. Huge amounts of multicast-based traffic travel on-chip or cross chips, making the interconnection network design more challenging and become the bottleneck of the NN system performance and energy. In this article, we propose coupling intrachip and interchip communication techniques, called NeuronLink, for NN accelerators. Regarding the intrachip communication, we propose scoring crossbar arbitration, arbitration interception, and route computation parallelization techniques for virtual-channel routing, leading to a high-throughput NoC with a lower hardware cost for multicast-based traffic. Regarding the interchip communication, we propose a lightweight and NoC-aware chip-to-chip interconnection scheme, enabling efficient interconnection for NoC-based NN chips. In addition, we evaluate the proposed techniques on a four connected NoC-based deep neural network (DNN) chips with four field-programmable gate arrays (FPGAs). The experimental results show that the proposed interconnection network can efficiently manage the data traffic inside DNNs with high-throughput and low-overhead against state-of-the-art interconnects.

A Table-Free Approximate Q-Learning-Based Thermal-Aware Adaptive Routing for Optical NoCs

Optical networks-on-chips (NoCs) based on silicon photonics have been proposed as an emerging communication architecture for many-core chip multiprocessors. However, the thermal sensitivity of silicon photonics is one of the major challenges. $Q$ -learning-based adaptive routing has been proposed in related work to mitigate the thermal issue. However, table overhead of the traditional table-based $Q$ -routing would scale up quickly with the increase of network size. In this article, we propose a table-free approximate $Q$ -learning-based thermal-aware adaptive routing to find optimal low-loss paths in the presence of on-chip temperature variations. The simulation results show that the proposed table-free approximate $Q$ -learning-based adaptive routing can converge faster and it can achieve similar optimization effect as compared to the best optimization effect of the traditional table-based $Q$ -routing. The performance gap between the proposed approximation method and the traditional table-based $Q$ -routing expands when the network size increases.

A Survey of Silicon Photonics for Energy-Efficient Manycore Computing

Silicon photonics is an emerging paradigm for designing energy -efficient and high-performance communication backbone for manycore chips. This article presents a survey about designing photonic on-chip infrastructure.

On hardware-trojan-assisted power budgeting system attack targeting many core systems

Abstract In a modern many-core chip, as all the cores are constantly competing for their shares of power out of the maximum power available to the chip, a sound power budgeting scheme is needed to efficiently allocate power to achieve the highest possible overall system performance. When a core is poised to run some applications, it has to request its power budget by sending a series of data packets, routed typically through an on-chip communication network infrastructure, to a specific core designated as the global manager that makes its power allocation decision based on all the budget requests it receives and its assessment of each core’s potential contribution to the overall system performance. This power budgeting scheme is shown, in this paper, to be highly vulnerable to stealthy false-data attacks, which can cause catastrophic denial of service (DoS) effects. Essentially, when a power budget request packet is routed through a Trojan-infected network-on-chip node, such as a router, the power budget request can be secretly modified by the Trojan. The global manager then tends to make really bad power budget allocation decisions with all the tampered power requests it received. That is, legitimate applications will be victimized with lower power budgets than what they initially asked for, and thus, could suffer serious performance degradation; malicious applications, on the other hand, may be entitled to high power budgets and thus see performance boost that they do not deserve. Our study has revealed that this new type of DoS attack can be initiated and sustained by a simple hardware Trojan (HT) circuit that is extremely hard to be detected due to its low silicon footprint and short activation time. The effects of this new DoS attack are simulated following a network model, and all the major parameters and factors that impact the attack effects are identified and quantified. The HTs are intelligently turned ON/OFF following a scheme based on Q-learning, we further demonstrate that the attacks can undermine the best countermeasures against power budgeting system attack as suggested in this paper, which gives rise to a need for further research in this regard.

Scalable energy-efficient parallel sorting on a fine-grained many-core processor array

Three parallel sorting applications and two list output protocols for the first phase of an external sort execute on a fine-grained many-core processor array that contains no algorithm-specific hardware acting as a co-processor with a variety of array sizes. Results are generated using a cycle-accurate model based on measured data from a fabricated many-core chip, and simulated for different processor array sizes. The data shows most energy efficient first-phase many-core sort requires over 65× lower energy than GNU C++ standard library sort performed on an Intel laptop-class processor and over 105× lower energy than a radix sort running on an Nvidia GPU. In addition, the highest first-phase throughput many-core sort is over 9.8× faster than the std::sort and over 14× faster than the radix sort. Both phases of a 10 GB external sort require 6.2× lower energy×time energy delay product than the std::sort and over 13× lower energy×time than the radix sort.

Decreasing latency considering power consumption issue in silicon interposer-based network-on-chip

Stacking technology is an approach to improve scalability of 2D network-on-chip systems. 3D stacking technology places multiple chips vertically, while silicon chips are stacked side-by-side on a silicon interposer layer in the 2.5D stacking technology. 2.5D stacking can solve many of the 3D stacking difficulties such as thermal problem. The cores in the processing element (PE) layer must have the ability to connect together. Moreover, the connection between the processing cores and the other chips is a critical issue that should be concerned. The memory chip is one of the most important chips, integrated with the many-core chip. The network-on-chip can be extended to the interposer layer to increase the usability of the interposer layer. It is essential to have an efficient topology and deadlock-free routing algorithm to handle operations effectively and decrease delay and power consumption. In this paper, a new topology called “Balanced Mesh” and a deadlock-free routing algorithm is recommended that balances fairly the connection between different Mesh-based segments of a network. Many of interposer network topologies such as ButterDonut increase the degree of intermediate routers in the interposer layer or nodes related to other chips. Many of them cannot be easily used in the PE layer to have a uniform system. The proposed topology can be simply applied to both of many-core layer and the interposer layer to decrease delay and power consumption without any change in the degree of nodes and has lesser number of links. Our proposed topology is compared with some other topologies such as concentrated Mesh(CMesh) and ButterDount. Simulation results show that our proposed topology can improve the system efficiency with lesser number of links. Using our proposed topology in both layers achieves 13% improvement in network latency compared with using Mesh in the PE layer and ButterDonut in the interposer layer. Also, it achieves 12% improvement in power consumption.

H2WNoC: A honeycomb hardware-efficient wireless network-on-chip architecture

Network-on-chips (NoCs) have emerged as communication backbones for enabling massive parallelism and high degree of integration in many-core chips. In spite of the advantages of conventional NoCs, wired multi-hop links impose limitations on NoCs performance by long delay and high power consumption especially in large systems. To alleviate these problems, different solutions such as wireless network-on-chip (WiNoC) designs have been proposed. WiNoCs benefit from long-range, high bandwidth and low power wireless links to solve problems corresponding to wired communications. Most of the WiNoC architectures have been designed based on mesh topology, while, honeycomb topology provides more energy-efficient NoC architecture with higher throughput than mesh topology, but, as we will show, a honeycomb-based WiNoC, by itself, does not reduce the amount of utilized hardware resources and delay. In this paper, we propose a hardware-efficient WiNoC with honeycomb topology, namely, H2WNoC aiming at reducing hardware resources, network cost, delay, and also energy consumption. Considering different performance parameters, cycle-accurate-based evaluations are performed for the proposed architecture; H2WNoC is compared with the traditional mesh WiNoC, as the baseline, and also with three state-of-the-art WiNoC architectures. Furthermore, design space exploration of the proposed architecture is performed. Performance evaluations indicate that H2WNoC utilizes less hardware resources, consumes less amount of energy and improves both throughput and delay, compared to the other WiNoC architectures. Moreover, the obtained results show that the proposed architecture outperforms wired NoCs either with mesh or honeycomb topology.

Thermal-Aware Task Mapping on Dynamically Reconfigurable Network-on-Chip Based Multiprocessor System-on-Chip

Dark silicon is the phenomenon that a fraction of many-core chip has to be turned off or run in a low-power state in order to maintain the safe chip temperature. System-level thermal management techniques normally map application on non-adjacent cores, while communication efficiency among these cores will be oppositely affected over conventional network-on-chip (NoC). Recently, SMART NoC architecture is proposed, enabling single-cycle multi-hop bypass channels to be built between distant cores at runtime, to reduce communication latency. However, communication efficiency of SMART NoC will be diminished by communication contention, which will in turn decrease system performance. In this paper, we first propose an Integer-Linear Programming (ILP) model to properly address communication problem, which generates the optimal solutions with the consideration of inter-processor communication. We further present a novel heuristic algorithm for task mapping in dark silicon many-core systems, called TopoMap , on top of SMART architecture, which can effectively solve communication contention problem in polynomial time. With fine-grained consideration of chip thermal reliability and inter-processor communication, presented approaches are able to control the reconfigurability of NoC communication topology in task mapping and scheduling. Thermal-safe system is guaranteed by physically decentralized active cores, and communication overhead is reduced by the minimized communication contention and maximized bypass routing. Performance evaluation on PARSEC shows the applicability and effectiveness of the proposed techniques, which achieve on average 42.5 and 32.4 percent improvement in communication and application performance, and 32.3 percent reduction in system energy consumption, compared with state-of-the-art techniques. TopoMap only introduces 1.8 percent performance difference compared to ILP model and is more scalable to large-size NoCs.

BiGNoC: Accelerating Big Data Computing with Application-Specific Photonic Network-on-Chip Architectures

In the era of big data, high performance data analytics applications are frequently executed on large-scale cluster architectures to accomplish massive data-parallel computations. Often, these applications involve iterative machine learning algorithms to extract information and make predictions from large data sets. Multicast data dissemination is one of the major performance bottlenecks for such data analytics applications in cluster computing, as terabytes of data need to be distributed frequently from a single data source to hundreds of computing nodes. To overcome this bottleneck for big data applications, we propose BiGNoC , a manycore chip platform with a novel application-specific photonic network-on-chip (PNoC) fabric. BiGNoC is designed for big data computing and exploits multicasting in photonic waveguides. For high performance data analytics applications, BiGNoC improves throughput by up to ${{9.9}}\times$ while reducing latency by up to 88 percent and energy-per-bit by up to 98 percent over two state-of-the-art PNoC architectures as well as a broadcast-optimized electrical mesh NoC architecture, and a traditional electrical mesh NoC architecture.

A Survey of System Level Power Management Schemes in the Dark-Silicon Era for Many-Core Architectures

Power consumption in Complementary Metal Oxide Semiconductor (CMOS) technology has escalated to a point that only a fractional part of many-core chips can be powered-on at a time. Fortunately, this fraction can be increased at the expense of performance through the dark-silicon solution. However, wi

Performance and Thermal Tradeoffs for Energy-Efficient Monolithic 3D Network-on-Chip

Three-dimensional (3D) integration enables the design of high-performance and energy-efficient network on chip (NoC) architectures as communication backbones for manycore chips. To exploit the benefits of the vertical dimension of 3D integration, through-silicon-via (TSV) has been predominantly used in state-of-the-art manycore chip design. However, for TSV-based systems, high power density and the resultant thermal hotspot remain major concerns from the perspectives of chip functionality and overall reliability. The power consumption and thermal profiles of 3D NoCs can be improved by incorporating a Voltage-Frequency-Island (VFI)-based power management strategy. However, due to inherent thermal constraints of a TSV-based 3D system, we are unable to fully exploit the benefits offered by the power management methodology. In this context, emergence of monolithic 3D (M3D) integration has opened up new possibility of designing ultra-low-power and high-performance circuits and systems. The smaller dimensions of the inter-layer dielectric (ILD) and monolithic inter-tier vias (MIVs) offer high-density integration, flexibility of partitioning logic blocks across multiple tiers, and significant reduction of total wire-length. In this work, we present the first-ever study of the performance-thermal tradeoffs for energy efficient monolithic 3D manycore chips. In particular, we present a comparative performance evaluation of M3D NoCs with respect to their conventional TSV-based counterparts. We demonstrate that the proposed M3D-based NoC architecture incorporating VFI-based power management achieves a maximum of 29.4% lower energy-delay-product (EDP) compared to the TSV-based designs for a large set of benchmarks. We also demonstrate that the M3D-based NoC shows up to 29.1% lower maximum temperature than the TSV-based counterpart for these benchmarks.