Mainframe Computer Research Articles

Design and Implementation of Hardware-Software Architecture Based on Hashes for SPHINCS+

Advances in quantum computing have posed a future threat to today’s cryptography. With the advent of these quantum computers, security could be compromised. Therefore, the National Institute of Standards and Technology (NIST) has issued a request for proposals to standardize algorithms for post-quantum cryptography (PQC), which is considered difficult to solve for both classical and quantum computers. Among the proposed technologies, the most popular choices are lattice-based (shortest vector problem) and hash-based approaches. Other important categories are public key cryptography (PKE) and digital signatures. Within the realm of digital signatures lies SPHINCS+. However, there are few implementations of this scheme in hardware architectures. In this article, we present a hardware-software architecture for the SPHINCS+ scheme. We utilized a free RISC-V (Reduced Instruction Set Computer) processor synthesized on a Field Programmable Gate Array (FPGA), primarily integrating two accelerator modules for Keccak-1600 and the Haraka hash function. Additionally, modifications were made to the processor to accommodate the execution of these added modules. Our implementation yielded a 15-fold increase in performance with the SHAKE-256 function and nearly 90-fold improvement when using Haraka, compared to the reference software. Moreover, it is more compact compared to related works. This implementation was realized on a Xilinx FPGA Arty S7: Spartan-7.

Virtualization and energy management optimization of high speed computer network data centers based on optical switching and network technology

With the development of cloud computing and big data technology, the scale and complexity of data centers are increasing, and the thermal energy consumption management of computer processors can effectively improve the energy efficiency of data centers and reduce operating costs. Therefore, this study discusses the application of high-speed computer network architecture based on optical switching and network technology in data center virtualization. By constructing a high-speed computer network model based on optical switching technology, virtualization technology is used to dynamically schedule and manage resources, combined with real-time monitoring system, and the energy consumption data of the processor is collected. Using the data analysis method, the energy consumption performance under different load conditions is evaluated and the optimization strategy is proposed. The experimental results show that the network architecture using optical switching technology significantly reduces the latency of data center and improves the resource utilization. In the thermal management of the processor, dynamic resource scheduling successfully reduces the energy consumption and effectively maintains the stability and performance of the system. As a result, data center virtualization solutions based on optical switching and networking technologies can significantly optimize the power management of computer processors and improve overall energy efficiency.

Portable Acceleration of CMS Computing Workflows with Coprocessors as a Service

Computing demands for large scientific experiments, such as the CMS experiment at the CERN LHC, will increase dramatically in the next decades. To complement the future performance increases of software running on central processing units (CPUs), explorations of coprocessor usage in data processing hold great potential and interest. Coprocessors are a class of computer processors that supplement CPUs, often improving the execution of certain functions due to architectural design choices. We explore the approach of Services for Optimized Network Inference on Coprocessors (SONIC) and study the deployment of this as-a-service approach in large-scale data processing. In the studies, we take a data processing workflow of the CMS experiment and run the main workflow on CPUs, while offloading several machine learning (ML) inference tasks onto either remote or local coprocessors, specifically graphics processing units (GPUs). With experiments performed at Google Cloud, the Purdue Tier-2 computing center, and combinations of the two, we demonstrate the acceleration of these ML algorithms individually on coprocessors and the corresponding throughput improvement for the entire workflow. This approach can be easily generalized to different types of coprocessors and deployed on local CPUs without decreasing the throughput performance. We emphasize that the SONIC approach enables high coprocessor usage and enables the portability to run workflows on different types of coprocessors.

Parallel implementation for real-time visual SLAM systems based on heterogeneous computing

Simultaneous localization and mapping has become rapidly developed and plays an indispensable role in intelligent vehicles. However, many state-of-the-art visual simultaneous localization and mapping (VSLAM) frameworks are very time-consuming both in front-end and back-end, especially for large-scale scenes. Nowadays, the increasingly popular use of graphics processors for general-purpose computing, and the progressively mature high-performance programming theory based on compute unified device architecture (CUDA) have given the possibility for large-scale VSLAM to solve the conflict between limited computing power and excessive computing tasks. The paper proposes a full-flow optimal parallelization scheme based on heterogeneous computing to speed up the time-consuming modules in VSLAM. Firstly, a parallel strategy for feature extraction and matching is designed to reduce the time consumption arising from multiple data transfers between devices. Secondly, a bundle adjustment method based solely on CUDA is developed. By fully optimizing memory scheduling and task allocation, a large increase in speed is achieved while maintaining accuracy. Besides, CUDA heterogeneous acceleration is fully utilized for tasks such as error computation and linear system construction in the VSLAM back-end to enhance the operation speed. Our proposed method is tested on numerous public datasets on both computer and embedded sides, respectively. A number of qualitative and quantitative experiments are performed to verify its superiority in terms of speed compared to other states-of-the-art.

Implementation of Application Specific Instruction set Processor for Approximate Computing

The performance, energy efficiency, power dissipation, and cost of the processors used in Internet of Things edge devices can be improved by introducing approximate computing. In this paper, the design and synthesis of an application-specific instruction set processor for approximate computing is proposed. Approximate computing can also be defined by using Artificial Intelligence-based technique like the Fractal theory and Inconsistent Information System. Application Specific Instruction Set Processor is a new processor design area and is used to design a new instruction set using existing processor configuration available on the EDA tool. From the results, it is observed that significant improvement is achieved in processor performance using the TIE application as compared to without the TIE application which is applied to user-designed instruction.

GPU accelerated sparse curvelet-constrained wavefield reconstruction inversion with source estimation: Application to Chevron Benchmark 2014 blind test data set

Full-waveform inversion (FWI) is a pivotal tool in seismic exploration and seismology but encounters a persistent challenge known as “cycle-skipping,” causing it to frequently converge to local minima. Wavefield reconstruction inversion (WRI) has emerged as a potential solution to mitigate the risk of cycle skipping. Researchers have provided numerical examples indicating that WRI is less prone to being ensnared in local minima caused by the absence of low-frequency component data and the absence of a well-defined initial model compared with conventional FWI. Despite its potential, the computational demands of WRI have hindered its widespread application, especially in scenarios involving ocean towed streamer seismic acquisition and unknown sources, where the augmented systems differ from source to source. In our study, we introduce a novel approach — sparse curvelet-constrained WRI with source estimation (WRI-SE-CC) — accelerated by graphics processing unit (GPU). Real-time source function estimation is achieved through the variable projection method, and noise-related artifacts are suppressed using sparse curvelet constraints. By optimizing the utilization of hundreds of computation processors within a GPU for parallel computing of matrix-vector multiplications, we present a GPU-based grouped conjugate gradient method to accelerate the computation of WRI-SE-CC. Numerical experiments demonstrate a significant 240-fold acceleration compared with the preconditioned conjugate gradient using one CPU core for computations involving multiple sources. Inversion experiments with the overthrust model demonstrate the capability of our method in mitigating local minima and suppressing noise-related artifacts. Furthermore, we validate the framework on the Chevron 2014 blind test data set, showcasing its effectiveness in addressing practical challenges in the field.

GOLD RECOVERY USING CITRUS SINENSIS PEELS AS BIOADSORBENT

The recovery of gold from electronic waste using locally available and environmentally friendly materials were investigated. Bio-adsorbent for gold recovery was prepared from Citrus sinensis peels through mechanical processing and chemical modification. Some ceramic computer processor units were leached using aqua-regia as lixiviant. Gold was recovered from the solution using the prepared bio-adsorbent and Sodium Meta Bisulphite (SMB). The recovery efficiency of the bio-adsorbent was determined and results compared to that of SMB. The adsorption of gold at different contact times was determined and the concentration of gold in solution was found using Agilent 4100 Micro Plasma Atomic Emission Spectroscopy (MP-AES). The results obtained showed that the bio-adsorbent has an adsorption capacity of 98.4% for gold and an adsorption kinetics correlation coefficient of 0.99989. This is comparable with SMB which has 95.4%. adsorption capacity and an adsorption kinetics correlation coefficient of 0.98597. The higher adsorption capacity of the bio-adsorbent is attributed to the binding sites and the chemical modification which increases the reducing properties of the functional groups present in the Citrussinensis peels.

MISO: Monitoring Inactivity of Single Older Adults at Home Using RGB-D Technology

A new application for real-time monitoring of the lack of movement in older adults’ own homes is proposed, aiming to support people’s lives and independence in their later years. A lightweight camera monitoring system, based on an RGB-D camera and a compact computer processor, was developed and piloted in community homes to observe the daily behavior of older adults. Instances of body inactivity were detected in everyday scenarios anonymously and unobtrusively. These events can be explained at a higher level, such as a loss of consciousness or physiological deterioration. The accuracy of the inactivity monitoring system is assessed, and statistics of inactivity events related to the daily behavior of older adults are provided. The results demonstrate that our method achieves high accuracy in inactivity detection across various environments and camera views. It outperforms existing state-of-the-art vision-based models in challenging conditions like dim room lighting and TV flickering. However, the proposed method does require some ambient light to function effectively.

Reconstruction of Tomographic Size Using a Filtered Back Projection Algorithm

Due to their widespread use, image processors are among the most essential computer processors. FBP technique is one of the most widely used tomographic reconstruction methods. Images from a computed tomography (CT) scanner with 512x512 pixels of raw data for parallel beam projections are the metadata to which this approach is applied. This work is divided into three parts. Several projections are created from an input test picture termed Shepp-Logan phantom in the first section, utilizing radon transformation. The picture is rebuilt from the projection of a parallel beam in the second section to minimize reconstruction time. Finally, the proposed system filters the projections using the Ram Lak filter and the Hann window in the third section to refine the picture and then recombine the projections to generate the reconstructed image. The reconstruction procedure is performed on CT images using a filtered back-projection algorithm in this article for image optimization and then projection recombination to generate the rebuilt picture. Since CT can accurately depict anatomical elements like bones and organs and may pick slides in any orientation, it is frequently used in biological applications and diagnostics. It also offers a great spatial resolution and soft tissue contrast. We develop, create, and run computer programs when we work with MATLAB. After projecting the 2D image onto a CT scanner, a very good result in reconstructing the image is received.

Reconstruction of Tomographic Size Using a Filtered Back Projection Algorithm

Due to their widespread use, image processors are among the most essential computer processors. FBP technique is one of the most widely used tomographic reconstruction methods. Images from a computed tomography (CT) scanner with 512x512 pixels of raw data for parallel beam projections are the metadata to which this approach is applied. This work is divided into three parts. Several projections are created from an input test picture termed Shepp-Logan phantom in the first section, utilizing radon transformation. The picture is rebuilt from the projection of a parallel beam in the second section to minimize reconstruction time. Finally, the proposed system filters the projections using the Ram Lak filter and the Hann window in the third section to refine the picture and then recombine the projections to generate the reconstructed image. The reconstruction procedure is performed on CT images using a filtered back-projection algorithm in this article for image optimization and then projection recombination to generate the rebuilt picture. Since CT can accurately depict anatomical elements like bones and organs and may pick slides in any orientation, it is frequently used in biological applications and diagnostics. It also offers a great spatial resolution and soft tissue contrast. We develop, create, and run computer programs when we work with MATLAB. After projecting the 2D image onto a CT scanner, a very good result in reconstructing the image is received.

Design and Implementation of Digital Down Converter for WiFi Network

This paper introduces a field-programmable gate array (FPGA)-based digital down converter (DDC) processing a sampling frequency of about 3.64 GHz to a down-converted frequency of 28.4375 MHz to match the IEEE 802.11ah Wi-Fi HaLow standard. The proposed DDC uses a polyphase mixer(PM) and a resampling filter. The PM adopts parallel coordinate rotation digital computer (CORDIC) processors and lowpass filter arrays to reduce high-speed data rates with minimum resource utilization. Again, the resampling filter employs a cascaded integrator comb (CIC) filter associated with a parallel prefixed adder (PPA) and a multi-channel systolic finite impulse response (FIR) filter implemented with canonical expression, attaining optimum hardware cost. Converting floating-point to fixed-point data types provides significant resource savings. Finally, the improved design is coded in the Xilinx Vivado synthesis tool and successfully tested on the FPGA Kintex-7 device. In contrast to other recent architectures, the proposed design substantially reduces area requirements and power utilization. The Matlab tool verifies the design to achieve an acceptable spurious-free dynamic range (SFDR) of 115 dB.

Application of regional meteorology and air quality models based on the microprocessor without interlocked piped stages (MIPS) and LoongArch CPU platforms

Abstract. The microprocessor without interlocked piped stages (MIPS) and LoongArch are reduced instruction set computing (RISC) processor architectures, which have advantages in terms of energy consumption and efficiency. There are few studies on the application of MIPS and LoongArch central processing units (CPUs) in geoscientific numerical models. In this study, the Loongson 3A4000 CPU platform with the MIPS64 architecture and the Loongson 3A6000 CPU platform with the LoongArch architecture were used to establish the runtime environment for the air quality modelling system Weather Research and Forecasting–Comprehensive Air Quality Model with extensions (WRF-CAMx) in the Beijing–Tianjin–Hebei region. The results show that the relative errors for the major species (NO2, SO2, O3, CO, PNO3, and PSO4) between the MIPS and X86 benchmark platforms are within ±0.1 %. The maximum mean absolute error (MAE) of major species ranged up to 10−2 ppbV or µg m−3, the maximum root mean square error (RMSE) ranged up to 10−1 ppbV or µg m−3, and the mean absolute percentage error (MAPE) remained within 0.5 %. The CAMx takes about 195 min on the Loongson 3A4000 CPU, 71 min on the Loongson 3A6000 CPU, and 66 min on the Intel Xeon E5-2697 v4 CPU, when simulating a 24 h case with four parallel processes using MPICH. As a result, the single-core computing capability of the Loongson 3A4000 CPU for the WRF-CAMx modelling system is about one-third of the Intel Xeon E5-2697 v4 CPU, and the one of Loongson 3A6000 CPU is slightly lower than that of Intel Xeon E5-2697 v4 CPU; but, the thermal design power (TDP) of Loongson 3A4000 is 40 W, while the TDP of Loongson 3A6000 is 38 W, only about one-fourth of that of Intel Xeon E5-2697 v4, whose TDP is 145 W. The results also verify the feasibility of cross-platform porting and the scientific usability of the ported model. This study provides a technical foundation for the porting and optimization of numerical models based on MIPS, LoongArch, or other RISC platforms.

Lightweight and Error-Tolerant Stereo Matching with a Stochastic Computing Processor

Stereo matching, utilized in diverse fields, poses a challenge to systems in resource-constrained environments due to the significant growth of computational load with image resolution. The challenge is crucial for the systems because fields utilizing stereo matching require short operational time for real-time applications and low power architecture. Stochastic computing (SC) is able to be a valuable approach to address the challenge by reducing the computational load by representing binary numbers with stochastic sequences, which are encoded as a probability value, and by leveraging the concept of mathematical probability. Also, it is possible for a system to be error-tolerant by utilizing the characteristics of stochastic computing. Therefore, in this paper, we propose an approach for lightweight and error-tolerant stereo matching with a hardware-implemented stochastic computing processor. To verify the feasibility and error tolerance of the proposed system, we implemented the proposed system and conducted experiments comparing depth maps with or without stochastic computing by calculating similarities. According to the experimental results, the proposed system indicated no significant differences in output depth maps and achieved an improvement in the depth maps from error-injected input images by an average of 58.95%. Therefore, we demonstrated that stereo matching with stochastic computing is feasible and error-tolerant.

Design and Modeling of a Terahertz Transceiver for Intra- and Inter-Chip Communications in Wireless Network-on-Chip Architectures.

This paper addresses the increasing demand for computing power and the challenges associated with adding more core units to a computer processor. It explores the utilization of System-on-Chip (SoC) technology, which integrates Terahertz (THz) wave communication capabilities for intra- and inter-chip communication, using the concept of Wireless Network-on-Chips (WNoCs). Various types of network topologies are discussed, along with the disadvantages of wired networks. We explore the idea of applying wireless connections among cores and across the chip. Additionally, we describe the WNoC architecture, the flip-chip package, and the THz antenna. Electromagnetic fields are analyzed using a full-wave simulation software, Ansys High Frequency Structure Simulator (HFSS). The simulation is conducted with dipole and zigzag antennas communicating within the chip at resonant frequencies of 446 GHz and 462.5 GHz, with transmission coefficients of around -28 dB and -33 to -41 dB, respectively. Transmission coefficient characterization, path loss analysis, a study of electric field distribution, and a basic link budget for transmission are provided. Furthermore, the feasibility of calculated transmission power is validated in cases of high insertion loss, ensuring that the achieved energy expenditure is less than 1 pJ/bit. Finally, employing a similar setup, we study intra-chip communication using the same antennas. Simulation results indicate that the zigzag antenna exhibits a higher electric field magnitude compared with the dipole antenna across the simulated chip structure. We conclude that transmission occurs through reflection from the ground plane of a printed circuit board (PCB), as evidenced by the electric field distribution.

Dual-mode optical thermometers via the thermochromic Bi3+, Eu3+ co-doped La2LiSbO6 phosphors for real-time chip temperature monitoring

In recent years, with the increasing demand for non-contact temperature measurement, it is urgent to develop a new type of phosphor with double emission centers, high sensitivity and good reliability. A series of Bi3+and Eu3+ co-doped La2LiSbO6 double emission center phosphors were successfully prepared. The response characteristics of Bi3+and Eu3+ at different temperatures in the range of 293–473k were calculated by fluorescence intensity ratio (FIR) technique. The optimal relative sensitivity Sr and absolute sensitivity Sa were 1.13 % K−1 and 1.27 % K−1, respectively. Hence, La2LiSbO6:Bi3+, Eu3+ phosphors have the capability of non-contact optical temperature measurement and are a promising material for application. The phosphor is combined with the optical fiber temperature sensor to monitor the real-time temperature of the computer central processing unit. The optical fiber temperature sensor system breaks through the limitations of traditional temperature measurement, and can be used in special environments such as small size and strong electromagnetic interference. It has become an ideal choice to replace the traditional temperature sensor.

Insight into porous fin microchannel heat sinks with improved thermo-hydraulic performance

The escalating demand for enhanced cooling systems, particularly in high-power computer processors, necessitates innovative solutions within the spatial constraints of computing environments. This paper introduces a design modification that strategically diverts a portion of the main flow toward and through the porous fin region, creating a “cross flow.” The novel approach aims to maximize heat transfer through the fins, harnessing both conduction and convection heat transfer mechanisms. The realization of these flow patterns is achieved through interdigitated blocking of the inlet and outlet reigns of the microchannel, coupled with the utilization of converging and diverging microchannel porous fins in distinct elbow and zigzag geometrical configurations. Numerical simulations using computational fluid dynamics are employed to assess the proposed microchannel heat sink's thermo-hydraulic performance. The proposed design innovation significantly enhances heat dissipation efficiency by augmenting the convection heat transfer mechanism within the porous fins, resulting in a remarkable 17% improvement in Nusselt number compared to conventional parallel microchannel heat sinks with porous fins. This study provides valuable insight into the thermal and hydraulic performance of the proposed design, offering promising prospects for addressing the escalating demand for enhanced cooling systems in high-power computing environments.

AUTOMATIC ASSEMBLY OF INTERLOCKING BUILDING CUBES BY USING VISUAL SERVOING APPROACH

Most of the robotic arms are set up for operation by the teach-and-repeat (T&R) technique, also known as coordinate-based control, using pre-recorded coordination values to generate robotic arm trajectories. This technique is inefficient because it requires teaching a robotic arm every single coordinate point to complete an operation. It is a manual, tedious and time-consuming task. Moreover, this task needs to be repeated if there are slight changes in the operation. This paper studied the visual servoing approach to replace the T&R technique in assembling different interlocking building cubes (IBC) combinations. The proposed method uses an image-based visual servo (IBVS) with a dynamic look-and-move system, and the eye-to-hand system, which requires computing the incremental joint angles of the robotic arm, a novel kinematic formula with a combination of Trigonometry formulas has been proposed in this paper. The experimental results show the feasibility of using a visual servoing approach to complete the assembly tasks without relying on the T&R technique and achieved an average success rate of 90% and an average of 40.2 seconds for task duration. Thus, this eliminates the tedious and time-consuming tasks of teaching the coordinate points to the robotic arms. Further improvement on the servo motor, camera and computer processor can be done to increase the accuracy, computation time and task duration in future.

ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation

High-performance computing (HPC) processors are nowadays integrated cyber-physical systems demanding complex and high-bandwidth closed-loop power and thermal control strategies. To efficiently satisfy real-time multi-input multi-output (MIMO) optimal power requirements, high-end processors integrate an on-die power controller system (PCS). While traditional PCSs are based on a simple microcontroller (MCU)-class core, more scalable and flexible PCS architectures are required to support advanced MIMO control algorithms for managing the ever-increasing number of cores, power states, and process, voltage, and temperature variability. This paper presents ControlPULP, an open-source, HW/SW RISC-V parallel PCS platform consisting of a single-core MCU with fast interrupt handling coupled with a scalable multi-core programmable cluster accelerator and a specialized DMA engine for the parallel acceleration of real-time power management policies. ControlPULP relies on FreeRTOS to schedule a reactive power control firmware (PCF) application layer. We demonstrate ControlPULP in a power management use-case targeting a next-generation 72-core HPC processor. We first show that the multi-core cluster accelerates the PCF, achieving 4.9x speedup compared to single-core execution, enabling more advanced power management algorithms within the control hyper-period at a shallow area overhead, about 0.1% the area of a modern HPC CPU die. We then assess the PCS and PCF by designing an FPGA-based, closed-loop emulation framework that leverages the heterogeneous SoCs paradigm, achieving DVFS tracking with a mean deviation within 3% the plant’s thermal design power (TDP) against a software-equivalent model-in-the-loop approach. Finally, we show that the proposed PCF compares favorably with an industry-grade control algorithm under computational-intensive workloads.

Extension VM: Interleaved Data Layout in Vector Memory

While vector architecture is widely employed in processors for neural networks, signal processing, and high-performance computing; however, its performance is limited by inefficient column-major memory access. The column-major access limitation originates from the unsuitable mapping of multidimensional data structures to two-dimensional vector memory spaces. In addition, the traditional data layout mapping method creates an irreconcilable conflict between row- and column-major accesses. Ideally, both row- and column-major accesses can take advantage of the bank parallelism of vector memory. To this end, we propose the Interleaved Data Layout (IDL) method in vector memory, which can distribute vector elements into different banks regardless of whether they are in the row- or column-major category, so that any vector memory access can benefit from bank parallelism. Additionally, we propose an Extension Vector Memory (EVM) architecture to achieve IDL in vector memory. EVM can support two data layout methods and vector memory access modes simultaneously. The key idea is to continuously distribute the data that needs to be accessed from the main memory to different banks during the loading period. Thus, EVM can provide a larger spatial locality level through careful programming and the extension ISA support. The experimental results showed a 1.43-fold improvement of state-of-the-art vector processors by the proposed architecture, with an area cost of only 1.73%. Furthermore, the energy consumption was reduced by 50.1%.

EVALUATION OF NERF 3D RECONSTRUCTION FOR ROCK ART DOCUMENTATION

Abstract. Digital documentation of rock art traditionally relies on a point cloud captured by a terrestrial laser scanner (TLS) or derived from an oriented image obtained using photogrammetry. In modern photogrammetry, the dense point cloud is generated using multi-view stereo (MVS) and subsequently used to generate a photorealistic 3D model. A recent method to reconstruct 3D models from images is Neural Radiance Fields (NeRF), which uses volume density to render the scenes through neural networks. The advantage of NeRF is that it can construct 3D models faster without using high computer processors and memory. NeRF has been studied in various applications, including cultural heritage, but not specifically for rock art documentation. Therefore, this paper evaluates three-dimensional (3D) reconstruction techniques using NeRF on Nerfstudio platform on two rock art datasets and compares them with the point cloud and 3D mesh models obtained from TLS and photogrammetry/MVS. The results have shown that NeRF does not match MVS in achieving geometric precision and texture quality. However, its learning-based approach accelerates reconstruction and offers potential enhancements to complement photogrammetric workflow.