Magnitudes Of Dc Voltage Sources Research Articles

The development of a generalized multilevel inverter for symmetrical and asymmetrical dc sources with a minimized ON state switch

This paper proposes a double source double diode double switch (DSDDDS) multilevel inverter to generate positive voltage and a connecting polarity changing circuit of an H-bridge inverter to generate negative voltage. By connecting the jth number of basic units in series, the desired level is obtained. Various algorithms, such as Natural, Binary, Trinary, and Quasi-Linear sequences, and two proposed algorithms are discussed to determine the magnitude of DC voltage sources in order to generate more stepped levels with fewer switches. The proposed multilevel inverter eliminates the need to turn on additional power switches for different levels, which is the main advantages of this topology. The proposed multilevel inverter is compared to conventional switched diode multilevel inverters in terms of switch count, number of ON state switches per level, driver circuits, and total standing voltage. Real-time results from the OPAL-RT test bench and simulation have validated the proposed inverter.

A Modular Cascaded Multilevel Converter With High Configurability: Design, Analysis, and Optimization Study

This article introduces a new modular cascaded multilevel inverter (MLI) that is composed of a cascaded connection of submodules (SMs). The combination of basic cells (BCs) with polarity changer H-bridge produces the SMs, which is the basis of the introduced inverter. Due to its high modularity, the proposed inverter can be extended to reach higher voltage levels. Hence, two extensions are suggested: 1) extension based on cascading more BCs within each SM and 2) extension based on cascading more SMs. Using a set of algorithms, the magnitude of dc voltage sources is determined to synthesize the proper ac-side voltage waveform. Furthermore, the proposed topology is optimized in different ways to achieve the desired purposes, such as maximizing the number of voltage levels, minimizing the number of switches and dc sources, and providing the least total standing voltage on the switches. Therefore, in each of the mentioned optimization goals, the optimal structure is obtained. A prototype of the presented MLI is defined and its performance is verified through several simulation studies in MATLAB/Simulink and experimental tests. Besides, a comprehensive comparison is made with the best performance of the existing alternatives to demonstrate the merits and superiorities of the proposed MLI.

An improved switched diode multilevel inverter topology with fewer on state switches

A double capacitor double diode double switch (DCDDDS) multilevel inverter is proposed in this paper to generate positive voltage and connect a polarity changing circuit of H-bridge inverter that generates negative voltage. The desired level is achieved by connecting the j th number of basic units in series. To generate more stepped levels with fewer switches, various algorithms, such as Natural, Binary, Trinary, and Quasi-Linear sequences, and two new proposed algorithms are discussed to determine the magnitude of DC voltage sources. The proposed multilevel inverter eliminates the need to turn on more power switches for different levels, which is the highlight of this topology. The proposed multilevel inverter is compared in terms of the switch count, number of ON state switches per level, driver circuits, and total standing voltage with the conventional switched diode multilevel inverters. Real-time results from the test bench of OPAL-RT and simulation have been used to validate the proposed inverter.

A Novel Cascaded Asymmetrical Multilevel Inverter With Reduced Number of Switches

In this article, a new cascaded multilevel inverter has been presented. In order to produce all voltage levels in output voltage waveform, eight different algorithms are proposed to determine the magnitude of dc voltage sources. This topology is able to increase the number of output voltage levels by using lower number of power electronic switches, driver circuits, power diodes, and dc voltage sources. In addition, the low amount of blocked voltage by power electronic switches is another advantage of the proposed inverter. Comparison results with other recently presented topologies in the literature are provided in terms of power electronic switches, blocking voltage, and number of dc voltage sources. Compared to other topologies, the proposed topology utilizes less number of driver circuits, insulated-gate bipolar transistors, and dc voltage sources. To approve the practicability of the proposed inverter, a prototype of the proposed topology for 57 level has been implemented. The operation and performance of the proposed topology in generating the positive and negative levels is verified through the experimental results on a 57-level inverter.

Design, analysis and implementation of a generalised topology for multilevel inverters with reduced circuit devices

This study proposes a multilevel inverter with optimised structure from switching device number point of view. Configuration of the presented multilevel inverter is modular and extendable. Three different methods are introduced to determine the magnitude of DC voltage sources. Characteristics of inverter topology based on suggested methods are given and compared with each other. Also, the proposed multilevel inverter is compared with some similar topologies in terms of controlled switches, driver circuits, DC voltage sources and total blocking voltage to verify its advantages and probable disadvantages where the results show the superiority of the proposed topology in the comparison items. Selective harmonic elimination pulse width modulation technique is applied to achieve output voltage with high quality. Finally, a laboratory prototype of the proposed multilevel inverter is implemented and then, the experimental and simulation results are derived to validate the inverter capability in generating staircase waveforms.

Flexible transformer‐based multilevel inverter topologies

Cascaded multilevel inverters (MLIs) have been proposed that utilise transformers in the basic unit. The proposed inverters primarily serve to step up the input voltages in addition to using lower number of components in comparison to traditional MLIs. In order to generate all voltage levels (even and odd) at the output, three different algorithms are proposed to determine the magnitude of DC voltage sources and transformer turn ratios. Also, the basic inverter unit was further developed and two new flexible MLI structures have been obtained. The developed structures increase the input voltage with no need for an additional boost converter. A reduction in the number of power switches, the peak inverse voltage, and the number of DC voltage sources are other advantages of the proposed topologies. Also, a simple cost model was developed and the dimensionless cost coefficient was determined. The overall cost of the proposed MLIs was compared to the similar MLIs from the literature. It was shown that the proposed MLI decrease the overall cost of the system if the cost coefficient is selected appropriately. To verify the performance of the proposed topologies simulated by the mathematical model; several lab-scale inverters were built and tested and good agreement was achieved.

Optimal Design of a New Cascaded Multilevel Inverter Topology With Reduced Switch Count

Multilevel inverters (MLIs) are a great development for industrial and renewable energy applications due to their dominance over conventional two-level inverter with respect to size, rating of switches, filter requirement, and efficiency. A new single-phase cascaded MLI topology is suggested in this paper. The proposed MLI topology is designed with the aim of reducing the number of switches and the number of dc voltage sources with modularity while having a higher number of levels at the output. For the determination of the magnitude of dc voltage sources and a number of levels in the cascade connection, three different algorithms are proposed. The optimization of the proposed topology is aimed at achieving a higher number of levels while minimizing other parameters. A detailed comparison is made with other comparable MLI topologies to prove the superiority of the proposed structure. A selective harmonic elimination pulse width modulation technique is used to produce the pulses for the switches to achieve high-quality voltage at the output. Finally, the experimental results are provided for the basic unit with 11 levels and for cascading of two such units to achieve 71 levels at the output.

Multilevel inverter for interfacing renewable energy sources with low/medium‐ and high‐voltage grids

This study presents a new multilevel inverter (MLI) with reduced devices, for low/medium- and high-voltage applications. The proposed MLI is evolved from existing cross-connected source-based multilevel inverter (CCS-MLI), results in reduced switches, driver circuits, diodes, and DC voltage sources when compared with the classical CHB, CCS-MLI, and other MLIs. Owing to reduced device numbers, the complexity, size, cost, and maintenance of the proposed topology are greatly reduced. The detailed analysis and working of the proposed topology is presented along with its comparison with classical, CCS-MLI, and other MLIs. Different algorithms are presented for selecting appropriate magnitudes of DC voltage sources to generate different voltage levels in the output. The proposed MLI is suitable for grid integration of renewable energy sources. The concept is presented through modelling and simulation in MATLAB/Simulation environment and validated through real-time simulator OPAL-RT (OP-4500).

Neoteric Hybrid Multilevel Cascade Inverter Based on Low Switch Numbers Along with Low Voltage Stress: Design, Analysis, Verification

Abstract: With the purpose of rein in the high voltage of flexible power systems, renovation and amendment of multi-level structures aimed at acquisition of high quality voltage is certainly required. In this regard, robust topology must be occupied that encompass the maximum output voltage levels along with minimum of switch number, of course, with taking into account of Peak Inverse Voltage (PIV). In this paper, a neoteric high-performance multilevel cascaded inverter is suggested up to the problem of repetitive output levels to be unraveled and also number of output voltage levels to be maximized. It has been constructed by series-connected multilevel inverters blocks and three-level inverter. The simulation results along with experimental results extracted by manufactured prototype have transparently approved high efficiency of proposed inverter as well as its feasibility. Apart from above, new mathematical approach has been presented to calculate and define the DC voltage sources magnitudes in asymmetric converter.

Optimal Structures for Cascaded Multilevel Inverter

The general function of a multilevel inverter is to synthesize a desired output voltage from several levels of dc voltages as inputs. In order to increase the steps in the output voltage, a new H- bridge topology is recommended which benefits from a series connection of several sub-multilevel inverters. In addition, for producing an output voltage with a constant number of steps, there are different configurations with a different number of components. In this paper, the optimal structures for H- bridge topology are investigated for various objectives such as minimum number of switches and dc voltage sources and minimum standing voltage on the switches for producing the maximum output voltage steps. Two new algorithms for determining the dc voltage sources magnitudes have been proposed. Finally, in order to verify the theoretical issues, simulation results for 25 level inverter with a maximum output voltage of 120V are presented.

A New Cascaded Multi-level Inverter Topology with Reduced Number of Components and Charge Balance Control Methods Capabilities

In this article, a new basic unit for cascaded multi-level inverter is proposed. This inverter is able to increase the number of output voltage levels and reduces the number of power electronic devices. To generate all voltage levels at the output, five different algorithms to determine the magnitude of DC voltage sources are suggested. This inverter is compared with conventional cascaded multi-level inverters. The comparisons show that the proposed topology needs fewer DC voltage sources and power switches, less variety of the magnitude of DC voltage sources, and smaller amounts of blocked voltage by switches. As a result, the installation space and total cost of the inverter decrease. As it is impossible to use charge balance control methods for the asymmetric cascaded multi-level inverters, the developed topology based on the proposed cascaded inverter–the sub-symmetric topology with the usability of charge balance control methods–is proposed. A new algorithm is proposed to determine the magnitude of DC voltage sources. In addition, full-wave and half-wave charge balance control methods are applied in the proposed developed topology. The accurate performance of the proposed topology by applying charge balance control methods is verified through the simulation and experimental results of an 81-level sub-symmetric inverter.

A Single-Phase Cascaded Multilevel Inverter Based on a New Basic Unit With Reduced Number of Power Switches

In this paper, a new single-phase cascaded multilevel inverter is proposed. This inverter is comprised of a series connection of the proposed basic unit and is able to only generate positive levels at the output. Therefore, an H-bridge is added to the proposed inverter. This inverter is called the developed cascaded multilevel inverter. In order to generate all voltage levels (even and odd) at the output, four different algorithms are proposed to determine the magnitude of dc voltage sources. Reduction in the number of power switches, driver circuits, and dc voltage sources is the advantage of the developed single-phase cascaded multilevel inverter. As a result, the installation space and cost of the inverter are reduced. These features are obtained by the comparison of the conventional cascaded multilevel inverters with the proposed cascaded topology. The ability of the proposed inverter to generate all voltage levels (even and odd) is reconfirmed by using the experimental results of a 15-level inverter.

Cascaded Multilevel Inverter With Series Connection of Novel H-Bridge Basic Units

In this paper, a new single-phase cascaded multilevel inverter based on novel H-bridge units is proposed. In order to generate all voltage levels (even and odd) at the output, nine different algorithms are proposed to determine the magnitudes of dc voltage sources. Then, the proposed algorithms are compared to investigate their advantages and disadvantages. This topology is able to increase the number of output voltage levels by using a lower number of power electronic devices such as switches, power diodes, driver circuits, and dc voltage sources that lead to reduction in installation space and cost of the inverter. In addition, in the proposed cascaded multilevel inverter, not only the number of required power electronic devices is reduced, but also the amount of the blocked voltage by switches, and the number of different voltage amplitudes of the used sources is decreased. These features are some of the most important advantages of the proposed topology. These features are obtained via the comparison of the proposed topology and its proposed algorithms with the conventional cascaded multilevel inverters that have been presented in the literatures. The operation and performances of the proposed topology with its presented algorithms in generating all voltage levels have been verified by using the experimental results of a 49-level single-phase inverter.

A New General Topology for Cascaded Multilevel Inverters With Reduced Number of Components Based on Developed H-Bridge

In this paper, a new general cascaded multilevel inverter using developed H-bridges is proposed. The proposed topology requires a lesser number of dc voltage sources and power switches and consists of lower blocking voltage on switches, which results in decreased complexity and total cost of the inverter. These abilities obtained within comparing the proposed topology with the conventional topologies from aforementioned points of view. Moreover, a new algorithm to determine the magnitude of dc voltage sources is proposed. The performance and functional accuracy of the proposed topology using the new algorithm in generating all voltage levels for a 31-level inverter are confirmed by simulation and experimental results.

Switched‐diode structure for multilevel converter with reduced number of power electronic devices

To reduce the number of power electronic devices in multilevel converters, a new switched-diode multilevel converter is proposed in this study. This topology generates a large number of levels with fewer number of insulated gate bipolar transistors (IGBTs), gate driver circuits and power diodes. For recommended multilevel converter, a novel method for determination of dc voltage sources magnitudes is presented. Also, the optimal structures is presented for different aims including less number of IGBTs, gate driver circuits, dc voltage sources and power diodes in order to generating a large number of levels. The proposed structure is compared with other topologies to reflect the merits of the proposed structure. The operation and performance of the proposed topology is verified by experimental and simulation results.

Improvement of Multilevel Inverters Topology Using Series and Parallel Connections of DC Voltage Sources

This paper proposes a new topology for multilevel inverters based on series and parallel {R1–7} connection’s of the dc voltage sources. Series and parallel {R1–7} connections ability of the proposed topology make it capable of increasing the number of voltage levels and the output current, respectively. The proposed topology is optimized from the viewpoint of number of switches, number of dc voltage sources, and maximum blocked voltage by switches. The optimal topologies with minimum number of switches and dc voltage sources are computed to produce the maximum number of output voltage levels with minimum blocked voltage by switches. In addition, a new algorithm for the determination of magnitudes of dc voltage sources is presented. Furthermore, to verify the theoretical aspects, the proposed topology is compared with some of the new presented multilevel inverters. The performance of the proposed multilevel inverter is verified by the simulation and experimental results of a single-phase 25-level inverter.

A new topology for multilevel inverter considering its optimal structures

In this paper, a new topology for multilevel inverters is proposed. The proposed topology consists of a basic unit and a full bridge converter. An extended topology is proposed and for the extended topology, three algorithms have been proposed to determine magnitudes of dc voltage sources. The proposed topology from viewpoint of the number of switches, the number of dc voltage sources, and the number of output voltage steps are optimized. The optimal structures for the extended topology are investigated for various objectives such as minimum number of switches and dc voltage sources for producing the maximum output voltage steps. Both simulation results and experimental verification of the proposed multilevel inverter for a single-phase 19-level multilevel inverter are presented.

Improvement of the Performance of the Cascaded Multilevel Inverters Using Power Cells with Two Series Legs

A modular three-phase multilevel inverter especially suitable for electrical drive applications has been previously presented. This topology is based on series connection of power cells in which each cell comprised of two inverter legs in series. In this paper, in order to generate the maximum number of voltage levels with reduced number of switches, three algorithms are proposed for determination of the magnitudes of dc voltage sources. In addition, a new hybrid multilevel inverter is proposed that is composed of series connection of the previously presented multilevel inverter and some H-bridges. The proposed topology has been compared with some other presented multilevel inverters. The performance of the proposed multilevel inverter has been verified by simulation and experimental results of a single-phase 39-level multilevel inverter.

Asymmetric Cascaded Multi-level Inverter: A Solution to Obtain High Number of Voltage Levels

Multilevel inverters produce a staircase output voltage from DC voltage sources. Requiring great number of semiconductor switches is main disadvantage of multilevel inverters. The multilevel inverters can be divided in two groups: symmetric and asymmetric converters. The asymmetric multilevel inverters provide a large number of output steps without increasing the number of DC voltage sources and components. In this paper, a novel topology for multilevel converters is proposed using cascaded sub-multilevel Cells. This sub-multilevel converters can produce five levels of voltage. Four algorithms for determining the DC voltage sources magnitudes have been presented. Finally, in order to verify the theoretical issues, simulation is presented.

A New Multilevel Converter Topology With Reduced Number of Power Electronic Components

In this paper, a new topology for cascaded multilevel converter based on submultilevel converter units and full-bridge converters is proposed. The proposed topology significantly reduces the number of dc voltage sources, switches, IGBTs, and power diodes as the number of output voltage levels increases. Also, an algorithm to determine dc voltage sources magnitudes is proposed. To synthesize maximum levels at the output voltage, the proposed topology is optimized for various objectives, such as the minimization of the number of switches, gate driver circuits and capacitors, and blocking voltage on switches. The analytical analyses of the power losses of the proposed converter are also presented. The operation and performance of the proposed multilevel converter have been evaluated with the experimental results of a single-phase 125-level prototype converter.