Machine Instruction Level Research Articles

Hierarchical Flight Control System for Tilt-Rotor Drones

This paper presents a hierarchical flight control system for tilt-rotor drones. The offered approach performs high-level mission goals by gradually confirming them into machine-level instructions. The learned data from numerous sensors is spread backside to the greater levels for sensitive decision making. Each vertical take-off and landing drone is linked through regular wireless communication rules for accessible multi-agent facility. The proposed flight control system has been effectively employed on several small tilt-rotor drones and validated in some applications. Solutions from waypoint navigation, a probabilistic chase-evasion competition and vision-based object chasing show the capability of the recommended method for intelligent flying drones.

Quantifying Life Cycle Inventories for Machining Processes at Detailed Design

This paper quantifies machining process inventories based on commonly used techniques in various stages of the detailed design process. We investigate variabilities in process inventories between these techniques and their relation to manufacturing process parameters, which are required for generating machine-level instructions. We also benchmark these process inventory modeling techniques against experimental measurements. We then showcase potential issues of using available process models without properly accounting for product and process differences. Our results caution practitioners against basing their environmental analyses on data collected prior to detailed process planning. We conclude that accurate quantification of machining process inventories requires combining accurate simulation-based models with data-driven estimates for model parameters.

An efficient quantum compiler that reduces T count

Before executing a quantum algorithm, one must first decompose the algorithm into machine-level instructions compatible with the architecture of the quantum computer, a process known as quantum compiling. There are many different quantum circuit decompositions for the same algorithm but it is desirable to compile leaner circuits. A fundamentally important cost metric is the T count—the number of T gates in a circuit. For the single qubit case, optimal compiling is essentially a solved problem. However, multi-qubit compiling is a harder problem with optimal algorithms requiring classical runtime exponential in the number of qubits. Here, we present and compare several efficient quantum compilers for multi-qubit Clifford + T circuits. We implemented our compilers in C++ and benchmarked them on random circuits, from which we determine that our TODD compiler yields the lowest T counts on average. We also benchmarked TODD on a library of reversible logic circuits that appear in quantum algorithms and found that it reduced the T count for 97% of the circuits with an average T-count saving of 20% when compared against the best of all previous circuit decompositions.

Methods and software tools to support combined binary code analysis

Methods and tools for binary code analysis developed in the Institute of System Programming, Russian Academy of Sciences, and their applications in algorithm and data format recovery are considered. The executable code of various general-purpose CPU architectures is analyzed. The analysis is performed given no source codes, debugging information, and specific OS version requirements. The approach implies collecting a detailed machine instruction level execution trace; a method for successively increasing presentation level; extraction of algorithm's code followed by structuring of both code and data formats it processes. Important results are obtained, viz. an intermediate representation is developed that allows carrying out most preliminary processing tasks and algorithm code extraction without having to focus on specifics of a given machine; and a method and software tool are developed for automated recovery of network message and file formats. The tools are integrated into the unified analysis platform that supports their combined use. The architecture behind the platform is also described. Examples of its application to real programs are given.

Методы и программные средства, поддерживающие комбинированный анализ бинарного кода

This paper presents methods and tools for binary code analysis that have been developed in ISP RAS and their applications in fields of algorithm and data format recovery. The analysis subject is executable code of various general purpose CPU architectures. The analysis is carried out in lack of source code, debug records, and without specific OS version requirements. The approach consists of collecting a detailed machine instruction level execution trace; method for successive presentation level increase; extraction of code belonging to the algorithm followed by structuring of both code and data formats it processes. Important results have been achieved: an intermediate representation has been developed, that allows for carrying out most of the preliminary processing tasks and algorithm code extraction without having to focus on specifics of a given machine; and a method and software tool have been developed for automated recovery of network message and file formats. The tools have been incorporated into a unified analysis platform that supports their combined use. The architecture behind the platform is also described in the paper. Examples of its application to real programs are given.

A Parameterized Programmable MIMO Decoding Architecture With a Scalable Instruction Set and Compiler

We present a novel multiple-input multiple-output (MIMO) decoder accelerator and its associated integrated design environment. The accelerator architecture allows tradeoffs in decoding algorithm, antenna configuration, modulation scheme, and bandwidth at run-time via user programming. The accelerator delivers an improvement over a general purpose digital signal processor (DSP) reaching three orders of magnitude for matrix processing and linear MIMO decoding. The hardware architecture is user-configurable through ten independently set parameters. The parameterization allows independent control over the size and structure of the processing core as well as the structure, size, and access scheme of data memory. We provide a custom high level script and a scalable machine level instruction set and compiler. The elements of hardware configuration and programmability are combined in a user-friendly design flow that takes the MIMO decoder designer from simulation to hardware with dedicated-hardware-like performance in no time.

Self-Healing Control Flow Protection in Sensor Applications

Since sensors do not have a sophisticated hardware architecture or an operating system to manage code for safety, attacks injecting code to exploit memory-related vulnerabilities can present threats to sensor applications. In a sensor's simple memory architecture, injected code can alter the control flow of a sensor application to either misuse existing routines or download other malicious code to achieve attacks. To protect the control flow, this paper proposes a self-healing scheme that can stop attacks from exploiting the control flow and then recover sensor applications to normal operations with minimum overhead. The self-healing scheme embeds diversified protection code at particular locations to enforce access control in code memory. Both the access control code and the recovery code are designed to be resilient to control flow attacks that attempt to evade the protection. Furthermore, the self-healing scheme directly processes application code at the machine instruction level, instead of performing control or data analysis on source code. The implementation and evaluation show that the self-healing scheme is lightweight in protecting sensor applications.

Can Programming Be Liberated, Period?

We have come a long way since programming had to be done by tediously listing machine-level instructions that prescribed how a specific computer was to modify and move bits and words in its memory. The author describes his dream about freeing ourselves from the straightjackets of programming, making the process of getting computers to do what we want intuitive, natural, and also fun. He recommends harnessing the great power of computing and transforming a natural and almost playful means of programming so that it becomes fully operational and machine-doable. Once liberated, programmers will probably have new kinds of work to do, possibly including the need to set up specialized features of the new sophisticated computational tools that would be running in the background.

Taking a lesson from stealthy rootkits

Attackers use rootkits and obfuscation techniques to hide while covertly extracting information from commercial applications. The authors describe how developers can use similar obfuscation approaches to build more agile, less vulnerable software. Obfuscation deliberately transforms software into an identically functioning, but purposefully unreadable form, implemented in a high-level programming language at the machine-instruction level, or, to some extent, in the compiled binary. Obfuscation's only requirement is that its generated code be functionally equivalent to its parent.

Automatic validation of code-improving transformations on low-level program representations

This paper presents a general approach for automatically validating code-improving transformations on low-level program representations. The approach ensures the correctness of compiler and hand-specified optimizations at the machine instruction level. The method verifies the semantic equivalence of the program representation before and after a transformation to determine the validity of the transformation. To verify that the transformation is semantics preserving, the method derives semantic effects from the instructions that span the execution paths affected by the transformation. The semantics are preserved if the normalized semantic effects are unchanged. A validating compilation system was implemented that is able to validate traditional compiler transformations and more powerful transformations that modify the branch structure of a program.

Fine grain scheduler for shared-memory multiprocessor systems

The Tatung fine grain scheduler (TFGS), which works on machine instruction level for multiprocessor systems, is described. The object of TFGS is to minimise the total execution time of an application program that is to be executed on a shared memory multiprocessor system. An application program is compiled to generate intermediate code. This code is then represented by a data/control dependence graph, a branch nest tree and a priority list. The data dependence between operations, the pipeline effect of each processing element, and branches in the application programs are considered when TFGS does the scheduling task. The multiprocessor system is assumed to be interconnected by a shared memory. The hardware support of shared memory is designed. To process branches and loops within the application program, a status recording mechanism is proposed. The hardware has been designed and simulated. TFGS has been implemented, and some application programs have been used as the testing inputs. The results are very encouraging.

A multiprocessor architecture combining fine-grained and coarse-grained parallelism strategies

A wide variety of computer architectures have been proposed that attempt to exploit parallelism at different granularities. For example, pipelined processors and multiple instruction issue processors exploit the fine-grained parallelism available at the machine instruction level, while shared memory multiprocessors exploit the coarse-grained parallelism available at the loop level. Using a register-transfer level simulation methodology, this paper examines the performance of a multiprocessor architecture that combines both coarse-grained and fine-grained parallelism strategies to minimize the execution time of a single application program. These simulations indicate that the best system performance is obtained by using a mix of fine-grained and coarse-grained parallelism in which any number of processors can be used, but each processor should be pipelined to a degree of 2 to 4, or each should be capable of issuing from 2 to 4 instructions per cycle. These results suggest that current high-performance microprocessors, which typically can have 2 to 4 instructions simultaneously executing, may provide excellent components with which to construct a multiprocessor system.

Parallel execution on the function‐partitioned processor with multiple instruction streams

AbstractThis paper proposes a parallel execution mechanism with the refinement between machine instruction level to the register transfer level. In the proposed mechanism, the processor is function‐partitioned into a number of processing units, and instruction streams are assigned independently to the processing units. According to the arc indicating the dependency in the control flow graph, the processing units exchange the asynchronous control signals at a high speed. Compared with the synchronous parallel execution mechanism such as VLIW, the proposed mechanism can extract the parallelism in a flexible and detailed way.First, the general parallel computation model based on the proposed mechanism is described. Then the basic configuration of the computer is described for the prototype model based on three classes of machine instructions. A simple evaluation is presented through execution examples of sample programs.

Flow-control machines: the structured execution architecture (SXA)

Can the looping, branching, sequencing, and modularity of structured programming be implemented effectively by single instructions at the machine-instruction level? A proposal for a class of machines to do so is presented. Flow control verbs such as REPEAT and IF/THEN/ELSE are represented in large-format instructions containing pointers to conditional controls and other instructions. An active-instruction stack is used to nest flow structures. Independent buses for logically distinct memory spaces enhance performance.

The implementation of Prolog via VAX 8600 microcode

We have implemented a high performance Prolog engine by directly executing in microcode the constructs of Warren's Abstract Machine. The implementation vehicle is the VAX 8600 computer. The VAX 8600 is a general purpose processor containing 8K words of writable control store. In our system, each of the Warren Abstract Machine instructions is implemented as a VAX 8600 machine level instruction. Other Prolog built-ins are either implemented directly in microcode or executed by the general VAX instruction set. Initial results indicate that our system is the fastest implementation of Prolog on a commercially available general purpose processor.

The design of an interactive compiler for optimizing microprograms

Microprogramming has traditionally been done in assembly language because of the perceived need for fast execution; compiler technology does not yet exist for discovering and performing many of the clever tricks of an experienced microprogrammer. Unfortunately, programming at the machine-instruction level is both tedious and error-prone. A possible compromise between these two approaches is that of an interactive compiler, where the programmer guides the crafting of critical data structures and sections of code, while the compiler ensures that the resulting code has the same semantics as the original program, generates code where speed is not critical, and performs bookkeeping tasks. We are in the process of implementing a prototype of such a system. This paper describes the system being developed and discusses some of the key design issues.

An interactive assembly level debugging system

AbstractAn interactive assembly level debugging system has been developed to facilitate program development on an INTEL 8080A/8085 based microcomputer. It has features such as decoding machine level instructions into the assembly language, relocating programs in memory, changing instructions interactively at assembly level etc. This paper deals with the design of the assembly level debugging system and the various facilities and features it provides. The debugging system requires only 4.5K bytes of RAM besides the memory requirements of the application program that has to be debugged.

Postpass Code Optimization of Pipeline Constraints

Pipeline interlocks are used in a pipelined architecture to prevent the execution of a machine instruction before its operands are available. An alternative to this complex piece of hardware is to rearrange the instructions at compile time to avoid pipeline interlocks. This problem is called code reorganization and is studied. The basic problem of reorganization of machine-level instructions at compile time is shown to be np-complete. A heuristic algorithm is proposed, and its properties and effectiveness are explored. Empirical data from MIPs, a VLSI processor design, are given. The impact of code reorganization techniques on the rest of a compiler system is discussed. 30 references.

Microprogram structures for high level language elements

Some elements of ALGOL-like languages consume much computer time, if they are coded on the machine instruction level. The examples of this paper show that this time and the number of program steps can be drastically reduced by microprogramming and suitable hardware processor structures. Furthermore it seems to be reasonable and possible to translate HLL-programs to microprograms avoiding the machine instruction level. The language MIMOLA is used for the documentation of the microprograms and for the top-down design of the hardware structures. An example structure is given.