MAC Processor Research Articles

CD-MAC: mixed-signal binary/ternary in-memory computing accelerator for power-constrained MAC processing

CD-MAC: mixed-signal binary/ternary in-memory computing accelerator for power-constrained MAC processing

The practice of manager as coach (MAC): Unequal power relations and their effect on feelings toward the organization

AbstractManager as Coach (MAC) is a concept that relates to managers who actively coach their subordinates to improve their skills, competence, and performance. The MAC practice is a popular tool for managers in organizations; however, there is a debate about the benefits gained from coaching by MACs and a theoretical gap regarding the effectiveness of this process. The purpose of this study is to examine the different perceptions of managers who coach their subordinates and subordinates coached by their managers of the coaching process and to estimate the perceived success of this process. In‐depth interviews were conducted with 13 MACs and 9 coachees from various organizations in Israel. Qualitative content analysis was used to analyze and interpret the data. Basic analysis indicates that the perceptions of the MACs toward the coaching process were positive, whereas the coachees held mixed perceptions. The different perceptions point to the unequal power relations between the MACs and the coachees. In the interpretive analysis, it was found that the perceptions toward the MAC process affect coachee feelings toward the organization but not the coach's feelings. Relying on Leader‐Member Exchange (LMX) theory, the MAC process will be successful only if managers significantly reduce power distances. Therefore, organizations must offer their MACs significant coaching training to decrease the negative consequences of the MAC practice and to diminish the power distance between MAC and coachee.

Research and Simulation of a Synchronous Fieldbus Technology Based on OPNET

Synchronous fieldbus technology is based on the traditional CAN bus with the time division technology, so that communication nodes only send data in a characteristic time slice of a communication cycle. The method can eliminate the conflict between nodes and avoid the competition between nodes of the bus. In this paper, the node layer, LLC process layer and MAC process layer models of the synchronous fieldbus technology are established in the OPNET environment, and an experiment is designed to simulate the actual use scenario, and the method is verified. The result of the method is correct, the effect of it is intuitive, the simulation method of it is correct, and it can be used in synchronous fieldbus simulation research and engineering application.

A Bio inspired optimization with Reliable QoS Routing through Efficient Packet Transmission in Mobile ad-hoc Network

A collection of mobile devices is defined as a Mobile Ad-hoc Network (MANET). Without any prior management these devices can communicate and synchronize with one another. The state of the concerned channel determines how much life energy can be increased. It also extends the node's lifetime while it waits for the control messages to be completed. The nodes' lifespan and packet flow quality are harmed in the current system due to unanticipated energy conservation strategies. It causes post-network collapse due to an energy throughput trade off. This failure causes an increase in overhead and a decrease in Time-to-Live (TTL). In addition to proposing a novel performance modeling in Volunteered Computing MANET and tactile internet, this paper discusses an effective buffer management mechanism. The best execution the nodes can achieve with fractional data is depicted for utilities in general. A switch state promoting Optimized mutual MAC (OMAC) process was presented in this study for node conserving energy and the optimal utilization of accessible nodes before their resource drain to link the space between network efficiency conservation based on minimal overhead. As proof of the proposed solution, simulation results are provided. Compared the simulation outcomes with the existing system using the parameters like latency, quantity, node availability & energy consumption.

Energy‐Efficient Memristive Euclidean Distance Engine for Brain‐Inspired Competitive Learning

Euclidean Distance Engine In article number 2100114, a memristive Euclidean distance (ED) engine has been experimentally demonstrated based on the analog MAC process in a 1T1R array by Yi Li, Qingjiang Li, and co-workers. This ED engine shows great capability for accelerating the brain-inspired competitive learning and exhibits high energy efficiency for future applications at the edge.

SDN@home: A method for controlling future wireless home networks

Recent advances in wireless networking technologies are leading toward the proliferation of novel home network applications. However, the landscape of emerging scenarios is fragmented due to their varying technological requirements and the heterogeneity of current wireless technologies. We argue that the development of flexible software-defined wireless architectures, including such efforts as the wireless MAC processor, coupled with SDN concepts, will enable the support of both emerging and future home applications. In this article, we first identify problems with managing current home networks composed of separate network segments governed by different technologies. Second, we point out the flaws of current approaches to provide interoperability of these technologies. Third, we present a vision of a software-defined multi-technology network architecture (SDN@home) and demonstrate how a future home gateway (SDN controller) can directly and dynamically program network devices. Finally, we define a new type of flexibility enabled by SDN@home. Wireless protocols and features are no longer tied to specific technologies but can be used by general-purpose wireless SDN devices. This permits satisfaction of the requirements demanded by home owners and service providers under heterogeneous network conditions.

Performance Analysis of MAC in VDL2 Based on OPNET Simulation

As one of VHF data links of ATN, VDL2 is publicly recognized as the next generation data-link in the transition period. The paper focused in the performance research of MAC, of which p-CSMA is the core protocol, based on network simulation. As the precondition of simulation, we build VDL2 model in an integral way and realize MAC process modules in both ground station side and aircraft side applying dynamic process and queue management mechanism. In the paper, Performance targets are defined to evaluate the system performance. Through simulation, trends between parameters and targets are reached and the relationships are revealed between packet delay and throughput\ packets strength.

Variation-Aware Voltage Level Selection

In this paper, we address the problem of variation-aware selection of voltage levels for system-on-chips (SoCs) that are organized into multiple frequency and voltage domains. Conventionally, the voltage levels for each domain, as well as the mapping between frequencies and voltages, are determined without considering variations. In the presence of variations, these choices are often suboptimal since the frequency versus voltage characteristics vary from one SoC instance to another and across different voltage domains within an instance. We present a two-pronged approach to address this problem. First, we propose breaking the conventional fixed coupling between voltage levels and frequencies and demonstrate that performing this association based on the characteristics of individual chip instances can lead to significant improvements in power and performance. Second, we show that voltage levels that are computed while accounting for variations can lead to further improvements. We present a methodology to determine a set of discrete voltage levels in a variation-aware manner by generating and quantizing the ideal voltage distribution for a given SoC. Our experiments on an 802.11 MAC processor SoC indicate that the proposed techniques lead to significant improvements in power and performance characteristics in the presence of variations. We obtained an improvement of up to 68% in parametric yield (number of chips meeting power and performance targets) compared to conventional voltage scaling.

A data flow optimization method for high speed MAC processing in an IEEE 802.16m modem

IEEE 802.16m technology is expected to provide high speed packet data service over wireless. Due to the large amount of data to be processed over a short period of time, an efficient MAC processing in the modem is crucial. Since the MAC processing algorithm has optimization limitations, we focus on a data flow optimization in the system level design, so that the number of external memory accesses is minimized. Experimental results show that our approach results in an up to sixteen times faster IEEE 802.16m modem system.

Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication

The on-chip communication architecture is a primary determinant of overall performance in complex system-on-chip (SoC) designs. Since the communication requirements of SoC components can vary significantly over time, communication architectures that dynamically detect and adapt to such variations can substantially improve system performance. In this paper, we propose Flexbus, a new architecture that can efficiently adapt the logical connectivity of the communication architecture and the components connected to it. Flexbus achieves this by dynamically controlling both the communication architecture topology, as well as the mapping of SoC components to the communication architecture. This is achieved through new dynamic bridge by-pass, and component remapping techniques. In this paper, we introduce these techniques, describe how they can be realized within modern on-chip buses, and discuss policies for run-time reconfiguration of Flexbus-based architectures.The techniques underlying Flexbus are general, and are applicable to a variety of bus standards. We have implemented Flexbus as an extension of the popular AMBA AHB bus, and have evaluated it using a commercial design flow. We report on experiments conducted to analyze its area, timing, and performance under a wide variety of system-level traffic profiles. We have applied Flexbus to two example SoC designs: 1) an IEEE 802.11 MAC processor and 2) an UMTS turbo decoder. Our results show that Flexbus provides gains of up to 34.55 % in application data-rates over conventional architectures, with negligible area overhead and a 3.2% penalty in clock period.

Maximizing Production Capacity With Intelligent-Well Systems in a Deepwater West Africa Field

This article, written by Technology Editor Dennis Denney, contains highlights of paper SPE 103308, "Maximizing Production Capacity Using Intelligent- Well Systems in a Deepwater, West Africa Field," by D.J. Goggin, M.A. Ovuede, N. Liu, SPE, U. Ozdogan, SPE, P.B. Coleman, SPE, and D.P. Meinert, SPE, Chevron; I. Nygard, Statoil; and J. Gontijo, Petroleo Brasileiro Nigeria, prepared for the 2006 SPE Annual Technical Conference and Exhibition, San Antonio, Texas, 24–27 September. Large, deepwater fields with a limited number of wells may require intelligent-well systems to maximize production capacity under facility constraints. Agbami field, a highly dipping reservoir with many producing zones and few wells, will use intelligent-well systems consisting of interval-control valves (ICVs) and many sensors to monitor, analyze, and control (MAC) injection and production at the zonal level. Introduction A key objective for optimizing asset performance is maximizing and accelerating recovery by producing wells at optimal rates, which will delay the arrival of water and gas while honoring the mechanical limitations of the production network (e.g., flowlines, manifolds, risers, and separators). The challenge for operators is to know where the excess production capacity exists in the network at any given time and what control settings can be adopted if well failures occur. Therefore, a MAC process is used to respond to unplanned operational interruptions and to be prepared for longer-term reservoir behavior caused by geologic uncertainties. Reservoir Description The overall field structure is a northwest/southeast-trending four-way-closure anticline on the Niger delta front, approximately 65 miles offshore Nigeria in the Gulf of Guinea. The anticlinal structure has dip angles as steep as 30° on the northeast and southwest flanks. From 3D-seismic data, several faults have been mapped across the anticlinal structure. A major thrust fault divides the Agbami field into inboard (northeast) and outboard (southwest) halves. Normal faults further subdivide the field into eight potentially noncommunicating areas. The high structural dip and the fault compartments are important factors in the well-placement strategy, injection patterns, and oil-recovery expectation. The field has four stacked reservoirs with distinct pressure profiles. The current geologic model includes three of these reservoirs designated as 14MY, 16MY, and 17MY. The 17MY reservoir contains 80% of the total-field oil-in-place of approximately 2 billion bbl. Field-Development Plan and Production Network The field-development plan recommends midflank oil production with crestal gas injection and peripheral water injection as the primary oil-recovery, pressure-maintenance, and gas-disposition scheme in the 17MY units. Oil properties of 47°API gravity and 0.23-cp viscosity are favorable to a combined crestal miscible-gas drive and peripheral water-injection scheme in a highly dipping reservoir. Thirty-eight wells are planned in three drilling stages. Plans include 17 Stage-1 wells drilled and completed before first oil production, comprising 10 producers, four water injectors, and three gas injectors. Stages-2/-3 drilling occurs after first oil production.

Efficient Power Profiling for Battery-Driven Embedded System Design

The ability to efficiently and accurately estimate battery life under different design choices at the system level is an important aid in designing battery-efficient systems. Recently developed battery models help by estimating battery life under given profiles of the battery discharge current over time. However, existing techniques for energy (or average power) estimation do not provide sufficient information (such as time profiles of system power consumption) to drive battery-life estimation. Techniques that are capable of generating such profiles often lack the efficiency required to support exploration at the system level. In this paper, we describe techniques for efficient generation of system-level power profiles, for use in a battery-life estimation framework. Our power profiling technique allows a designer to experiment with: 1) the mapping of system tasks to a set of architectural components and 2) the mapping of system communications to a specified communication architecture, and efficiently generate system power profiles for each alternative. The resulting profiles can then be analyzed using existing battery models to estimate battery lifetime and capacity. Extensive experiments conducted on an IEEE 802.11 MAC processor design demonstrate that our power profiler offers orders of magnitude improvement in runtimes over state-of-the-art cosimulation-based power estimation techniques, while suffering minimal loss of accuracy (average profiling error was 3.8%).

Topics in circuits for communications - Design and implementation of an all-cmos 802.11a wireless lan chipset

The tremendous growth in wireless LANs has generated interest in technologies that provide higher data rates and greater system capacities. The IEEE 802.11a standard, based on coded OFDM modulation, provides nearly five times the data rate and at least 20 times the overall system capacity compared to the incumbent 802.11b wireless LAN systems. This article describes the design challenges and circuit implementation of a two-chip set that forms a complete 802.11a solution in 0.25 μm CMOS technology. Wherever possible, sophisticated digital signal processing techniques are used to compensate for possible analog impairments associated with integrating RF circuitry in a CMOS technology. The analog portion of the chip set implements a 5 GHz transceiver comprising all the necessary RF and analog circuits of the 802.11a standard integrated on a single chip. Some features of this IC include 22 dBm peak transmitted power, 8 dB overall receive-chain noise figure, and -112 dBc/Hz synthesizer phase noise at 1 MHz frequency offset. The digital portion of the chip set, the baseband and MAC processor, contains dual ADCs/DACs and all the digital circuits for synchronization, detection, and 802.11 MAC layer data processing. This IC delivers up to 54 Mb/s in a 20 MHz channel according to the 802.11a standard, and includes proprietary modes supporting up to 108 Mb/s in a 40 MHz channel.