LSB DNL Research Articles

Flexible and fully integrated 4-bit SAR ADC using metal-oxide TFTs

This paper presents a flexible fully integrated 4-bit successive approximation register (SAR) analog-to-digital converter (ADC), which is fabricated by unipolar n-type indium-zinc-oxide thin-film transistors. A bootstrap switch and a comparator with a pre-amplifier are proposed and employed to realize the SAR ADC. The fabricated SAR ADC achieves a sampling rate of up to 20 kHz and a peak signal-to-noise and distortion ratio of 22.9 dB, corresponding to an effective-number-of-bits of 3.52 bits. The static performance of −0.58/+0.37 LSB DNL and −0.49/+0.39 LSB INL is achieved.

Pipelined Memristive Analog-to-Digital Converter With Self-Adaptive Weight Tuning

Benefiting from area and power efficiency, memristors enable the development of neural network analog-to-digital converter (ADC) to break through the limitations of conventional ADCs. Although some memristive ADC (mADC) architectures have been proposed recently, the current research is still at an early stage, which is mainly on the simulation and requires numerous target labels to train the synapse weights. In this paper, we propose a pipelined Hopfield neural network mADC architecture and experimentally demonstrate that such mADC has the capability of self-adaptive weight tuning. The proposed training algorithm is an unsupervised method originated from the random weight change (RWC) algorithm, which is modified to reduce the complexity of error feedback circuit to make it more hardware friendly. The synapse matrix could be adapted to the 1T1R crossbar array. For an 8-bit two-stage pipelined mADC, the proposed architecture in the simulation could achieve 7.69 fJ/conv FOM, 7.90 ENOB, 0.1 LSB INL, and 0.1 LSB DNL. And the experimental performance only achieves 1.56 pJ/conv FOM, 7.59 ENOB, 0.21 LSB INL, and 0.29 LSB DNL, which is mainly limited by the comparator’s switching time.

A 4.32-ps precision Time-to-Digital Convertor using multisampling wave union method on a 28-nm FPGA

In this paper, a fully implemented field programmable gate array (FPGA) based time-to-digital converter (TDC) using multisampling wave union method (MSWU) is proposed to get higher measurement precision with lower resource utilization. Different from the previously published works based on wave union methods, an inverter-chain-based wave launcher is introduced to generate more low-jitter edges in the same operation range. Meanwhile, a new de-bubble solution combining with offline bin alignment and online bin sorting is applied to eliminate severe bubbles in FPGAs of advanced manufacturing technologies. The proposed TDCs are verified on a Virtex-7 (28 nm) of FPGA development board VC707. According to test results, the average measurement precision and mean resolution reach 4.32 ps and 0.82 ps, respectively with [-0.98;3.43] LSB DNL and [-6.06;34.1] LSB INL. A complete TDC channel only uses 831 D-type flip-flops (DFFs), 1305 look-up tables (LUTs) and 6 block random access memories (BRAMs) of 36k bits.

A 9.38-bit, 422nW, high linear SAR-ADC for wireless implantable system

In wireless implantable systems (WIS) low power consumption and linearity are the most prominent performance metrics in data acquisition systems. successive approximation register-analog to digital converter (SAR-ADC) is used for data processing in WIS. In this research work, a 10-bit low power high linear SAR-ADC has been designed for WIS. The proposed SAR-ADC architecture is designed using the sample and hold (S/H) circuit consisting of a bootstrap circuit with a dummy switch. This SAR-ADC has a dynamic latch comparator, a split capacitance digital to analog converter (SC-DAC) with mismatch calibration, and a SAR using D-flipflop. This architecture is designed in 45 nm CMOS technology. This ADC reduces non-linearity errors and improve the output voltage swing due to the usage of a clock booster and dummy switch in the sample and hold. The calculated outcomes of the proposed SAR ADC display that with on-chip calibration an ENOB of 9.38 (bits), spurious free distortion ratio (SFDR) of 58.621 dB, and ± 0.2 LSB DNL and ± 0.4LSB INL after calibration.

Breaking Through the Speed-Power-Accuracy Tradeoff in ADCs Using a Memristive Neuromorphic Architecture

The analog-to-digital converter (ADC) is a principal component in every data acquisition system. Unfortunately, modern ADCs tradeoff speed, power, and accuracy. In this paper, novel neuroinspired approaches are used to design a smart ADC that could be trained in real time for general purpose applications and break through conventional ADC limitations. Motivated by artificial intelligent learning algorithms and neural network architectures, the proposed ADC integrates emerging memristor technology with CMOS. We design a trainable four-bit ADC with a memristive neural network that implements the online gradient descent algorithm. This supervised machine learning algorithm fits multiple application specifications such as full-scale voltage ranges and sampling frequencies. Theoretical analysis, as well as simulation results, demonstrate highly powerful collective properties, including reconfiguration, mismatch self-calibration, adaptation to dynamic voltage and frequency scaling, noise tolerance, and power consumption optimization. The proposed ADC achieves 8.25 fJ/conv FOM, 3.7 ENOB, 0.4 LSB INL, and 0.5 LSB DNL. These promising properties make it a leading contender for general purpose and emerging data driven applications.

Two-step pulse-shrinking time-to-digital converter

This paper presents a two-step pulse-shrinking time-to-digital converter (TDC) consisting of a 4-stage coarse pulse-shrinking TDC with per-stage shrinkage 1ns and a 4-stage fine pulse-shrinking TDC with per-stage shrinkage 250ps. A simple residual time extraction scheme is proposed to extract the residual pulse of the coarse TDC. The characteristics of the TDC including mismatch and noise-induced timing errors, timing errors of delay blocks, conversion time, power consumption, and silicon consumption are analyzed in detail. The proposed TDC was implemented in an IBM 130nm 1.2V CMOS technology. Simulation results show that the proposed TDC offers 1.4ns conversion time, 1 LSB DNL and INL, and figure-of-merit (FoM) of 0.163pJ/step. Some measurement results of the proposed TDC are also presented.

A Hybrid AMOLED Driver IC for Real-Time TFT Nonuniformity Compensation

An active matrix organic light emitting diode (AMOLED) display driver IC, enabling real-time thin-film transistor (TFT) nonuniformity compensation, is presented with a hybrid driving method to satisfy fast driving speed, high TFT current accuracy, and a high aperture ratio. The proposed hybrid column-driver IC drives a mobile UHD $\left({{3840} \times {2160}} \right)$ AMOLED panel, with one horizontal time of ${7}.{7}\,{\upmu \text{s}}$ at a scan frequency of 60 Hz, simultaneously senses the TFT current for back-end TFT variation compensation. Due to external compensation, a simple 3T1C pixel circuit is employed in each pixel. Accurate current sensing and high panel noise immunity is guaranteed by a proposed current-sensing circuit. By reusing the hybrid column-driver circuitries, the driver embodies an 8 bit current-mode ADC to measure OLED $V$ – $I$ transfer characteristic for OLED luminance-degradation compensation. Measurement results show that the hybrid driving method reduces the maximum current error between two emulated TFTs with a 60 mV threshold voltage difference under 1 gray-level error of 0.94 gray level (37 nA) in 8 bit gray scales from 12.82 gray level (501 nA). The circuit-reused current-mode ADC achieves 0.56 LSB DNL and 0.75 LSB INL.

Time interval generator with 8 ps resolution and wide range for large TDC array characterization

Accurate generation of picosecond-resolution wide---range time intervals gives rise to a new time-efficient method for the characterization of large arrays of time-to-digital converters involved in time resolved imaging. This paper presents the design and measurement of a time interval generator based on FPGA technology. Although it can be employed in different automatic test setups, it has been designed to characterize an array of time-to-digital converters. It can work as periodic pulse/frequency generator but also as a digital-to-time converter. The accuracy of periodic pulse generator is around 20 ps RMS jitter for a pulse width ranging from 600 ps to 33 µs. The incremental time resolution is 8 ps and the repetition rate is up to 2 MHz. The accuracy of the digital-to-time converter is less than 0.8LSB DNL and 2LSB INL, whilst the time resolution is 27 ps. Full characterization of the module is reported including a comparison with state-of-the-art instruments in this field. The measurement results of the time-to-digital converter array driven by the designed digital-to-time converter module are presented as well. The effectiveness of the proposed method is evaluated by comparing it with the statistical code density test.

10-bit segmented current steering DAC in 90nm CMOS technology

This special project presents a 10-Bit 1Gs/s 1.2V/3.3V Digital-to-Analog Converter using1 Poly 9 Metal SAED 90-nm CMOS Technology intended for mixed-signal and power IC applications. To achieve maximum performance with minimum area, the DAC has been implemented in 6+4 Segmentation. The simulation results show a static performance of ±0.56 LSB INL and ±0.79 LSB DNL with a total layout chip area of 0.683 mm2.The segmented architecture is implemented using two sub DAC's, which are the LSB and MSB section with certain number bits. The DAC is designed using 4-BitBinary Weighted DAC for the LSB section and 6-BitThermometer-coded DAC for the MSB section. The thermometer-coded architecture provides the most optimized results in terms of linearity through reducing the clock feed-through effect especially in hot switching between multiple transistors. The binary- weighted architecture gives better linearity output in higher frequencies with better saturation in current sources.

A single shot TDC with 4.8 ps resolution in 40 nm CMOS for high energy physics applications

A robust TDC with 4.8 ps bin width has been designed for harsh environments and high energy physics applications. The circuit uses resistive interpolation DLL with a novel dual phase detector architecture. This architecture improves startup- and recovery speed from single event strikes without control voltage ripple trade-off and requires no off-line calibrations. A 0.43 LSB DNL has been measured at a power consumption of 4.2 mW with an extended frequency range from 0.8 GHz to 2.4 GHz. The TDC has been processed in 40 nm CMOS technology.

A wideband calibration-free 1.5-GS/s 8-bit analog-to-digital converter with low latency

This article presents a wideband calibration-free 8-bit analog-to-digital converter (ADC) with low latency. The ADC employs a two-stage cascaded folding and interpolating architecture. A high-linearity and wideband track-and-hold amplifier combined with a low-parasitic-capacitance folding amplifier is employed to improve the performance. A binary-ROM with "keep-alive" current is proposed to guarantee no miscode when large bit-rate is input. When the sampling frequency is 1.5 GHz, the ADC achieves +0.29/?0.20 LSB DNL and 0.90 LSB INL. The ADC's effective-number-of-bit and spur-free-dynamic-range are 7.0 bit and 51.8 dB respectively at 230 MHz input. The effective-resolution-bandwidth exceeds the second Nyquist zone up to 1.8 GHz. All of this makes this ADC suitable for wideband digital receiver system.

Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC

Charge redistribution based successive approximation (SA) analog-to-digital converter (ADC) has the advantage of power efficiency. Split capacitor digital-to-analog converter (CDAC) technique implements two sets of binary-weighted capacitor arrays connected by a bridge capacitor so as to reduce both input load capacitance and area. However, capacitor mismatches degrade ADC performance in terms of DNL and INL. In this work, a split CDAC mismatch calibration method is proposed. A bridge capacitor larger than conventional design is implemented so that a tunable capacitor can be added in parallel with the lower-weight capacitor array to compensate for mismatches. To guarantee correct CDAC calibration, comparator offset is cancelled using a digital timing control charge compensation technique. To further reduce the input load capacitance, an extra unit capacitor is added to the higher-weight capacitor array. Instead of the lower-weight capacitor array, the extra unit capacitor and the higher-weight capacitor array sample analog input signal. An 8-bit SA ADC with 4-bit + 4-bit split CDAC has been implemented in a 65nm CMOS process. The ADC has an input capacitance of 180fF and occupies an active area of 0.03mm2. Measured results of +0.2/-0.3LSB DNL and +0.3/-0.3LSB INL have been achieved after calibration.

A 1.8 V 1.0 GS/s 10b Self-Calibrating Unified-Folding-Interpolating ADC With 9.1 ENOB at Nyquist Frequency

An advance in folding-interpolating ADCs is presented that simplifies their extension to higher resolution by building the converter out of identical but scaled pipelined cascaded folding stages. The limitation of the classical folding architecture [1] is the separate coarse channel to determine which fold an input signal is in. Higher-resolution ADCs benefit from a higher order of folding, which results in more closely spaced folds and makes the alignment between this “fine” channel and the “coarse” channel increasingly difficult due to offset and settling mismatch. In this paper we eliminate this separate coarse channel using instead a single “unified” set of cascaded folding stages, in which each folding stage acts as the coarse channel for the following folding stage. This extends the work of [2] where the coarse channel is distributed and [3] where the cascaded folding stages are pipelined. Our approach is demonstrated in a dual 1.8V 1.0GS/s 10b ADC that achieves ±0.2 LSB DNL and 9.1 ENOB at Nyquist while consuming 1.2W/channel.

A 1.8-V 1.6-GSample/s 8-b self-calibrating folding ADC with 7.26 ENOB at Nyquist frequency

This study demonstrates for the first time the significant performance enhancement that calibration brings to folding-interpolating analog-to-digital converters (ADCs). The resulting 1.8-V ADC in 0.18-/spl mu/m CMOS achieves a conversion rate exceeding 1.6 GSample/s, since the amplifier device sizes can be minimized to maximize speed without the restriction of device matching. At 1.6 GS/s, the ADC achieves 0.15 LSB DNL, 0.35 LSB INL, 7.6 effective number of bits (ENOBs) at 100 MHz input, and 7.26 ENOB at Nyquist. At this speed, current consumption from a single 1.8-V supply is 245 mA analog, 185 mA digital, and 90 mA for the LVDS drivers. The ac performance is approximately 1.5 ENOBs higher compared to the same circuit with calibration disabled. The use of best design practices to optimize the ADC linearity prior to introducing calibration resulted in this small required dynamic calibration range, simplifying the calibrator circuitry and resulting in stable continuous performance over time without recalibration. Therefore, the fully on-chip calibration is performed automatically, just one time at power-up.

A 10 bit 30 MSPS CMOS A/D converter for a high performance video application system

In a video application system, an A/D converter which converts the analog signal into digital codes plays an important role in determining the system performance. In this paper, a high performance A/D converter which has 10-bit resolution and 30 MSPS conversion speed is proposed. It has an architecture of pipeline style. With 0.5 /spl mu/m double poly and double metal fully CMOS technology, the experimental prototype of the proposed A/D converter has /spl plusmn/0.7 LSB INL, and /spl plusmn/0.5 LSB DNL.

A 3 V 6-bit 70 MSPS dual CMOS A/D converter for DBS (direct broadcasting for satellite)

In a front-end receiver of DBS (direct broadcasting for satellite), the A/D converter, which converts I/Q signals of the QPSK demodulator into the digital domain, has an important role in determining the system performance. A 3 V dual A/D converter which has a 6-b resolution and a 70 MSPS conversion rate is proposed. It has a dual flash architecture in which comparators use an auto-zero offset cancellation technique with 0.65 /spl mu/m double-poly and double-metal CMOS technology, the experimental prototype of the proposed A/D converter has /spl plusmn/0.7 LSB INL (integral non-linearity error) and /spl plusmn/0.9 LSB DNL (differential non-linearity error).