Low-voltage Operational Transconductance Amplifier Research Articles

Excel Methods to Design and Validate in Microelectronics (Complementary Metal–Oxide–Semiconductor, CMOS) for Biomedical Instrumentation Application

CMOS microelectronics design has evolved tremendously during the last two decades. The evolution of CMOS devices to short channel designs where the feature size is below 1000 nm brings a great deal of uncertainty in the way the microelectronics design cycle is completed. After the conceptual idea, developing a thinking model to understand the operation of the device requires a good “ballpark” evaluation of transistor sizes, decision making, and assumptions to fulfill the specifications. This design process has iterations to meet specifications that exceed in number of the available degrees of freedom to maneuver the design. Once the thinking model is developed, the simulation validation follows to test if the design has a good possibility of delivering a successful prototype. If the simulation provides a good match between specifications and results, then the layout is developed. This paper shows a useful open science strategy, using the Excel software, to develop CMOS microelectronics hand calculations to verify a design, before performing the computer simulation and layout of CMOS analog integrated circuits. The full methodology is described to develop designs of passive components, as well as CMOS amplifiers. The methods are used in teaching CMOS microelectronics to students of electronic engineering with industrial partner participation. This paper describes an exhaustive example of a low-voltage operational transconductance amplifier (OTA) design which is used to design an instrumentation amplifier. Finally, a test is performed using this instrumentation amplifier to implement a front-end signal conditioning device for CMOS-MEMS biomedical applications.

0.5-V High Linear and Wide Tunable OTA for Biomedical Applications

This paper presents a low-voltage nano-power multiple-input operational transconductance amplifier (MI-OTA) with high linearity performance and increased input voltage swing. The enhanced performances are achieved thanks to employing several techniques as the bulk-driven, source-degeneration, self-cascode and negative conductance along with the concept of the input signal attenuation formed by multiple-input MOS transistor. The MI-OTA is widely tunable that serves for biological signals processing. A 3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rd</sup> -order Butterworth band-pass filter (BPF) for electrocardiogram (ECG) signal processing with 55.8 dB dynamic rang is presented. The MI-OTA circuit is designed for 0.5V voltage supply and offers a 0.22% total harmonic distortion (THD) for 0.2V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pp</sub> input signal with total power consumption of 13.4nW. Extensive simulation results including Monte Carlo analysis and process, voltage, temperature (PVT) corners using the 0.18μm CMOS technology from TSMC confirm the characteristics of the proposed MI-OTA and the filter.

Nanopower multiple-input DTMOS OTA and its applications to high-order filters for biomedical systems

A new solution for a low-voltage multiple-input dynamic threshold operational transconductance amplifier (MIDT OTA) for low-frequency signal processing applications is presented. The differential pairs of the proposed OTA combine, for the first time, the multiple-input MOS technique along with the dynamic threshold voltage MOS to achieve a very simple and power-efficient CMOS structure with increased total transconductance. Further, the proposed MIDT OTA has been used to realize a fifth-order low-pass filter (LP) and a sixth-order band-pass filter (BP) using coupled-biquads. The proposed OTA and the filter applications are supplied with 0.5 V and consume 5 nW and 25 nW, respectively. The input band pass filter noise is 82.76 µV, while the dynamic range is 59.5 dB for the third intermodulation distortion (IMD) of 2%. The proposed circuits were designed in a 0.18 µm TSMC technology, and validated by simulations using Cadence platform.

Subthreshold biased enhanced bulk-driven double recycling current mirror OTA

This paper presents a single-stage bulk-driven double recycling low-voltage low-power operational transconductance amplifier (OTA) operating in subthreshold region. The proposed OTA utilizes double recycling topology and provides enough open loop voltage gain, slew rate, and unity gain frequency (UGF). The flipped voltage follower-based adaptively biased input differential pair working in class AB mode has ensured dynamic current boosting and increased slew rate. Further, the proposed OTA has utilized partial positive feedback to mitigate some of the performance reduction caused by the bulk-driven topology. The simulation results of the proposed OTA have ensured open loop gain of 79.5 dB, UGF of 37.1 kHz, and phase margin of 64°. It operates with dual power supply of ± 0.25 V and consumes low power of 60 nW. These performance parameters validate its usefulness for LV, LP and low-frequency applications. The process, voltage, and temperature variation effects on low-frequency voltage gain, UGF, and phase margin of the proposed OTA has also been investigated with process corner simulations. The proposed OTA is designed and simulated in UMC 180 nm standard n-tub bulk CMOS process technology utilizing Tanner EDA tools.

A new low-voltage operational transconductance amplifier with push-pull CMFB scheme for low-pass filter applications

This paper proposes a new common-mode feedback (CMFB) scheme for a fully differential operational transconductance amplifier (OTA) with enhanced linearity and large voltage swing. The main feature is that the common-mode feedback circuit output with push-pull scheme, which is parallel to the high-side PMOS and low-side NMOS of the output stage, to stabilize the common-mode state quickly and to maximize the output voltage swing. In addition, the third-order Butterworth low-pass transconductance–capacitance filter based on linear transformation techniques is also implemented in the TSMC 0.18 µm 1P6M CMOS process. The power dissipation of the designed transconductance cell is only 161 μW and the average power consumption of this chip is 1.4 mW under 1.2 V supply voltage. The filter core occupies a silicon area of 0.044 mm2.

Design and simulation of tunable low-pass Gm-C filter with 1 GHz cutoff frequency based on CMOS inventers for high speed telecommunication applications

A tunable low-pass Gm-C filter with 1 GHz cutoff frequency is presented. The core of this filter is a high frequency low voltage operational transconductance amplifier (OTA) in which CMOS inverters...

A design of an ultra low-power operational transconductance amplifier

This paper describes a design of an ultra low-power, low-voltage operational transconductance amplifier (OTA). A two stage OTA is implemented in 0.13 μ m SiGe BiCMOS technology. The OTA operates with all transistors active in subthreshold region. Under the typical operating conditions, circuit supply voltage is 0.5 V, supply current 150 nA and power consumption is 75 nW. Low-frequency gain is 53 dB, gain-bandwidth product (GBW) 350 kHz and phase margin 55°. -1 dB gain compression point is -7.4 dBm and output intercept point (OIP3) -21.5 dBm. OTA layout active chip area is 0.0014 mm2.

Design of a low voltage low power self-biased OTA using independent gate FinFET and PTM models

In this paper a low power low voltage operational transconductance amplifier has been designed using IGFinFET. Pseudo differential pair and self-biased techniques have been used for rail-to-rail input operation of the OTA. The new technique used in this paper has the advantage of bulk-drive technique for low voltage analog designs without bulk-drive limitations. Using double gate FinFET, one gate has been used to adjust threshold voltage, while the input signal is applied to the other gate. Optimum gm and ro have been investigated for different gate configurations of the IGFinFET. Power consumption of the IGFinFET circuit is lower than its CMOS counterpart and shows good merits for analog design in analog and mixed signal applications. DFC method has been used for frequency compensation that needs smaller capacitors. Predictive Technology Model (PTM) 20nm IGFinFET has been employed for HSPICE simulations. The designed amplifier has 39.27dB gain with 45.05° phase margin and unity-gain bandwidth of 8.26MHz with 37.75μW power dissipation from a single 0.5V power supply.

Low-voltage bulk-driven OTA with enhanced transconductance and dc gain

A novel low-voltage bulk-driven operational transconductance amplifier (OTA) with enhanced transconductance and dc gain is presented. Based on the current-recycling structure and partial positive feedback technique, the effective transconductance of the bulk-driven input stage is improved. Also, the bulk-biasing technique is proposed to the composite transistor to achieve the dc gain enhancement. The proposed OTA is designed to operate with a 1 V supply using the CSMC 0.18 µm CMOS process. Results confirm that the gain–bandwidth achieves 29.6 MHz and the dc gain is higher than 86.1 dB when the load is 25.0 pF. The figure of merit is above 370, which demonstrates the proposed OTA has a significant boost compared to prior arts.

Low-voltage high-gain large-capacitive-load amplifiers in 90-nm CMOS technology

Low-voltage and low-power multistage operational transconductance amplifiers with new and efficient gain boosting and frequency compensation schemes are proposed in this paper. The presented amplifiers are designed to drive large capacitive loads with small power consumption at low-voltage supplies. The compensation schemes exploit a single Miller capacitor and an active feedback to form the main negative feedback loops for pole splitting and two feedforward paths. The new gain boosting technique discussed here improves the dc gain with negligible effect on the frequency response. The analysis and design procedures are discussed and the performance enhancements of the amplifiers are verified. The proposed OTAs have been implemented in a standard 90-nm CMOS process and the post-layout simulation results are reported. The amplifiers consume 8.7μW and 8.1μW at 0.5-V supplies and achieve 12.65MHz and 2MHz gain-bandwidth products while driving 150-pF and 15-nF capacitive loads, respectively.

A High-Gain and Low-Noise 0.9 µW Operational Amplifier

A low-voltage, low-power, high-gain and low-noise operational transconductance amplifier (OTA) by modifying conventional one is presented and analyzed. Design strategies are discussed for minimizing noise and increasing gain. The simulation results show that the open loop gain is improved from 68 dB to 74 dB and the input referred noise is also reduced from 926 / nV Hz to 475 / nV Hz . This amplifier operates at 0.8 V power supply voltage with a power consumption of 0.9 µW. All the simulations are obtained by using Hspice tool with 0.18 µm CMOS TSMC parameters.

Low Power Operational Transconductance Amplifier (OTA) with Enhanced DC Gain and Slew-Rate

This paper presents a low-voltage differential operational transconductance amplifier (OTA) with enhanced DC gain and slew-rate. Based on the current mirror OTA topology, the optimization techniques are discussed in this work. The proposed structure achieves enhanced DC gain, unit gain frequency (UGF) and slew-rate (SR) with adding four devices. The design of the OTA is described with theory analysis. The OTA operates at the power supply of 1.8V. Simulation results for 0.18μm standard CMOS technology show that the DC gain increases from 60.6dB to 65dB, the UGF is optimized from 2.5MHz to 4.3MHz, the SR is enhanced from 0.88 V/μs to 4.8 V/μs with close power consumption dramatically.

A 0.4 V Bulk-Driven Amplifier for Low-Power Data Converter Applications

This paper presents the design of an ultra low-voltage (ULV) pseudo operational transconductance amplifier (P-OTA) that is able to operate with a single supply voltage as low as 0.4 V. The proposed circuit is based on the bulk-driven technique and use of cross-coupled self-cascode pairs that boosts the differential DC gain. The stability condition of this structure for the DC gain is considered by definition of two coefficients to cancel out a controllable percentage of the denominator. This expression for stability condition yield optimized value for the DC gain. Also, as the principle of operation of the proposed technique relies on matching conditions, Monte Carlo analyzes are considered to study of the behavior of the proposed circuit against mismatches. The designed P-OTA have a DC gain of 64 dB, 212 KHz unity gain bandwidth, 57phase margin that is loaded by 10 pF differential capacitive loads, while consume only 16 μW. Eventually, from the proposed P-OTA, a low-power Sample and Hold (S/H) circuit with sampling frequency of 10 KS/s has been designed and simulated. The correct functionality for this configuration is verified from –30℃ to 70℃. The simulated data presented is obtained using the HSPICE Environment and is valid for the 90 nm triple-well CMOS process.

Ultra Low Power Improved Differential Amplifier

In this paper, a low voltage and ultra low power operational transconductance amplifier (OTA) is presented. As will be shown, the transient response and open loop gain of the proposed OTA are improved using adaptive biasing and DC gain enhancement techniques. The contributions of the proposed OTA are ultra low power consumption (only 3.977 μw), low supply voltages (±0.6 V), high swing, high speed, and high gain. It can clearly be seen that for the proposed OTA, the gain of the differential half-circuit in the input stage (A d ), DC gain (A 0), gain bandwidth (GBW), and slew rate (SR) are increased, whereas the settling time (T S ) is decreased. The results of simulations done using 0.18 μm Silterra CMOS process technology and the measurement results are presented to validate and compare the advantages of this work and other related works.

Rail-to-rail input/output operational transconductance amplifier (OTA) with high CMRR and PSRR

This paper introduces a low-voltage CMOS operational transconductance amplifier (OTA) with rail-to-rail input/output stages. Input stage uses floating gate transistors to realize rail-to-rail scheme. However, this scheme gives rise to reduction in transconductance of the OTA. To increase transconductance (G m), an effective partial positive feedback is used. Class AB output stage is so designed that improves the gain, slew rate, common mode rejection ratio and maximum swing of the OTA. With ±0.75 v power supply, this OTA consumes the low power of 397.5 μw. G m variation of input stage is 0.004% for rail-to-rail (±0.75 v) variation in common mode input signals and reaches to 0.036% beyond the rail-to-rail range (±1 v) which is a superior result compared with previously reported works. As is proved by theoretical relations and simulation results, proposed auxiliary circuit for rail-to-rail operation results in both high CMRR due to fixing common source node of input differential pair and high linearity due to attenuation of input signals. Simulation results show that CMRR in DC frequency is 259.5 dB and HD3 is −46 dB for 2.15 vP-P differential output voltage signal with applying a 0.48 vP-P input signal at 1 MHz. Proposed OTA is simulated in TSMC 0.18 μm CMOS technology with Hspice. Monte Carlo simulation results are included to forecast mismatch effects after fabrication process.

A High-Swing OTA with wide Linearity for design of self-tunable linear resistor

Low power consumption, long battery life and portability are essential requirements of modern health monitoring products. Operational Transconductance Amplifier (OTA) operating in subthreshold region is an basic building block for low power health monitoring products design. An modified design of OTA which incorporates better linearity and increased output impedance has been discussed in this paper. The proposed OTA uses High-swing improved-Wilson current mirror for low power and low-frequency applications. The achieved linearity is about ± 1.9 volt and unity gain bandwidth (UGB) of 342.30 KHz at power supply of 0.9 volt which makes OTA to consume power in range of nanowatts. The proposed low voltage OTA implementation in design of self- tunable linear resistor has been presented in this paper. The circuit implementation has been done using standard 0.18 micron technology provided by TSMC on BSIM 3v3 level-53 model parameter and verified results through use of ELDO Simulator.

Low Voltage, Low Power, Inverter-Based Switched-Capacitor Delta-Sigma Modulator

An operational transconductance amplifier (OTA) is a major building block and consumes most of the power in switched-capacitor (SC) circuits, but it is difficult to design low-voltage OTAs in scaled CMOS technologies. Instead of using an OTA, this paper proposes an inverter-based SC circuit and its application to low-voltage, low-power delta-sigma (DeltaSigma) modulators. Detailed analysis and design optimizations are also provided. Three inverter-based DeltaSigma modulators are implemented for an implantable pacemaker, a CMOS image sensor, and an audio codec. The modulator-I for an implantable pacemaker achieves 65-dB peak-SNDR for 120-Hz bandwidth consuming 0.73 muW with 1.5 V supply. The modulator-II for a CMOS image sensor implemented with 320-channel parallel ADC architecture achieves 63-dB peak-SNDR for 8-kHz bandwidth consuming 5.6 muW for each channel with 1.2-V supply. The modulator-III for an audio codec achieves 81-dB peak-SNDR with 20-kHz bandwidth consuming 36 muW with 0.7-V supply. The prototype DeltaSigma modulators achieved high power efficiency maintaining sufficient performances for practical applications.

Low-distortion low-voltage operational transconductance amplifier

A new operational transconductance amplifier (OTA) is proposed, which is based on the flipped voltage follower and source degeneration techniques. The OTA is simulated in a standard TSMC 0.18 μm CMOS process with a 1.8 V supply voltage. The simulation results show that the total harmonic distortion of the proposed OTA is less than 1% up to 0.85 Vp-p.

A 0.8-V 0.25-mW Current-Mirror OTA With 160-MHz GBW in 0.18-&lt;formula formulatype="inline"&gt;&lt;tex&gt;$\mu{\hbox {m}}$&lt;/tex&gt;&lt;/formula&gt; CMOS

A low-voltage low-power CMOS operational transconductance amplifier (OTA) with near rail-to-rail output swing is presented in this brief. The proposed circuit is based on the current-mirror OTA topology. In addition, several circuit techniques are adopted to enhance the voltage gain. Simulated from a 0.8-V supply voltage, the proposed OTA achieves a 62-dB dc gain and a gain-bandwidth product of 160 MHz while driving a 2-pF load. The OTA is designed in a 0.18-mum CMOS process. The power consumption is 0.25 mW including the common-mode feedback circuit

Low-Voltage Super class AB CMOS OTA cells with very high slew rate and power efficiency

A simple technique to achieve low-voltage power-efficient class AB operational transconductance amplifiers (OTAs) is presented. It is based on the combination of class AB differential input stages and local common-mode feedback (LCMFB) which provides additional dynamic current boosting, increased gain-bandwidth product (GBW), and near-optimal current efficiency. LCMFB is applied to various class AB differential input stages, leading to different class AB OTA topologies. Three OTA realizations based on this technique have been fabricated in a 0.5-/spl mu/m CMOS technology. For an 80-pF load they show enhancement factors of slew rate and GBW of up to 280 and 3.6, respectively, compared to a conventional class A OTA with the same 10-/spl mu/A quiescent currents and /spl plusmn/1-V supply voltages. In addition, the overhead in terms of common-mode input range, output swing, silicon area, noise, and static power consumption, is minimal.