Low-voltage Multiplier Research Articles

Network design of ultra low voltage multiplier

A core optimality criterion peremnozhuvala signal, taking into account the amplitude of the output signal and limit the parameters of components and component level constant. Determined arguments based on sensitivity analysis circuit components. A comparison of the rate of convergence of search terms such optimal gradient method as gradient descent method and coordinate-wise descent. Made opt for the latter.Byblos. 4. Fig. 7 Table. 5.

Network design of ultra low voltage multiplier

The conditions of transition of the operating conditions of the traditional differential stage constructed MOSFET to conditions ultra low voltage mode as multiplier signal by the weighting coefficients of +1 and -1. The features of this multiplier circuitry signal constituting the basis of a programmable correlation filter. The main sources of multiplication errors are discussed and analytical assessment of their value is made. The conditions for conversion of the output signal, the product of multiplication. Practical schemes for output current-voltage converting are developed. Reference 5, figures 5.

Erratum to “A DC-100 GHz Active Frequency Doubler With a Low-Voltage Multiplier Core” [Sep 15 1963-1973

Presents corrections to the paper, “A DC-100 GHz active frequency doubler with a low-voltage multiplier core,” (Vera, L. and Long, J.R.) IEEE J. Solid-State Circuits, vol. 50, no. 9, pp. 1963–1973, Sep. 2015.

A mixed-signal GFSK demodulator for Bluetooth

A discrete-time mixed-signal Gaussian frequency-shift keying demodulator designed for a low intermediate frequency Bluetooth receiver performs FSK demodulation. Employing passive sampling and time-domain differentiation techniques, the demodulator performs quadrature demodulation while tolerating up to 200-kHz frequency offset. A distributed array of interleaved sampling circuits and a low-voltage multiplier allow both low-voltage operation and low power dissipation. Fabricated in a CMOS 0.25-/spl mu/m technology, the demodulator only dissipates 6 mW from a 2-V power supply.

A micropower low-voltage multiplier with reduced spurious switching

We describe a micropower 16/spl times/16-bit multiplier (18.8 /spl mu/W/MHz @1.1 V) for low-voltage power-critical low speed (/spl les/5 MHz) applications including hearing aids. We achieve the micropower operation by substantially reducing (by /spl sim/62% and /spl sim/79% compared to conventional 16/spl times/16-bit and 32/spl times/32-bit designs respectively) the spurious switching in the Adder Block in the multiplier. The approach taken is to use latches to synchronize the inputs to the adders in the Adder Block in a predetermined chronological sequence. The hardware penalty of the latches is small because the latches are integrated (as opposed to external latches) into the adder, termed the latch adder (LA). By means of the LAs and timing, the number of switchings (spurious and that for computation) is reduced from /spl sim/5.6 and /spl sim/10 per adder in the adder block in conventional 16/spl times/16-bit and 32/spl times/32-bit designs respectively to /spl sim/2 in our designs. Based on simulations and measurements on prototype ICs (0.35 /spl mu/m three metal dual poly CMOS process), we show that our 16/spl times/16-bit design dissipates /spl sim/32% less power, is /spl sim/20% slower but has /spl sim/20% better energy-delay-product (EDP) than conventional 16/spl times/16-bit multipliers. Our 32/spl times/32-bit design is estimated to dissipate /spl sim/53% less power, /spl sim/29% slower but is /spl sim/39% better EDP than the conventional general multiplier.