Low-voltage Metal-oxide Semiconductor Field-effect Transistors Research Articles

Failure Mechanism of Aluminum Diffusion in Low-Voltage Trench MOSFET With High Cell Density

In this paper, a low-voltage trench metal oxide semiconductor field effect transistor (MOSFET) with high cell density is researched on the process design. The experimental device pitch is reduced to 0.5 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\mu }\text{m}$ </tex-math></inline-formula> by three-dimensional (3-D) design of P plus region and self-aligned process, while the contact between silicon and metal is convex rather than the concave in conventional trench MOSFET. BV failure was founded because of the particularity of this structure and the failure is caused by the diffusion of aluminum (Al) into the drift region during the final alloy step in the metal forming process. This paper reveals the mechanism of Al / Silicon (Si) double diffusion and presents the refined surface metal film, which can suppress reverse diffusion and forward diffusion simultaneously. The risk of failure is reduced and functional devices are obtained by the application of the proposed surface metal film. Furthermore, it is recommended to use TiN layers in a total 50 nm as the barrier layer in the metallization process to provide a certain diffusion length and the fabricated device achieves a low specific on-resistance of 3.58 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{m}\Omega \cdot $ </tex-math></inline-formula> mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> with a corresponding breakdown voltage of 26.2 V eventually.

Temperature and SiO2/4H-SiC interface trap effects on the electrical characteristics of low breakdown voltage MOSFETs

The temperature and carrier-trapping effects on the electrical characteristics of a 4H silicon carbide (4H-SiC) metal–oxide–semiconductor field effect transistor (MOSFET) dimensioned for a low breakdown voltage (BVDS) are investigated. Firstly, the impact of the temperature is evaluated referring to a fresh device (defects-free). In particular, the threshold voltage (Vth), channel mobility (µch), and on-state resistance (RON) are calculated in the temperature range of 300 K to 500 K starting from the device current–voltage characteristics. A defective MOSFET is then considered. A combined model of defect energy levels inside the 4H-SiC bandgap (deep and tail centers) and oxide-fixed traps is taken into account referring to literature data. The simulation results show that the SiO2/4H-SiC interface traps act to increase RON, reduce µch, and increase the sensitivity of Vth with temperature. In more detail, the deep-level traps in the mid-gap have a limited effect in determining RON once the tail traps contributions have been introduced. Also, for gate biases greater than about 2Vth (i.e., VGS > 12 V) the increase of mobile carriers in the inversion layer leads to an increased screening of traps which enhances the MOSFET output current limiting the RON increase in particular at low temperatures. Finally, a high oxide-fixed trap density meaningfully influences Vth (negative shifting) and penalizes the device drain current over the whole explored voltage range.

The Topology of a High-Power Compound Transistor and Its Blocking Ability during Commutation

This article considers the problem of maintaining the blocking ability of high-power compound transistors in dynamic (commutation) modes. A compound transistor is an electrostatically controlled high-voltage induction thyristor serially connected to a low-voltage metal-oxide-semiconductor field effect transistor (MOSFET) that provides control along an isolated gate circuit. In addition, a major component of the compound circuit is a key threshold switch that supports floating potential mode in the gate circuit of the induction thyristor, when it is open, and fixes the gate to the common bus at locking. Emergency situations that render the compound transistor inoperable occur in the transient shutdown process and are associated with two main causes. The first one is the reduction in the negative locking voltage in the gate-source circuit of the induction thyristors below the level that ensures the closure of the space charge regions in its base region. The second cause is the rising voltage in the output circuit of the low-voltage MOSFET above the maximum permissible level. Mathematical criteria of maintaining the blocking ability of the high-power compound transistor are derived. It is shown that the reliable operation of the compound circuit requires reducing the reverse current amplitude in the gate circuit of the induction thyristor and parasitic inductance in the commutation loop, and harmonizing the parasitic capacitance values in the compound circuit elements. The suggested analytical model is used to consider methods of ensuring the blocking ability of compound thyristors for a number of practical circuit configurations with various threshold elements.

Implementation of Trench-based Power LDMOS and Low Voltage MOSFET on InGaAs

ABSTRACTIn this paper, we propose a design concept of integration of trench-based power and low voltage small signal metal-oxide-semiconductor field-effect transistors (MOSFETs) on high mobility InGaAs material. A high power dual-trench-gate (DTG) MOSFET and a low voltage MOSFET are implemented side by side in same InGaAs epitaxial layer using junction isolation technique. The high voltage DTG-MOSFET has two gates which are placed in oxide-filled trenches in the drift region. This structure provides a better trade-off between specific on-resistance (Ron−sp) and breakdown voltage (Vbr) due to the formation of dual conduction channels and enhancement in reduced-surface-field (RESURF) effect caused by folding of the drift region in the vertical direction. Further, simultaneous conduction of channels increases the drain current (ID) and transconductance (gm) leading to better cut-off frequency (ft) and maximum oscillation frequency (fmax). On the other hand, the gate of low voltage MOSFET is placed in an oxide trench to make two n-channels in the p-base. The parallel conduction of two channels gives substantial improvement in ID, peak gm, ft and fmax with good control over the short channel effects. Two-dimensional simulations are carried out to evaluate the performance of both high voltage and low voltage MOSFETs.

Simulation Model Development for Packaged Cascode Gallium Nitride Field-Effect Transistors

This paper presents a simple behavioral model with experimentally extracted parameters for packaged cascode gallium nitride (GaN) field-effect transistors (FETs). This study combined a level-1 metal–oxide–semiconductor field-effect transistor (MOSFET), a junction field-effect transistor (JFET), and a diode model to simulate a cascode GaN FET, in which a JFET was used to simulate a metal-insulator-semiconductor high-electron-mobility transistor (MIS-HEMT). Using the JFET to simulate the MIS-HEMT not only ensures that the curve fits an S-shape transfer characteristic but also enables the pinch-off voltages extracted from the threshold voltage of the MIS-HEMT to be used as a watershed to distinguish where the drop in parasitic capacitance occurs. Parameter extraction was based on static and dynamic characteristics, which involved simulating the behavior of the created GaN FET model and comparing the extracted parameters with experimental measurements to demonstrate the accuracy of the simulation program with an integrated circuit emphasis (SPICE) model. Cascode capacitance was analyzed and verified through experimental measurements and SPICE simulations. The analysis revealed that the capacitance of low-voltage MOSFETs plays a critical role in increasing the overall capacitance of cascode GaN FETs. The turn-off resistance mechanism effectively described the leakage current, and a double-pulse tester was used to evaluate the switching performance of the fabricated cascode GaN FET. LTspice simulation software was adopted to compare the experimental switching results. Overall, the simulation results were strongly in agreement with the experimental results.

New series half-bridge converters with the balance input split capacitor voltages

This article presents a new dc/dc converter to perform the main functions of zero voltage switching (ZWS), low converter size, high switching frequency and low-voltage stress. Metal–oxide–semiconductor field-effect transistors (MOSFETs) with high switching frequency are used to reduce the converter size and increase circuit efficiency. To overcome low-voltage stress and high turn-on resistance of MOSFETs, the series half-bridge topology is adopted in the proposed converter. Hence, the low-voltage stress MOSFETs can be used for medium-input voltage applications. The asymmetric pulse-width modulation is used to generate the gating signals and achieve the ZWS. On the secondary side, the parallel connection of two diode rectifiers is adopted to reduce the current rating of passive components. On the primary side, the series connection of two transformers is used to balance two output inductor currents. Two flying capacitors are used to automatically balance the input split capacitor voltages. Finally, experiments with 1000 W rated power are performed to verify the theoretical analysis and the effectiveness of proposed converter.

Modified current‐fed full‐bridge isolated power factor correction converter with low‐voltage stress

One drawback of the conventional current-fed full-bridge (CFFB) power factor correction (PFC) converters is extremely high-voltage spikes on metal oxide semiconductor field effect transistors (MOSFETs), which cause many problems such as high-voltage high-cost devices used, unreliability and burdensome magnetising components imposed. To overcome above shortcomings, a new isolated CFFB PFC converter featuring efficiency improvement, high input current quality and good common mode (CM) noise performance is proposed in this study. The voltage spikes are effectively eliminated by using a non-dissipative clamping structure resulting of no-loss consumption and low-voltage MOSFETs used. Additionally, to evaluate the conducted electromagnetic interference behaviour, the differential mode loop and CM loop models are also presented. Two testing hardware systems with 180–240 V input, 380 V/1 kW output of the conventional CFFB PFC and proposed PFC were built and inspected to compare their performances. The experimental results showed that the proposed topology completely eliminated the voltage spike on MOSFETs. The efficiency was largely improved by utilising of high-performance MOSFETs. In consequence, the experimental results reveal the preponderance of the proposed PFC converter to the previous researches on this topic.

Zero‐voltage switching current‐fed flyback converter for power factor correction application

Previous research on flyback power factor correction (PFC) converters exposes some inherent shortcomings, such as high-voltage spike on the metal oxide semiconductor field effect transistor (MOSFET), frequency variation, pulsating input current and hard switching operation. This study presents a new topology for PFC applications named zero-voltage switching (ZVS) current-fed flyback converter to not only achieve spike-free voltage, ZVS on the MOSFETs, but also improve the input current quality. By utilising quasi-z-source configuration, the voltage spikes on the MOSFET are effectively eliminated using only a capacitive clamper, resulting in no-loss consumption. Low-voltage MOSFETs with low on-resistance Rds (on) are used to improve the efficiency. In addition, by taking advantage of the average current mode control with the continuous conduction mode operation, the input current perfectly tracks the input voltage. To demonstrate the circuit's feasibility, a 100–140 V input, 28 V/5 A output laboratory prototype was built. The experimental results showed that the proposed topology completely eliminated the voltage spikes on the MOSFETs. The efficiency was improved using low Rds (on) MOSFETs, and ZVS was achieved. In summary, the proposed topology meets the high efficiency and high-input current quality requirements.

Source switching circuit with low‐gate‐driving loss in high‐voltage buck light emitting diode driver

Source switching circuit with low-gate-driving loss in high-voltage buck light emitting diode (LED) driver is proposed in this study. Source switching circuit comprises of a high-voltage power metal-oxide semiconductor field-effect transistor (MOSFET) (HVMOS) and a low-voltage power MOSFET (LVMOS) in series, a capacitor and a Zener diode. By switching the HVMOS by different source voltage and constant gate voltage, it recycles gate charges of HVMOS to reduce gate-driving loss. Gate charges are recycled in the capacitor when LVMOS is turning off, and can be reused when LVMOS is turning on. This circuit also provides a new power feeding route for control chip, and power consumption is relatively low on the proposed route. The power feeding route also improves power efficiency. With a 12 W LED load, the experiment shows that the efficiency of the proposed driving circuit is improved by 3.7% with 156 V input voltage and 4.8% with 326 V input voltage compared with the converter using single HVMOS.

Model requirements for simulation of low-voltage MOSFET in automotive applications

This paper focuses on the modeling of low-voltage automotive power electronic circuits to obtain accurate system simulation, including estimation of losses. The aim is to compare several metal-oxide semiconductor field-effect transistor (MOSFET) models to find out which can be used for low-voltage, high-current automotive converter simulations. As these models are intended for system simulation, only analytical models are addressed as they may be implemented into any circuit simulator. The different modes of operation of the switches are described (commutation, synchronous rectification, avalanche...), and several models of the power MOSFET transistor, allowing for simulation in these modes, are presented. Special care is given to the parameter extraction methods and to the interconnection model of the commutation cell. The four test circuits used to identify the low-voltage power MOSFET model parameters are presented. Comparison between simulations and measurements obtained with a calorimeter are then detailed. This measurement method is accurate and offers a simple way to prove the quality of simulation results. It is shown that the parameter identification is of major concern to achieve high accuracy, as classical Spice models can give good results, providing the model parameters are correctly set