Low-voltage Low-power Applications Research Articles

A 1.2 V, 92 dB Dynamic-Range Delta-Sigma Modulator Based on an Output Swing-Enhanced Gain-Boost Inverter

This article presents a third-order, feedforward, single-bit Delta-Sigma analog-to-digital modulator (DSM) based on an output swing-enhanced gain-boost inverter for low-voltage low-power applications such as wearable devices, mobile health, and the Internet of Things (IoTs). The proposed output swing-enhanced structure addresses the output-swing reduction in the conventional structure while achieving high DC gain and large output swing simultaneously. Implemented in a 180 nm CMOS process, the entire chip is comprised of a delta-sigma modulator, an oscillator, and a current reference. It achieves 86.1 dB peak SNR and 92 dB dynamic range (DR) with 1.95 kHz signal bandwidth. The whole chip dissipates 54.5 μW, leading to a 167.6 dB Schreier Figure of Merit (FoMs).

Variable Pulse Density Modulation for a Buck-Type Three-Switch Current Source Rectifier

With flexible voltage adjustment without an intermediate DC/DC converter, short-circuit protection, self-starting, high reliability, and three-phase current source rectifiers (CSRs) are being widely used in high-power medium-voltage applications and low-power low-voltage applications. Modulation methods significantly affect the performance of CSRs and can be categorized into offline modulation methods, such as selective harmonic elimination/compensation pulse width modulation (SHE/SHC-PWM), and online modulation methods, such as space vector pulse width modulation (SV-PWM) and carrier-based pulse width modulation (CB-PWM). The SHE/SHC-PWM is popular in high-power medium-voltage applications that do not require a fast dynamic response and have a low switching frequency. Online modulations considerably improve the dynamic response and performance of the CSR; however, high computational power, such as digital signal processors (DSPs), is required at higher switching frequencies, leading to greater system complexity and cost. In this paper, an offline method based on variable pulse density modulation (VPDM) of power switches to synthesize sinusoidal input currents and control power transfer with pulse width modulation (PWM) is proposed. The proposed modulation is applicable to the three-switch buck-type VIENNA rectifier, showing the capability of improving the input current total harmonic distortion (THD) with respect to the SHE-PWM and is comparable to online modulations at a sufficiently high switching frequency. The simulation and experimental results basically prove the feasibility of the proposed modulation.

High Efficiency Over 70% at 3.6-GHz InAlN/GaN HEMT Fabricated by Gate Recess and Oxidation Process for Low-Voltage RF Applications

In this work, high-efficiency InAlN/GaN high electron mobility transistor (HEMT) is fabricated by recess and oxidation process under the gate (RAO) for low-voltage RF applications. Compared with conventional HEMT fabricated on the same heterojunction, RAO-HEMT exhibits a significant decrease in gate leakage, attributed to the thin oxide layer formed around and under the gate as well as adjustment of the location of the peak electric field and confinement of the strong electric field in the oxide. Due to the alleviated electric field as well as adoption of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{N}_{{2}}\text{O}$ </tex-math></inline-formula> for plasma treatment, suppressed RF dispersion including the extremely low current collapse and negligible knee voltage walkout is obtained for RAO-HEMT. Although RAO-HEMT delivers lower saturation current as the result of the partial oxidation of the barrier under the gate, it shows a similar ON-resistance to conventional HEMT, which contributes to the reduction in knee voltage. Besides, higher <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${f}_{T}/{f}_{\text {MAX}}$ </tex-math></inline-formula> is achieved for RAO-HEMT, as the result of the higher dc transconductance and suppressed RF transconductance collapse as well as larger output resistance. Eventually, benefiting from the improvement in gate leakage, RF dispersion, knee voltage, and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${f}_{\text {MAX}}$ </tex-math></inline-formula> by RAO, RAO-HEMT delivers both higher power-added-efficiency (PAE) and output power ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${P}_{\text {OUT}}$ </tex-math></inline-formula> ) than conventional HEMT. At 3.6 GHz, RAO-HEMT provides a high PAE of 71% (74%) at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{{\text {DS}}}$ </tex-math></inline-formula> of 6 V (9 V), which performs better than most of the existing Si, GaAs, or GaN RF devices in PAE, revealing the great potential of InAlN/GaN RAO-HEMT in low-voltage low-power consumption RF applications.

0.5 V, nW-Range Universal Filter Based on Multiple-Input Transconductor for Biosignals Processing.

This paper demonstrates the advantages of the multiple-input transconductor (MI-Gm) in filter application, in terms of topology simplification, increasing filter functions, and minimizing the count of needed active blocks and their consumed power. Further, the filter enjoys high input impedance, uses three MI-Gms and two grounded capacitors, and it offers both inverting and non-inverting versions of low-pass (LPF), high-pass (HPF), band-pass (BPF), band-stop (BS) and all-pass (AP) functions. The filter operates under a supply voltage of 0.5 V and consumes 37 nW, hence it is suitable for extremely low-voltage low-power applications like biosignals processing. The circuit was designed in a Cadence environment using 180 nm CMOS technology from Taiwan Semiconductor Manufacturing Company (TSMC). The post-layout simulation results, including Monte Carlo and process, voltage, temperature (PVT) corners for the proposed filter correlate well with the theoretical results that confirm attractive features of the developed filter based on MI-Gm.

1 V, 20 nW True RMS to DC Converter based on Third Order Dynamic Translinear Loop

This paper presents a novel current-mode true RMS–DC converter based on the dynamic translinear principle. The converter is designed using a third-order translinear loop, resulting in a very compact and simple circuit. The proposed circuit is designed in 65 nm CMOS technology, operates with 1 V power supply, has only 14 transistors and performs satisfactorily over a wide input current range of 300 nA–950 nA and for a frequency range of 600 Hz–650 kHz for a capacitance value of 10 nF. The frequency range of operation can be tuned by varying the external off chip capacitor and the bias current. The circuit consumes 20 nW static power, 1.6 μW maximum dynamic power and offers the lowest FOM among the other RMS–DC converter circuits presented in the literature. Comprehensive mathematical analysis along with the post layout simulation results confirm the validity of the proposed circuit. To test the use of converter in real world scenarios, the proposed converter is introduced within a typical ECG detection system and the results show that the circuit is an attractive solution for RMS–DC conversion in low-voltage low-power applications.

Gate-All-Around GaN Nanowire FET as a Potential Transistor at 5 nm Technology for Low-Power Low-Voltage Applications

In this paper, design and parameter optimization for the performance analysis of a Gate-All-Around GaN Nanowire Field Effect Transistor (GAA GaN NWFET) has been carried out based on the various quantum ballistic simulation models. The simulation results show a novel way to change the device mode of operation from Depletion-mode (D-Mode) to Enhancement mode (E-Mode) and vice-versa by varying the thickness of the nanowire channel ([Formula: see text], which has not been reported yet to the best of our knowledge. Also, the paper reveals novel approaches (i) threshold voltage ([Formula: see text] tuning using metal contact length ([Formula: see text], (ii) threshold voltage ([Formula: see text] tuning using metal electrode work functions ([Formula: see text] and (iii) threshold voltage ([Formula: see text] tuning using metal contact width ([Formula: see text]. The device has an [Formula: see text]/[Formula: see text] ratio of 105, suppressed off-state leakage in the range of 10[Formula: see text]–10[Formula: see text]A. The simulation work has been carried out on a commercially available ATLAS device simulator from Silvaco.

An ultra-low power high-precision logarithmic-curvature compensated all-CMOS voltage reference in 65 nm CMOS

In this paper, a low-complexity resistorless high-precision sub-1 V MOSFET-only voltage reference is presented. To obtain an accurate output, a curvature-compensation technique is used, canceling its logarithmic temperature dependence regardless of the value of the mobility temperature exponent $$(\gamma )$$ . The circuit is realized in 65 nm CMOS technology and yields an output voltage of 574 mV, a temperature coefficient of 3.5 $$\frac{{{\text{ppm}}}}{{^\circ {\text{C}}}}$$ in the range of − 50 to 150 °C, a power supply rejection ratio (PSRR) of − 103 dB at 100 Hz, a line sensitivity of $$6\,\frac{{\upmu {\text{V}}}}{{\text{V}}}$$ in the supply voltage range of 1.3–3 V, a power dissipation of 650nW at 1.3 V supply, and an output noise of 1.7 $${\mu V}/\sqrt {{\text{Hz}}}$$ at 100 Hz. The total active area of the design is 0.03 mm2. This voltage reference is suitable for low-power low-voltage applications which also require high precision.

Frequency-Compensated Bulk-Driven TIA Suitable for Low-Voltage Low-Power Applications

The importance of a transimpedance amplifier in an optical transceiver is very well known. In this paper, a novel CMOS design of the bulk-driven transimpedance amplifier (BD-TIA) is given where the bridge-shunt peaking-based frequency compensation technique is exploited to improve frequency response. A pre-existing active inductor has been used for the same. The electrical characteristics and functioning of this inductor simulator make it a suitable alternative to both floating and grounded spiral inductors. In order to verify the workability of the proposed circuit, it has been simulated with TSMC CMOS 0.18[Formula: see text][Formula: see text]m process parameters. The proposed circuit is useful in low-voltage low-power VLSI applications as it uses a single supply of 0.75[Formula: see text]V. The power consumption of BD-TIA is very low, being 0.37[Formula: see text]mW, because a standard MOSFET has been replaced by a bulk-driven MOSFET (BDMOS), while the 3-dB bandwidth is observed to be 4.5[Formula: see text]GHz. The mathematical investigation and small signal analysis show that the simulation results are in good agreement.

A Redundancy Eliminated Flip-Flop in 28 nm for Low-Voltage Low-Power Applications

A redundancy eliminated flip-flop (REFF) is presented in 28-nm LP process, targeting wide-range voltage scalability (1–0.3 V). The REFF removes redundant clock transitions to reduce dynamic power consumption and further eliminates redundant transistors with topological and logical methods while keeping it fully static and contention free. The measured power is reduced by 70%/59% with 0%/10% activity at 1-V compared to the TGFF, and 100 dies from five corners were functional down to 0.28 V.

An Improved Adjustable Modulation Strategy for Three-Level NPC Inverters Considering Dynamic Loading Applications

Three-level neutral-point-clamped (NPC) inverters are being widely adopted in low-voltage low-power applications. For an intended application, the modulation strategy and the operating conditions are the two key factors that highly influence the major performance indices of the NPC inverter, such as efficiency, harmonic distortion, and voltage oscillations at neutral point (NP). Considering dynamic loading applications where the operating point varies significantly, this paper proposes an improved adjustable pulsewidth modulation (PWM) strategy for a three-level NPC inverter that can alter its modulation pattern to meet desired performance objectives for the full operation range. It has been shown that by varying two control parameters namely discontinuity control parameter and bias control parameter, the proposed modulation strategy changes its pattern between the most efficient generalized discontinuous PWM to NP oscillations-free partial dipolar PWM strategy. Additionally, to obtain a tradeoff between the performance parameters-efficiency, NP oscillations, and waveform quality-The proposed strategy has the ability to settle at the intermediate modulation patterns by transforming into a hybrid modulation signal. Furthermore, considering NP voltage unbalance mitigation as major technical challenge in adjustable modulation strategy, a voltage unbalance compensator that exhibits satisfactory balancing performance for the entire variations of modulation patterns and operating conditions has also been presented. The performance of the proposed modulation strategy in conjunction with voltage unbalance compensator has been evaluated in simulation by widely varying the speed and load of induction motor, and verified in experimentation.

0.4 V fully differential current conveyor using multiple-input bulk-driven MOST technique

This paper presents a new ultra-low voltage ultra-low power fully differential current conveyor (FDCCII) which is suitable for extremely low-voltage low-power analog signal circuit applications. Thanks to multiple-input bulk-driven MOS transistor technique, the proposed structure employs two differential pairs which offer low complexity and low power consumption. The bulk-driven MOS technique based circuit also provides rail-to-rail input common-mode range of proposed circuit. To prove the workability of the proposed FDCCII, the circuit has been used to realize summing/subtracting amplifier as design examples. The performances of the proposed FDCCII and design examples are demonstrated through PSPICE simulations using a 0.18 μm TSMC n-well CMOS process with 0.4 V supply voltage.

0.5 V Universal Filter Based on Multiple-Input FDDAs

This brief presents a universal filter based on multiple-input fully differential difference amplifier (FDDA) that is suitable for extremely low-power low-voltage applications. The filter employs three FDDAs, eight resistors, four capacitors and can provide low-pass, band-pass, high-pass, band-stop and all-pass voltage responses. Thanks to the utilization of the multiple-input MOS transistor technique, one differential pair with an arbitrary number of inputs is required for constructing the FDDA. Therefore, unlike the previously published FDDA-based universal filters, the proposed filter has the simplest CMOS structure with less power consumption than those already published in the literature. The filter operates with 0.5 V, consumes 740 nW and exhibits rail-to-rail input common mode range. The dynamic range of the BP filter is 73 dB for 1% third intermodulation distortion. The circuit was designed in Cadence/Spectre environment using the TSMC 0.18 µm CMOS process design kit, and the simulation results confirm the advantages of the proposed filter.

A compact power-efficient 0.5 V fully differential difference amplifier

This brief presents a novel compact CMOS Fully Differential Difference Amplifier (FDDA) structure suitable for extremely low-voltage low-power applications. Unlike the conventional FB-DDAs that employ two differential pairs, the proposed structure employs one differential pair of multiple-input bulk-driven MOS transistor (MI-BD MOST) that results in reduced count of current branches and, consequently, of power consumption. The proposed FDDA has the simplest CMOS structure presented in the literature so far. Furthermore, while the voltage supply is 0.5 V and the power consumption is 246.6 nW the circuit enjoys rail-to-rail input common mode range (ICMR), high common mode rejection ratio (CMRR) of 100.3 dB @ DC, power supply rejection ratio (PSRR) of 127.8 dB@ DC, voltage gain of 61.4 dB and gain bandwidth product of 6.98 kHz for 30 pF capacitive load. The total harmonic distortion (THD) is less than 0.08% for 500 mV/1 kHz input sine wave signal. The circuit was designed and simulated in Cadence/Spectre environment using 0.18 µm CMOS process from TSMC.

A novel low offset low power CMOS dynamic comparator

This paper presents a novel fully dynamic double tail dynamic comparator that exhibits low offset voltage compared to the traditional dynamic comparators. This paper comprises a novel fully differential double tail high performance comparator suitable for low-voltage low-power applications. A fully differential double tail comparator has been intended to meet the necessity of low offset voltage with optimum power with relatively high speed. In this paper expression for the calculation of the offset voltage and delay of the proposed comparator are derived. These expressions corroborate previously stated results with analytical support as well as providing useful insight for the design of dynamic comparator by analyzing the influence of each transistor pair individually. Transistor mismatch analysis is carried out for offset voltage to fully explore the trade-offs in the design of comparator. The results are validated by Monte Carlo simulations and corner analysis. It is shown that in proposed comparator offset voltage is significantly reduced with optimum power. Authors have proposed novel architecture of dynamic voltage comparator which is differential and double tail and verified the architecture by simulation in 180 nm CMOS technology with ?ý0.9 V supply. The Post-layout simulation results illustrates that a comparator designed with the proposed techniques is 45% faster, and 30% more power efficient and exhibits 91% low offset as compared with conventional comparator, which is the fastest among the conventional comparators.

High bandwidth transimpedance amplifier using FGMOS for low voltage operation

In this paper a novel CMOS design of transimpedance amplifier (TIA) suitable for low-voltage low-power application is presented. A floating gate metal oxide semiconductor (FGMOS) transistor is used here in common source configuration to provide active feedback along with a standard MOSFET which acts as input stage of the circuit. Main intend of this work is to minimize supply requirement with increased linearity. The circuit of TIA presented in this paper works only at 1V supply with small power consumption of 1.1mW. One of the popular frequency compensation techniques is shunt peaking technique. It is employed here to extend bandwidth. The transimpedance output and − 3dB bandwidth of proposed circuit are 37.7dBOhms and 13.5GHz, respectively. The input impedance and transfer function is evaluated using mathematical analysis and small signal model of circuit. This is observed that results are improved as compared to well known regulated common gate (RC-G) amplifier.

Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications

Logic compatible gain cell (GC)-embedded DRAM (eDRAM) arrays are considered an alternative to SRAM due to their small size, nonratioed operation, low static leakage, and two-port functionality. However, traditional GC-eDRAM implementations require boosted control signals in order to write full voltage levels to the cell to reduce the refresh rate and shorten access times. These boosted levels require either an extra power supply or on-chip charge pumps, as well as nontrivial level shifting and toleration of high voltage levels. In this brief, we present a novel, logic compatible, 3T GC-eDRAM bitcell that operates with a single-supply voltage and provides superior write capability to the conventional GC structures. The proposed circuit is demonstrated with a 2-kb memory macro that was designed and fabricated in a mature 0.18- $\mu $ m CMOS process, targeted at low-power, energy-efficient applications. The test array is powered with a single supply of 900 mV, showing a 0.8-ms worst case retention time, a 1.3-ns write-access time, and a 2.4-pW/bit retention power. The proposed topology provides a bitcell area reduction of 43%, as compared with a redrawn 6-transistor SRAM in the same technology, and an overall macro area reduction of 67% including peripherals.

A New Trans-admittance-Mode Biquad Filter Suitable for Low Voltage Operation

The trans-admittance-mode (TAM) might act as a transforming bridge for voltage-mode to current-mode conversion. In this study a new low voltage operated electronically tunable TAM biquad filter structure realizing all the seven standard filtering functions namely; low-pass (LP), band-pass (BP), high-pass (HP), regular-notch (RN), low-pass-notch (LPN), high-pass-notch (HPN) and all-pass (AP) from the same configuration through appropriate selection of voltage inputs is presented. The proposed circuit structure comprises of three current conveyor trans-conductance amplifiers (CCTAs). Moreover, the new biquad filter structure still enjoys (i) realizations neither require inverted nor scaled voltage input(s), (ii) the employment of two grounded capacitors (Ideal for IC implementation and attractive for absorbing shunt parasitic capacitances), (iii) the pole frequency can be tuned electronically, (iv) possesses low incremental active and passive sensitivity performance and useful in low-voltage low-power applications. PSPICE simulation results using 0.25μm TSMC CMOS parameters verify the theoretical analysis.

Design and modeling of high-resolution multibit log-domain $$\Delta \Sigma$$ Δ Σ modulators

Log-domain Delta-Sigma ( $$\Delta \Sigma$$ Δ Σ ) modulators are attractive for implementing analog-to-digital (A/D) converters (ADCs) targeting low-power low-voltage applications. Previously reported log-domain $$\Delta \Sigma$$ Δ Σ modulators were limited to 1-bit quantization and, hence, could not benefit from the advantages associated with multibit quantization (namely, reduced in-band quantization noise, and increased modulator stability). Unlike classical $$\Delta \Sigma$$ Δ Σ modulators, directly extending a log-domain $$\Delta \Sigma$$ Δ Σ modulator with a 1-bit quantizer to a log-domain $$\Delta \Sigma$$ Δ Σ modulator with a multibit quantizer is challenging, in terms of CMOS circuit implementation. Additionally, the realization of log-domain $$\Delta \Sigma$$ Δ Σ modulators targeting high-resolution applications necessitates minimization of distortion and noise in the log-domain loop-filter. This paper discusses the challenges of multibit quantization and digital-to-analog (D/A) conversion in the log-domain, and presents a novel multibit log-domain $$\Delta \Sigma$$ Δ Σ modulator, practical for CMOS implementation. SIMULINK models of log-domain $$\Delta \Sigma$$ Δ Σ modulator circuits are proposed, and the effects of various circuit non-idealities are investigated, including the effects of log-domain compression---expansion mismatch. Furthermore, this paper proposes novel low-distortion log-domain analog blocks suitable for high-resolution analog-to-digital (A/D) conversion applications. Circuit simulation results of a proposed third-order 3-bit class AB log-domain $$\Delta \Sigma$$ Δ Σ loop-filter demonstrate 10.4-bit signal-to-noise-and-distortion-ratio (SNDR) over a 10 kHz bandwidth with a $$0.84\,V_{pp}$$ 0.84 V p p differential signal input, while operating from a 0.8 V supply and consuming a total power of $$35.5\,\upmu \hbox {W}.$$ 35.5 μ W .

Partially Depleted SOI Versus Deep N-Well Protected Bulk-Si MOSFETs: A High-Temperature RF Study for Low-Voltage Low-Power Applications

The design options for low-voltage low-power (LVLP) applications are not limited to the circuit level, but it should start with the right choice of device technology and architecture. This paper presents a comparative study between a special structure of bulk MOSFET called the deep n-well protected device and the partially depleted silicon-on-insulator device. This paper shows the advantage of each device for different operation schemes while concentrating on the RF behavior for very low bias conditions. The study shows the lower limit for the bias conditions for the devices to correctly operate in RF. It also presents the effect of high temperature on the key figures of merit for dc and RF operations for high-performance and LVLP operation regimes.

Introduction to the special issue “2011 International Analog VLSI Workshop”

This special issue of the SPRINGER Journal of Analog Integrated Circuits and Signal Processing is published with 9 papers selected from presented papers at the 2011 International Analog VLSI Workshop (AVLSIWS2012). The conference was held in Bali, Indonesia on October 2–4, 2011. This conference was organized by the Research Committee on Electronic Circuits of the Institute of Electrical Engineers of Japan (IEEJ) in cooperation with the Bandung Institute of Technology. The purpose of the conference is to exchange information, ideas and recent research results on analog VLSI circuits and their applications. The first 4 papers are related to power supply and power management circuits. The first paper by Eiichi et al. presents a low power wake-up receiver with CMOS operating in the subthreshold current region. The paper is focusing on the development of low-power envelope detector, highgain amplifier and PWM CDR. The fabricated detector and high-gain amplifier only consumes 6.8 lW from a 1.5-V power supply voltage. The second paper by Zachary et al. presents a design of boost regulator for energy harvesting applications. The proposed circuit uses two different control schemes for startup and steady-state operation. At the startup operation, a fixed-frequency oscillator is used to increase the output voltage up to sufficient level for steady state operation. At the steady state operation, a constant-on-time hysteretic control system is used to increase the efficiency. The proposed circuit can start up with an input voltage of 240 mV and achieve a maximum efficiency of 97 %. Toshiko discusses the design concepts of wireless sensor network system constructed with autonomous sensing nodes, which operates at extremely low power levels. The paper reviews a structure health-monitoring system, monitoring methodology with a focus on quantitative measurement accuracy, and issues of node synchronized sampling, multi-layer cluster, node distance and integrated sensor node module. Design example using a Wheatstone bridge strain sensor is demonstrated. Bin Shao presents a design of buck converter utilizing a low quiescent current PFM switching method. The proposed method improves the efficiency of the converter at a light load condition. An adaptive accurate zero-cross comparator for discontinuous mode and very low quiescent current circuit technique in skip period operation are introduced. The proposed circuit improves the efficiency at a 5-V input, 3-V output and 10-mA load by 60 % compared to a conventional circuit with PWM switching method. The fifth paper by Antaryami et al. presents a novel four quadrant voltage multiplier using bulk input for low-power low-voltage applications. The proposed circuit uses a current mirror operated in weak inversion region as an input stage where the bulk of MOSFETs are used as input terminals. The proposed circuit achieves a 5.8 % THD for 80 mV input voltage amplitude under 0.5 V power supply voltage. The power consumption of the proposed circuit is 714.3 nW. A. Yasuda Faculty of Science and Engineering, Department of Electrical and Electronics Engineering, Hosei University, 3-7-2 Kajino-cho, Koganei-city, Tokyo 184-8584, Japan e-mail: yasuda@hosei.ac.jp