Low-voltage Low-dropout Regulator Research Articles

Low Voltage Low Dropout Regulator with Current Splitting Technique

Integrated regulators are used for power management in modern portable devices. There are many primary regulators and post regulators which converts high dc voltages, but they are unable to work on low voltage with low quiescent current. A low-voltage low-dropout regulator with current splitting technique is proposed which converts a low-voltage of 1V to an output of 0.6 V with 90 nm CMOS technology. A power noise cancellation mechanism is formed at rail-to-rail output stage of error amplifier (EA) which minimizes the size of power MOS transistor. A transient accelerator (TA) is formed to reuse the part of EA which achieves high current efficiency. Keywords: Fast Transient Response, High Power Supply Rejection, Low Dropout (LDO) Regulator, Low Input Voltage

VLSI IMPLEMENTATION OF A PROGRAMMABLE LOW DROP-OUT VOLTAGE REGULATOR

LDO voltage regulators compose a small subset of the power supply arena. Low-drop-out (LDO) voltage regulators are used in analog applications that generally require low noise and high accuracy power rails. Voltage regulators provide a constant voltage supply rail under certain loading conditions. Circuits that are not performing tasks are temporarily turned off lowering the overall power consumption. The LDO voltage regulator, therefore, must respond quickly to system demands and power up connected circuits. To motivate new aspect of power management towards a design of a low drop-out voltage regulator that fulfils the present industry requirements as well as the upcoming demands of the future, it becomes necessary to design the LDO regulator which gives overall performance. A low-voltage low-dropout regulator that uses an Vdd of 1 V to an output of 0.8–0.74 V, with 32-nm CMOS technology is proposed. By scaling down the technology, we can get lower power consumption. More emphasis is given on the compactness and low drop-out voltage. The latest power management unit concept inside the system on chip (Soc) scheme inspires the digital control potential for the design of a novel LDO regulator. A simple operational transconductance amplifier is used as the error amplifier (EA), with a current splitting technique which is able to boost the gain. In the rail-to-rail output stage of the EA, a power noise cancellation mechanism is adopted. Programmability is added by applying two external control signals. These advantages allow the proposed LDO regulator to achieve a 60-mV output variation for low load transient, area efficient architecture with low power consumption.

English

Low drop-out regulators (LDO) are circuits which are designed to provide a stable and specified DC voltage, with a low input-to-output voltage difference. To get a new approach of power management towards a design of a low drop-out voltage regulator that provides a modern system on chip (SoC) solution and fulfils the present commercial requirements as well as the upcoming demands of the future, it becomes necessary to design the LDO regulator which gives all-rounder performance. This LDO should beware of various performance matrices. Also future nm technology offers more advantages in achieving most of the performance specifications. This paper presents a lowvoltage low-dropout regulator that is capable of providing regulated output with small drop-out voltage and offers a range of different voltages, by using two binary-input control signals. The entire circuit has been designed in a 32 nm technology and simulated using Microwind tool. This design utilizes a cascode current amplifier used with a high threshold PMOS operated in the sub-threshold region, which is responsible to boost the gain and yield the desired output voltage.

Design of a Low-Voltage Low-Dropout Regulator

A low-voltage low-dropout (LDO) regulator that converts an input of 1 V to an output of 0.85-0.5 V, with 90-nm CMOS technology is proposed. A simple symmetric operational transconductance amplifier is used as the error amplifier (EA), with a current splitting technique adopted to boost the gain. This also enhances the closed-loop bandwidth of the LDO regulator. In the rail-to-rail output stage of the EA, a power noise cancellation mechanism is formed, minimizing the size of the power MOS transistor. Furthermore, a fast responding transient accelerator is designed through the reuse of parts of the EA. These advantages allow the proposed LDO regulator to operate over a wide range of operating conditions while achieving 99.94% current efficiency, a 28-mV output variation for a 0-100 mA load transient, and a power supply rejection of roughly 50 dB over 0-100 kHz. The area of the proposed LDO regulator is only 0.0041 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , because of the compact architecture.

Design of an Op-Amp Based Low Voltage Low Dropout Regulator Using 180nm CMOS Technology

This paper describes the designing of a Low Voltage, Low Dropout (LVLD) Regulator with fast self-reacting (FSR) technique in 0.18 μm CMOS process. The LVLD Regulator provides 1.2 V regulated output voltage. The design procedure includes pass transistor, error amplifier, fast self-reacting path and bandgap reference (BGR) circuit. The pass transistor is designed for a desired minimum dropout voltage. The error amplifier has been developed with a gain of 65 dB and UGB of atleast 1 MHz. Curvature compensated CMOS BGR with 1.8 V supply has been developed to produce 0.8 V output voltage with better temperature coefficient.

A Low-Power High Accuracy Over Current Protection Circuit for Low Dropout Regulator

In this paper, a low power current protection circuit implemented in a low dropout regulator (LDO) is presented. The proposed circuit, designed in a 0.35 μm CMOS process, provides a precise limiting current as well as holding current with low dependency on both supply voltage and regulator output voltage. The experimental results showed that the proposed circuit is operable in the regulator output voltage range from VOUT=1.2V to VOUT=3.6V and supply voltage range from VDD=VOUT+0.5 V to VDD=5.6 V. Since the proposed circuit is composed of few simple basic circuits such as a comparator and a Schmitt Trigger, it has a low current consumption of less than IS S=0.82 μA at a load current of ILOAD=200 mA. This makes the circuit suitable for low power and low voltage LDO design.