Low Thermal Impedance Research Articles

Anti-leakage and recyclable phase change thermal conductive films with ultralow thermal impedance enabled by Field’s metal via the generation and internalization of metal oxides

The heat dissipation performance of a thermal interface material (TIM) is greatly dependent on its total thermal impedance, which can be effectively reduced by introducing a solid–liquid phase change material (PCM). However, previously reported phase change TIMs (PCTIMs) have been developed only based on organic PCMs with low thermal conductivities; thus, they cannot achieve low thermal impedance. Herein, Field’s metal (FM), which is a metal phase change material with a melting point of approximately 60 ℃, is first employed to develop a novel PCTIM with an ultralow thermal impedance. Trace oxidation is conducted on FM, and Bi2O3 and SnO are thus generated, followed by forming nanoscale particles by internalization. The formation of the nanoscale metal oxides increases the surface free energy and interfacial interaction force, thereby increasing the viscosity and improving the film-forming ability of the oxidized FM. The phase change thermal conductive films with different thicknesses, which are fabricated from the optimal oxidized FM, exhibit little liquid leakage, even at a pressure of 200 psi, and reach an ultralow thermal impedance of 0.03 cm2·K·W−1 at a thickness of 100 μm after the solid–liquid phase change, which is lower than those of the previously reported PCTIMs. The optimal film possesses good thermal reliability and recyclability, and shows a significantly better cooling effect than a commercial PCTIM with an identical thickness. These ideal characteristics make the FM-based phase change thermal conductive films up-and-coming in practical applications.

Design & Thermal Analysis of Heat Pipes

Abstract: Heat pipes are a unique type of heat transfer device that can transport large amounts of heat through a small crosssectional area, with minimal temperature differences. They offer high thermal conductance and low thermal impedance. In this study, we analyzed the impact of operating parameters on heat pipe performance and predicted optimal values for parameters such as temperature input, thermal expansion coefficient, and thermal conductivity. Our results demonstrate that these parameters have a significant impact on the performance of heat pipes. The material used here for the analysis is Copper alloy. The parameters were calculated and have done its Thermal analysis using ANSYS software

Shape-stabilized low melting-point alloy/expanded graphite composite thermal pad with excellent chip heat dissipation performance

• A low melting point alloy/expanded graphite composite thermal pad is prepared. • The oxidation of the alloy is beneficial to its adsorption by expanded graphite. • The composite thermal pad possesses a high thermal conductivity of 26.94 W/m·K. • A very low thermal impedance of 0.42 K·cm 2 /W is achieved by the thermal pad. • The thermal pad shows higher heat dissipation efficiency than the commercial one. Thermal interface materials that possess high thermal conductivity and can reach low thermal impedance during service, are highly desirable for chip heat dissipation systems, especially when cooling high-power chips. Herein, a novel thermal pad was developed by combining low melting point alloy having metal-level thermal conductivity and liquid-like rheological property with expanded graphite possessing large pore volume and high thermal conductivity. Specifically, the alloy 62.5Ga21.5In16Sn was modified by the trace-oxidation method to obtain oxidized alloy, followed by adsorbing into expanded graphite and then molding and pressing to fabricate the thermal pad. It is found that the oxidation treatment resulted in the generation of refractory metal oxides Ga 2 O 3 and SnO 2 within the alloy, thereby preventing the leakage of the alloy from the composite thermal pad. Impressively, the optimal low melting point alloy/expanded graphite composite thermal pad, prepared at the oxidation duration of 24 min, expanded graphite mass fraction of 4 % and compact density of 3.125 g/cm 3 , reached a thermal conductivity of as high as 26.94 W/m·K and a thermal impedance of as low as 0.42 K·cm 2 /W, along with exhibiting a good shape-stability. More significantly, when employed into a simulative desktop CPU cooling system, this thermal pad exhibited 36.78 % higher cooling efficiency under the forced air convection, extended ten times in the time for the chip to reach the upper limit temperature (100 ℃) under the natural air cooling, and benefited to the chip to fight with the pulse-type instantaneous thermal shock, as compared to the commercial thermal pad. These excellent characteristics and good heat dissipation performance make the low melting point alloy/expanded graphite composite thermal pad show great potential for use in chip thermal management systems.

Bulk-Si Platform: Born for DRAM, Upgraded With On-Chip Lasers, and Transplanted to LiDAR

The CMOS industry has been expecting silicon photonics to provide photonic and electro-photonic integrated circuits based on the CMOS processes and infrastructures for scalability of incumbent technology evolutions and creation of novel technologies. However, the compatibility with the legacy CMOS has been compromised with the development convenience of early silicon photonics in that the specialty silicon-on-insulator substrates have been widely used as integration platforms. Since this specialty substrate may hinder the photonics integration with legacy volume products later, a legacy-friendly integration platform with a generic bulk-silicon substrate has been developed for better compatibility. This paper overviews the bulk-silicon photonics platform born for DRAM integration, upgraded with III/V-on-bulk-Si lasers, and transplanted to LiDAR applications requiring the virtuous cycle of cost and volume. The photonics integration with DRAM was to resolve the speed-capacity trade-off in the DRAM interconnects, and technical feasibility as well as lessons learned from the integration attempt are reviewed. The bulk-silicon device performance approaches that of silicon-on-insulator devices with the thermal advantage of ∼40-% lower thermal impedance and the optical disadvantage of ∼0.4-dB/mm higher waveguide loss. In the LiDAR applications, detection performance up to ∼20 m at 20 fps by a single-chip scanner integrating tunable laser, semiconductor optical amplifiers, and optical phased array are presented with future outlooks.

Nano-porous GaN cladding and scattering loss in edge emitting laser diodes.

We report continuous wave operation of electrically injected InGaN laser diodes using nano-porous GaN n-side cladding with 33% porosity. At 454 nm emission wavelength, the pulsed injection slope efficiency is 0.24 W/A with a high loss of 82 cm-1. The considerable 60 cm-1 of excess loss of the nano-porous clad lasers is attributed to scattering at pores in unintentionally 3% porosified layers, supported by numerical modeling. Simulations comparing porous GaN cladding to AlInN cladding for lasers operating at 589 nm indicate that the porous cladding provides similar internal loss and lower thermal impedance.

Impact of SiC Switch–MOS for Thermal Impedance Evaluation of Power Module

In this paper, thermal impedances of Silicon carbide (SiC) power module assembled with a Schottky Barrier Diode (SBD)–wall–integrated trench MOSFET (SWITCH–MOS) and a conventional trench gate MOSFET (UMOS) are measured. Then they are compared to show the advantage of SWITCH–MOS for thermal impedance measurement. SiC power device is attracting attention as a candidate for future power device, since it can be operated at higher current density and higher switching speed than conventional silicon (Si) power device. The power module packaging technology for SiC power device should have low thermal impedance (both transient and steady state thermal resistance) to bring out a potential ability of the device. Thermal design often has difference from measurement due to various modeling errors such as power device heat generation, module structure, interfacial thermal resistance, and cooling environment. Therefore, accurate thermal impedance measurement is an essential technology. However, the thermal impedance measurement of SiC power modules has the significant issue due to the instability of the body diode built into the SiC–MOSFET. The thermal impedance is the junction temperature rise per heat generation amount of the device. The temperature dependence of the knee voltage of the body diode is used to measure the junction temperature of the MOSFET. Since the knee voltage of SiC–MOSFET changes depending on the gate voltage, a high negative gate bias was necessary to avoid this effect. However, the negative gate bias stress may cause serious device damage such as threshold shift. The SWITCH–MOS which has SBD built in near the MOSFET channel is expected to stabilize the junction temperature measurement and avoid the risk of device deterioration. Figure 1 shows the cross–sectional schematic of the SWITCH–MOS and the conventional UMOS. The SBD are formed on the trench sidewall in SWITCH-MOS, and the device structure is almost same to the UMOS. The temperature is detected by the PiN diode for the UMOS and by the SBD for the SWITCH–MOS. Both of them measure the temperature inside of the MOSFET cell. The appearance of the test module is shown in Fig. 2. Each type of the test module is composed of the SiC die (SWITCH–MOS, UMOS, and SBD), an SiN–AMC insulating circuit substrate and an Al baseplate. The components are attached each other using AuGe solder. The junction temperature is measured from the built–in voltage of the body diode in response to a constant current flowing from the source to the drain. In the case of the UMOS, the gate bias of −18 V is applied. The gate bias is zero for the SWITCH–MOS. The thermal impedance of each test module was measured by static mode (Fig. 3). Then, the thermal structure function was calculated by transient thermal analysis (Fig. 4). Both the thermal impedance and the structure function for the SWITCH–MOS and UMOS were in good agreement. Since the SWITCH–MOS does not need negative gate bias, the threshold shift issue does not occur in principle. In addition, it is possible to perform a transient thermal testing with a large current for a long time. Because the forward degradation does not occur even if a large current is applied to the SBD in the SWITCH–MOS. The SBD built into the SWITCH–MOS makes it easier and more accurate to measure the junction temperature of the SiC–MOSFET. The thermal impedance measurement using SWITCH-MOS not only allows the precise thermal modeling of SiC power modules to be performed, but also has the potential to be applied to the calibration of the thermal design and the evaluation of thermal properties inside of the package structure. Figure 1

Electric Field Analysis of Press-Pack IGBTs

High voltage IGBT module is the ideal option for the VSC-HVDC power transmission application. At present, wire-bonded technology and press-pack technology are available packaging technologies for high voltage IGBT. The press-pack IGBTs have such advantages as low inductance, low thermal impedance and short circuit failure mode than the wire-bonded IGBT module, which especially suit for high voltage power transmission application by series connection. However, the electrical insulation failure modes of press-pack IGBTs are much less known with limited literature published. In this paper, we presented the electric field analysis of a 3D press-pack IGBT model under DC rating voltage test condition. The electric field distribution of the press-pack IGBT stack was solved as an electrostatic problem by employing the finite element method. The results revealed the potential electrical insulation failure modes of the press-pack IGBTs: corona discharge at the edge of silver plate, partial discharge at the micro gap between die and PEEK frame and creeping discharge at the surface of PEEK frame.

Novel interface material used in high power electronic die-attaching on bare Cu substrates

Silver paste sintering on bare Cu substrates can be of significant interest in power semiconductor manufacturing. However, the bare Cu substrates easily oxidized and the die attachment using the silver paste commonly applied pressure. In this study, these problems are solved by using a prepared novel silver paste, which could be pressure-less low temperature sintered completely under inert gas (99.99 wt% N2). The silver paste consists of wide size distribution particles as Ag nanoparticles, Ag sub-micro-sized particles and micro-sized Ag flakes. High content of organic system mixture in the silver paste need more evaporating time to avoid cracks in the sintered Ag film. During sintering, the Ag flakes in situ formation of highly reactive silver nanoparticles is crucial for the sintering to occur between the silver flake and particles, unlike the sintering between the silver particles. A dense silver film contributed to the sintered silver flakes, which has the nature of good densification, well sintering with the silver nanoparticle. The possible joining mechanisms of metallic bond and hydrogen bonds between bare Cu and sintered Ag were proved. Accordingly, the sandwich joints (chip/silver paste/bare Cu) include high bonding strength and low thermal impedance.

3D integrated hybrid silicon laser.

Lasers were realized on silicon by flip-chip bonding of indium phosphide (InP) devices containing total internal reflection turning mirrors for surface emission. Light is coupled to the silicon waveguides through surface grating couplers. With this technique, InP lasers were integrated on silicon. Laser cavities were also formed by coupling InP reflective semiconductor optical amplifiers to microring resonator filters and distributed Bragg reflector mirrors. Single-mode continuous wave lasing was demonstrated with a side mode suppression ratio of 30 dB. Up to 2 mW of optical power was coupled to the silicon waveguide. Thermal simulations were also performed to evaluate the low thermal impedance afforded by this architecture and potential for high wall-plug efficiency.

Design and Fabrication of Hybrid Metal Semiconductor Mirror for High-Power VECSEL

The design, fabrication, and characterization of a hybrid metal–semiconductor distributed Bragg reflector (DBR) for optically pumped vertical external cavity surface emitting laser are reported. The realization of a pure gold reflector attached to an AlGaAs/AlAs DBR is achieved through the realization of a lithography pattern alternating gold and titanium areas for better surface adhesion. This reduces from 28 to 14, and the number of DBR pairs is needed to achieve a reflectivity above 99.9%. Experimental results are supported by simulations and show an output power beyond 4 W with an optical efficiency of 19% and very low thermal impedance, validating the excellent reflectivity and bonding quality of the device.

Room Temperature Lasing in 1-μm Microdisk Quantum Dot Lasers

Lasing characteristics of InAs/InGaAs quantum dot microdisks with diameter varied from 1 to 6 μm were studied under optical pumping. The disks were fabricated with standard photolithography and two-step wet etching. We demonstrate room temperature lasing in the 1.29-1.32-μm wavelength range (ground-state transition) in microlasers as small as 1 μm in diameter. The microlasers demonstrate narrow linewidths (40-60 pm), low thermal impedance (85°C/mW), and low threshold powers (50-100 μW).

Thermo-Mechanical Characterization of Au-In Transient Liquid Phase Bonding Die-Attach

Semiconductor die-attach techniques are critically important in the implementation of high-temperature wide-bandgap power devices. In this paper, thermal and mechanical characteristics of Au-In transient liquid phase (TLP) die-attach are examined for SiC devices. Samples with SiC diodes TLP-bonded to copper-metalized silicon nitride substrates are made using several different values for such fabrication properties as gold and indium thickness, Au/In ratio, and bonding pressure. The samples are then characterized for die-attach voiding, shear strength, and thermal impedance. It is found that the Au-In TLP-bonded samples offer a high average shear strength of 22.0 kgf and a low average thermal impedance of 0.35 K/W from the device junction through the substrate. It is also discovered that some of the fabrication properties have a greater influence on the bond characteristics than others. Overall, TLP bonding remains promising for high-temperature power electronic die-attach.

Si/Ge uni-traveling carrier photodetector

We have fabricated and characterized a germanium on silicon uni-traveling carrier photodetector for analog and coherent communications applications. The device has a bandwidth of 20GHz, a large-signal 1dB saturation photocurrent of 20mA at -3V, and a low thermal impedance of 520K/W.

Growth and electrical characterisation of δ-doped boron layers on (111) diamond surfaces

A plasma enhanced chemical vapor deposition protocol for the growth of δ-doping of boron in diamond is presented, using the (111) diamond plane as a substrate for diamond growth. AC Hall effect measurements have been performed on oxygen terminated δ-layers and desirable sheet carrier densities (∼1013 cm−2) for field-effect transistor application are reported with mobilities in excess of what would expected for equivalent but thicker heavily boron-doped diamond films. Temperature-dependent impedance spectroscopy and secondary ion mass spectroscopy measurements show that the grown layers have metallic-like electrical properties with high cut-off frequencies and low thermal impedance activation energies with estimated boron concentrations of approximately 1020 cm−3.

Wafer-Fused Optically Pumped VECSELs Emitting in the 1310-nm and 1550-nm Wavebands

1300-nm, 1550-nm, and 1480-nm wavelength, optically pumped VECSELs based on wafer-fused InAlGaAs/InP-AlGaAs/GaAs gain mirrors with intracavity diamond heat spreaders are described. These devices demonstrate very low thermal impedance of 4 K/W. Maximum CW output of devices with 5 groups of quantum wells shows CW output power of 2.7 W from 180 μm apertures in both the 1300-nm and the 1550-nm bands. Devices with 3 groups of quantum wells emitting at 1480 nm and with the same aperture size show CW output of 4.8 W. These VECSELs emit a high-quality beam with beam parameter below 1.6 allowing reaching a coupling efficiency as high as 70% into a single-mode fiber. Maximum value of output power of 6.6 W was reached for 1300 nm wavelength devices with 290 μm aperture size. Based on these VECSELs, second harmonic emission at 650 nm wavelength with a record output of 3 W and Raman fiber lasers with 0.5 W emission at 1600 nm have been demonstrated.

Low Thermal Impedance of Substrate-Free Metal Cavity Surface-Emitting Microlasers

The thermal impedance of a substrate-free metal cavity surface-emitting microlaser is measured. The lasing wavelength shifts with temperature at a ratio of 4.367 × 10-2 nm/°C. An extremely low thermal impedance below 1.730°C/mW is extracted for this microlaser with a 1.0-μm radius and 3.5-μm height in the temperature window of 20°C -80°C. The full metal coverage, substrate-free configuration, and metal bonding lead to efficient heat removal.

Characterization of Lead-Free Solder and Sintered Nano-Silver Die-Attach Layers Using Thermal Impedance

Since a die-attach layer has a significant impact on the thermal performance of a power module, its quality can be characterized using thermal performance. In this paper, a measurement system for thermal impedance is developed to evaluate three die-attach materials. Thanks to its high temperature sensitivity (10 mV/ <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C), the gate-emitter voltage of an insulated gate bipolar transistor (IGBT) is used as the temperature-sensitive parameter. The power dissipation in the IGBT remains constant by a feedback loop, regardless of the junction temperature. Experimental results show that the sample using sintered nano-silver for the die-attach has 12.1% lower thermal impedance than the samples using SAC305 and SN100C solders. To check the degradation of the die-attachment, six samples using three die-attach materials were thermally cycled from -40 to 125 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C. The experimental results show that, after 500 cycles, the thermal impedance of SAC305 samples and SN100C samples is increased by 12.9% and 13.3%, respectively, which are much higher than that of the sample using the sintered nano-silver for the die-attach (3.1%).

Investigation of An Acoustic Temperature Transducer and its Application for Heater Temperature Measurement

Recent developments in temperature measurement have encouraged researchers to develop low-cost, simple structure, computerized generic transducers for environmental monitoring and industrial process control. The research presents a computerized technique which allows to measure temperature according to the variation of acoustic velocity (frequency) in a closed waveguide. Signal conditioning and processing was carried out using labVIEW (G Language) VIs. In order to evaluate the time characteristic of the transducer its response was compared with that of a reference detector (PT 100) for the same step input. Static characteristics of the transducer show a quasi-linear relationship between the measured temperature and the resonance frequency. Results of practical experiments show that in order to improve the response curve of the transducer and decrease the rising time interval it is advisable to implement thin-wall glass tubes or another material with lower thermal impedance.

50-GHz Passively Mode-Locked Surface-Emitting Semiconductor Laser With 100-mW Average Output Power

We have developed a passively mode-locked optically-pumped vertical-external-cavity surface-emitting semiconductor laser (VECSEL) which delivers up to 100 mW of average output power at a repetition rate of 50 GHz in nearly transform-limited 3.3-ps pulses at a wavelength around 960 nm. The high-repetition-rate passive mode locking was achieved with a low-saturation-fluence semiconductor saturable absorber mirror (SESAM) incorporating a single layer of quantum-dots. The output power within a nearly diffraction-limited beam was maximized using a gain structure with a low thermal impedance soldered to a diamond heat spreader. In addition, we systematically optimized the laser resonator to accommodate for the strong thermal lens caused by the optical pumping. We measured the thermal lens dioptric power and present a numerical model which is in good agreement with the measurements and is useful for optimizing resonator designs. The experimental setup is very versatile and its design and construction are discussed in detail

Thermal Management in High-Density, Stacked-Die, Multi-chip Modules

ABSTRACTVery high density multi-chip modules are being manufactured by tiling an alumina substrate with IC chips and passive components, laminating a film of Kapton over them, laser drilling vias to their I/O pads, and interconnecting them with photo patterned, copper metallization. Additional layers of components and interconnects are added on top of the base layer, as needed, to allow greater integration of large circuits. Current products are typically two layers of chips and seven layers of interconnect. As higher power applications have emerged and the power density of IC chips has increased, thermal management has become a significant factor impacting module design. We have been conducting a thermal modeling effort to map the design space for this technology. Our principal objective is to define and evaluate low thermal impedance (heat removal) configurations for a given chip set. A second objective is to determine what gains in module performance might be realized by improvements in material properties or changes in the relative thicknesses of dielectric and metal layers.