Low Temperature Solid Phase Epitaxy Research Articles

Reduction of Interface Reactions in the Low-Temperature Solid-Phase Epitaxy of ScAlMgO4 on Al2O3(0001)

Low-temperature solid-phase epitaxy is a promising route for the synthesis of thin films of ScAlMgO4, a compound with lattice spacings close to compound semiconductors for which there are no practi...

High Sn-concentration (~ 8%) GeSn by low-temperature (~ 150 °C) solid-phase epitaxy of a-GeSn/c-Ge

GeSn with a high substitutional Sn concentration (>7%) is an attractive direct band gap material for high-efficiency photodevices that can be merged with large-scale integrated circuits (LSIs). To achieve GeSn with high Sn concentration, low-temperature solid-phase epitaxy using amorphous-GeSn (a-GeSn) (Sn concentration: 10%–36%)/crystal-Ge (c-Ge) stacked structures was investigated. Solid-phase growth of GeSn was enhanced as Sn concentration was increased, which enabled epitaxial growth at very low temperature (150–200°C). Interestingly, concentrations of substitutional Sn increased with decreasing growth temperature. As a result, epitaxial growth of GeSn with substitutional Sn concentrations of ~8% was achieved by decreasing the growth temperature to 150°C using a-GeSn (Sn concentration: 36%)/c-Ge stacked structures. This technique is expected to be useful to realize multi-function LSIs, where high-efficiency photodevices are integrated with transistors.

Liquid Phase Epitaxy (LPE) Formation of Localized High Quality and Mobility Ge & SiGe by High Dose Ge-Implantation with Laser Melt Annealing for 10nm and 7nm Node CMOS Technology

Localized Ge and SiGe high quality/mobility device surface material region on bulk-Si and SOI wafers are needed for 10nm and 7nm node CMOS technology. Traditionally SiGe and Ge device surface material on bulk-Si or SOI wafers are realized by CVD epitaxial growth or Vapor Phase Epi (VPE) at elevated temperatures. Selective deposition can be achieved with hard mask. To reduce defects strain relaxed buffer (SRB) or aspect ratio trapping (ART) have been employed with bulk-Si or layer transfer wafer bonding for SiGeOI or GeOI. An alternative to VPE is to use either SPE (solid phase epitaxy) or LPE (liquid phase epitaxy) to form SiGe or Ge epitaxial surface layers. Using high dose Ge implantation >E16/cm2 with photoresist soft mask as proposed in 2004 by Borland et al [1,2]. Localized amorphous Ge surface regions can be formed after Ge-infusion doping by Gas Cluster Ion Beam (GCIB) technique followed by low temperature SPE to form single crystal thin surface Ge epitaxial layers but residual end-of-range (EOR) damage remained. Today, laser melt annealing of implanted junctions are currently being used in production for high quality back-side illuminated CMOS image sensors used in smart phone cameras by several IC and foundry semiconductor manufacturers to completely eliminate any residual implant damage/defects with 100% dopant activation provided the melt depth exceeds the implant damage depth [3]. Last year at IWJT-2013 Borland et al [4] reported using Ge-plasma ion implantation at 1E16/cm2 and 1E17/cm2 doses with laser melt annealing to realize up to 55% SiGe by LPE with >4x higher mobility at 160cm2/Vs. One limitation they noted with plasma implantation was poor retained dose due to surface sputtering at low energies which limited the Ge content to <55% for 1E17/cm2 dose. Therefore to overcome this retained dose problem we investigated Ge beamline ion implantation in this paper which should give 100% retained dose. The Ge surface amorphous layer thickness measured by elipsometry was 15nm while the Ge-SIMS depth profile measures 7nm Ge at 100%. Therma-wave analysis was used to monitor the Ge-implant damage recovery and Ge or SiGe recrystallized epitaxial surface layer after various laser melt annealing conditions of varying power level and pulse duration. The Ge-SIMS depth profiles shows we could vary the melt depth for LPE Ge layer from 10nm to >400nm and the Ge layer content from 97% down to 2% respectively. We will also show X-TEM of the Ge-LPE regions. Sb implantation was used to investigate n-type dopant activation in Ge at low and high doses of 3E13/cm2 and 3E15/cm2. Rs measurements were done using a special Hx 4 point probe and SRP (spreading resistance profile) depth profiles. In summary, using high dose beam-line Ge-implantation we realized >7nm amorphous Ge deposition. Epitaxial growth of Ge was achieved by liquid phase epitaxy using shallow laser melt annealing between 10nm and >400nm melt depths.

Formation of Ultra Shallow p+/n Junction in Silicon Using a Combination of Low-Temperature Solid Phase Epitaxy and Non-Melt Double-Pulsed Green Laser Annealing

MOSFETs scaling-down is an effective way to attain high-performance CMOS operating with lower power and leakage current. However, short channel effects have become a serious problem due to the shortening of channel length. One of the promising methods to suppress this problem is by forming a shallow, highly doped and activated source/drain extension region. Fabricating ultra shallow p+/n junction is difficult due to the channeling of boron ions and anomalous boron diffusion during fabrication processes. A combination of Ge pre-amorphization implantation, low-energy boron implantation and two-step annealing, involving low-temperature solid phase epitaxy preannealing followed by non-melt laser annealing was used for forming ultra shallow p+/n junction in silicon. The physical relationship among the regrowth of implanted layer, boron activation and diffusion, and leakage current is investigated. We have succeeded in forming ultra shallow p+/n junction with junction depth of 8 nm and sheet resistance of 920 Ω/□.

Low-temperature solid phase epitaxy for integrating advanced source/drain metal-oxide-semiconductor structures

We show that chemical vapor deposition using trisilane decomposition opens capabilities for the deposition of amorphous silicon on Si substrate at low temperature. Based on this behavior we developed a process including amorphous silicon deposition and crystallization. Transmission electron microscopy observations prove that solid phase epitaxy (SPE) occurs and produces monocrystalline layers, free of extended defects and compatible with complementary metal-oxide-semiconductor technology. We also show that during SPE films remain amorphous on oxidized areas while they transform into single crystal on Si. This process opens promising perspectives for the fabrication of advanced MOS structures.

Instability of junctions formed by low energy B implant and low temperature solid phase epitaxy growth

The stability of p+∕n junctions remains a critical issue for device performance. Shallow junctions formed by low temperature solid phase epitaxy growth (LTSPEG) are not stable during additional thermal processes. Anomalous boron diffusion and boron trapping by end-of-range defects are observed during additional furnace annealing. The study shows that, by adding a (MeV) implantation step before LTSPEG, B trapping and B diffusion are significantly reduced during post-LTSPEG annealing. The technique can be used as a method to increase the stability of shallow junctions formed by LTSPEG.

An Examination of Athermal Photonic Effects on Boron Diffusion and Activation During Microwave Rapid Thermal Processing

This work examines the role of 672 nm optical illumination on the diffusion and activation of B in Si as a function of various factors. The factors studied include length of anneal, maximum temperature of anneal, type of co-implanted and pre-amorphizing species and ambient oxygen concentration. The anneal conditions fell into one of three categories: (1) high-temperature (>900°C) spike and 10-second anneals; (2) low temperature (550°C) 30-minute anneals; and (3) room-temperature long-term “anneals”. Implanted species included BF2 implants, pre-amorphized B-only implants, and pre-amorphized BF2 implants. Finally, the ambient oxygen concentration was varied from atmospheric pressure to 100 ppm.The results show that illumination: (1) affects the diffusion of B on spike anneal time frames; (2) has limited effect on diffusion over 10-second time frames; and (3) fails to enhance the activation of B during low-temperature solid phase epitaxy and at room temperature. Additionally, illumination has no effect on B-diffusion when oxygen is present in ambient concentrations but does show an effect when the presence of oxygen is restricted. Finally, the presence of F affects both the net diffusion of B in Si and the relative effect of illumination on the diffusion of B.

Evolution and Degeneration of Dimer-Adatom-Stacking-Fault Structure in Solid-Phase Epitaxy on Si(111) Surface Observed by Scanning Tunneling Microscopy

Large unit cells of dimer-adatom-stacking-fault structure and related 2 × 2 and c(4 × 2) reconstructions have been prepared by low-temperature solid-phase epitaxy and observed by scanning tunneling microscopy. The size-different unit cells of the DAS structure are considered to be a structure evolution in which more electron charge transfers in a larger unit cell from the adatom dangling bonds to the rest-atom dangling bonds. In some cases the DAS structure can degenerate into triangular 2 × 2 domains and bundlinke c(4 × 2) domains. The rest atoms are always fully filled by electrons due to the charge transfer. The adatom dangling bonds are partially filled in a c(4 × 2) symmetry and essentially empty in a 2 × 2 symmetry. As a result, the rest atoms in 2 × 2 domains can be imaged without the adatom protrusions while in the c(4 × 2) domains the protrusions of the adatoms and the rest atoms appear in zigzag chains, when the sample is negatively biased.

Charge transfer and rest-atom imaging in dimer-adatom-stacking-fault structure evolution observed by scanning tunnelling microscopy on the Si(111) surface

Large unit cells of dimer-adatom-stacking-fault (DAS) structure and related (2 × 2) and c(4 × 2) reconstructions have been prepared by low temperature solid phase epitaxy and observed by scanning tunnelling microscopy. The development of larger unit cells of the DAS structure is considered to be a structure evolution in which more electron charge transfers from the adatom dangling bonds to the rest-atom dangling bonds. In some cases the DAS structure can degenerate into triangular (2 × 2) domains and band-like c(4 × 2) domains. The former are located on a faulted layer while the underneath bilayer of the latter can consist of alternating faulted and unfaulted strips. The rest atoms are always fully filled by electrons due to the charge transfer. The adatom dangling bonds are partially filled in the c(4 × 2) domains and essentially empty in the (2 × 2) domains. As a result, the rest atoms in (2 × 2) domains can be imaged without the adatom protrusions while in the c(4 × 2) domains protrusions of both appear in zigzag chains in filled-state images, when the sample is negatively biased.

Phase Transformations in a-Si/Ni/C-Si Structures with Different Interfacial Ni Layer Thicknesses

Planar low-temperature solid phase epitaxy of amorphous silicon in a-Si/10nmNiSi/c-Si structure was observed. The crystallization rate is well described by the arrhenius-type expression with the activation energy and preexponencial factor deduced from our measurements of 1.7 eV and 2.4×10 12 nm/min, respectively. NiSi 2 formation at the NiSi 2 /a-Si interface is believed to be the limiting stage of the transformation. The structures with thicker Ni-reached interfacial layer perform much poorer a-Si epitaxy.