Low Temperature Selective Epitaxial Growth Research Articles

Low Temperature Cyclic Deposition/Etch (CDE) of Tensile-Strained Si:P

Our aim was to assess the feasibility of the Low Temperature Selective Epitaxial Growth of tensile-Si:P (for Raised Sources and Drains in n-type FETs). Ideally, we would like to have high amounts of tensile strain and low resistivities in t-Si:P layers grown at 550°C, with (i) mainstream Si2H6 + PH3 gases for the non-selective deposition of t-Si:P and (ii) HCl + GeH4 for the selective etches of amorphous Si:P versus monocrystalline Si:P (to have selectivity on patterned wafers). In Ref (1), we focused on deposition in such cyclic processes. Thanks to (i) high F(PH3)/(2*F(Si2H6)) Mass-Flow Ratios (MFR), (ii) a reduction of the H2 carrier flow, from the reference value of a few tens of standard liters per minute down to 1/5th of it and (iii) a chamber pressure increase, from 20 Torr up to 90 Torr, we succeeded in dramatically increase [P]subst. and reach values as high as 7.9% in t-Si:P layers. 40 Torr was the best pressure in order to simultaneously have (i) a high substitutional P concentration (6.3%), (ii) a reasonable growth rate (5.5 nm min.-1) and (iii) a low electrical resistivity (0.41 mOhm. cm), without being hampered by a layer uniformity that would be too degraded to be of use in actual devices. Those t-Si:P layers, grown with a MFR of 0.46, were of superior crystalline quality and smooth. We have otherwise shown in Ref. (2) that it was possible, thanks to (i) a reduced H2 carrier flow, (ii) a low HCl mass-flow and (iii) a relatively high GeH4 mass-flow, to etch away mono-cristalline t-Si:P at temperatures close to 550°CWe have thus evaluated the Cyclic Deposition / Etch (CDE) of t-Si:P at 550°C. Deposition occurred at 40 Torr with Si2H6 + GeH4, while (selective) etching was conducted at 90 Torr with HCl + GeH4. Pressure was ramped up or down with a 5 Torr / s slope. 15s pure HCl etchings, also at 90 Torr, were sometimes used after HCl + GeH4 etchings to remove surface Ge atoms.We first evaluated, for 10 cycles CDE processes, the impact of the HCl + GeH4 etch duration on the t-Si:P thickness and the substitutional P concentration. The deposition time / cycle was always 60s. As expected, the t-Si:P thickness decreased more or less linearly as the HCl + GeH4 etch duration / cycle increased, from ~ 50 nm for 0s down to 20-25 nm for 60s (Fig. a). Meanwhile, the “apparent” substitutional P concentration and thus the tensile strain decreased less and less, as the HCl + GeH4 etch duration/cycle increased, when using high flows of pure HCl at the end of each cycle to get rid of excess Ge atoms (from 6.2% for 0s down to 2.0% for 60s in the most favorable configuration; Fig. b). Such a tensile strain loss was shown by SIMS to be due to (i) less and less P atoms and (ii) more and more Ge atoms being present in the Si lattice as the HCl + GeH4 etch duration/cycle increased (from 6.2% and 0% for 0s down to/up to 4.4% and 5.5% for 60s; Fig. c). The surface haze of CDE-grown layers was otherwise ~ 2 times higher than that of layers grown without etchings and the electrical resistivity slightly increased with the HCl + GeH4 etch duration/cycle (from 0.38 mOhm.cm for 0s up to 0.42 mOhm.cm for 60s).Thanks to the use of 10 cycles CDE processes with various HCl + GeH4 etch durations on bulk and SiN-covered Si substrates, we then showed that an etch selectivity of ~ 6 could be expected, for a-Si:P over t-Si:P, on patterned wafers (Fig. d). The presence of numerous nuclei on SiN-covered substrates nominally free of any bi-dimensional a-Si:P layers was evidenced by haze measurements, however, hinting at a lower effective selectivity.We then switched over to patterned SOI wafers with gates. We succeeded, with 7 cycles CDE processes, in having almost full selectivity with 60s depositions and 40s etches / cycle, respectively (Fig. e). Maybe because there was a mix of a-Si:P and t-Si:P regions on such wafers, we had almost the same deposited t-Si:P thickness / CDE cycle (4.1 – 4.2 nm) whatever the HCl + GeH4 duration / cycle in the 15s – 40s range (Fig. f). Meanwhile, there was a gradual disappearance of a-Si:P on dielectrics as that etch duration increased.[1] J.M. Hartmann and J. Kanyandekwe, J. Cryst. Growth 582, 126543 (2022).[2] J.M. Hartmann and M. Veillerot, Semicond. Sci. Technol. 35, 015015 (2020). Figure 1

Insights into the C Distribution in Si:C/Si:C:P and the Annealing Behavior of Si:C Layers

Si:C and Si:C:P alloys are potential candidates for source-drain stressor applications in n-type Fin Field Effect Transistors (FinFETs). Increasing the C content to achieve high strain results in the arrangement of C atoms as third nearest neighbors (3nn) in the Si:C lattice. During thermal annealing, the presence of C atoms as 3nn may promote clustering at the interstitial sites, causing loss of stress. The concentration of C atoms as 3nn is reduced by the incorporation of a small amount of Ge atoms during the growth, whereas in-situ P doping does not influence this 3nn distribution [J Solid State Sci. Technol vol 6, p 755, 2017]. Small amounts of Ge are provided during low temperature selective epitaxial growth scheme, which are based on cyclic deposition and etching (CDE). In this work, we aim to provide physical insights into the aforementioned phenomena, to understand the behavior of 3nn C atoms and the types of defects that are formed in the annealed Si:C films. Using ab-initio simulations, the Ge-C interaction in the Si matrix is investigated and this insight is used to explain how the Ge incorporation leads to a reduced 3nn distribution of the C atoms. The interaction between C and P in the Si:C:P films is also investigated to explain why the P incorporation has not led to a reduction in the 3nn distribution. We then report on the Raman characterization of Si:C layers subjected to post epi annealing. As the penetration depth of the laser is dependent on the wavelength, Raman measurements at two different wavelengths enable us to probe the depth distribution of 3nn C atoms after applying different annealing conditions. We observed a homogeneous loss in 3nn C throughout the layer. Whereas in the kinematic modeling of high resolution X-ray diffraction spectra, a gradient in the substitutional C loss was observed close to the epitaxial layer/substrate interface. This gradient can be due to the out diffusion of C atoms into the Si substrate or to the formation of interstitial C clusters, which cannot be distinguished in HR-XRD. Deep Level Transient Spectroscopy indicated that the prominent out-diffusing species was interstitial CO complex while the interstitial C defects were also prevalent in the epi layer.

Low temperature selective epitaxial growth of SiCP on Si(110) oriented surfaces

We demonstrate growth of SiCP film on Si(110) substrates with excellent structural quality, based on X-Ray Diffraction, Cross-sectional Transmission Electron Microscopy and Secondary Ion Mass Spectrometry analysis. This (110) surface orientation is very important since it represents the sidewall of recessed Source/Drain (S/D) areas when the film is used as an embedded stressor to induce uniaxial tensile strain in a planar transistor. An optimized (110) SiCP growth process can also be used to thicken the S/D regions of non-planar multi-gate device structures (e.g. Fin Field Effect Transistors, Tri-gate FETs) with a highly doped epitaxial film in order to enable good electrical contacts and/or induce strain. The films have been grown using Si3H8, SiH3CH3 and PH3 for growth and Cl2 as the etchant gas, all in inert carrier gas. H2 has been eliminated, preventing Cl2 from reacting with H2 yielding HCl, since Cl2 is needed to establish selectivity. We present trends on temperature, total pressure, SiH3CH3, PH3 and Cl2 etch flow. We studied selective epitaxial growth (SEG) in the 525–575°C range. Thanks to the use of Si3H8 we can obtain high SEG rates even at 525°C in conjunction with a high deposition pressure of 20 kPa (~150Torr). It is observed that the growth rate, carbon concentration, phosphorous concentration and etch rate of SiCP on Si (110) differs greatly from that on Si (100). A process optimized specifically for Si(100) surfaces may yield no growth on Si(110) surfaces. However, optimizing a process on Si(110) is assured to result in growth on Si(100). Comparing one process optimized on Si(110) with the results on Si(100), we found a substantially lower SEG rate, higher [P] incorporation and lower [C] incorporation on Si(110). One key criterion for growth on patterned substrates with Si(110) sidewalls is that the SEG rate on the sidewall must be≥0; otherwise the vertical sidewall will be etched and undercut of the spacer will occur, degrading the structural quality of the transistor and potentially impacting the electrical performance of the device.

Dislocations and Triangular Defect in Low-Temperature Halo-Carbon Epitaxial Growth and Selective Epitaxial Growth

Dislocations were investigated in the halo-carbon low-temperature epitaxial growth and low-temperature selective epitaxial growth (LTSEG) conducted at 13000C. The origin of triangular defects was investigated in low-temperature epilayers grown at higher growth rates with HCl addition. Due to the conversion of substrates’ basal plane dislocations (BPD) into threading dislocations, the concentration of BPDs was about an order of magnitude lower than the concentration of threading dislocations at moderate growth rates. An additional order of magnitude conversion of BPDs into threading dislocations was observed at higher grow rates achieved with HCl addition. In LTSEG epilayers, dislocation concentration away from the mesa walls was comparable to the blanket (i.e., regular non-selective) growth. High concentrations of BPDs were found only at mesa edges located on the “upstream” side with respect to the step-flow direction. No substrate defects could be traced to the triangular defects. Instead, the disturbances causing the triangular defect generation are introduced during the epitaxial process.

Local-Loading Effect in Low-Temperature Selective Epitaxial Growth of 4H-SiC by Halo-Carbon Method

In this work, the local-loading effect and its influence on the growth rate enhancement and the growth rate non-homogeneity is investigated during the halo-carbon low-temperature selective epitaxial growth (LTSEG) using an SiO2 mask. The average growth rate during the LTSEG can be more than three-times higher than in blanket epitaxy at the same growth conditions. Both the size of the LTSEG seed windows and the surrounding area covered with the mask determine the growth rate non-homogeneity. A model for predicting the growth rate distribution is suggested.

Low temperature selective epitaxial growth of SiGe layers using various dielectric mask patterns and process conditions

The SiGe film was deposited at a low temperature of 675–725 °C with various dielectric mask patterns and process conditions using reduced pressure chemical vapor deposition. Pattern shape and process conditions associated with the growth rate and the Ge composition of the selective epitaxial growth (SEG) have been examined for the SiH 4–GeH 4–H 2 system. The objective was to understand the effect of pattern size at low temperature for the feasible device applications. The growth rates showed large non-uniformity of 1.4 depending upon the window width, 2–100 μm, of dielectric mask patterns. From the influence of the pattern shape/size and process parameters, the evolution of growth rates could be explained by the surface migration and the surface topology as well. After the surface migration control appearing dominantly at the initial stage, the surface topology became significant at the last part of the SEG process. The Ge composition is important to form the high quality SEG of SiGe films, so that it is important to optimize the flow rate of SiH 4, GeH 4, and total source gas.

Minimization of specific contact resistance in multiple gate NFETs by selective epitaxial growth of Si in the HDD regions

High parasitic S/D resistance is a major obstacle in realizing future generations of CMOS technologies using multiple gate FETs with narrow fins. Reduction of specific contact resistance by selective epitaxial growth of Si in heavily doped S/D regions of a multiple gate FET helps with achieving low S/D resistance. This paper addresses integration of low temperature selective epitaxial growth process into multiple gate FET processing. Our experimental results show more than 30% reduction in the parasitic S/D resistance for 16-nm selective epitaxial growth of Si in the heavily doped S/D regions of multiple gate NFETs with less than 20-nm wide fins. A follow up of this work with HfO 2-TiN gate stack shows more than 20% improvement in the drive current at a constant I OFF for 40-nm selective epitaxial growth of Si in the heavily doped S/D regions of multiple gate FETs.

Si-Ge-H-Cl 계를 이용한 자기정렬 HBT용 Si 및 SiGe의 선택적 에피성장

Low temperature selective epitaxial growth of Si and SiGe has been obtained using an industrial single wafer chemical vapor deposition module operating at reduced pressure. Epitaxial Si and heteroepitaxial SiGe deposition with Ge content about 20 % has been studied as extrinsic base for self-aligned heterojunction bipolar transistors(HBTs), which helps to reduce the parasitic resistance to obtain higher maximum oscillation frequencies(f<TEX>$\_$</TEX>max/). The dependence of Si and SiGe deposition rates on exposed windows and their evolution with the addition of HCl to the gas mixture are investigated. SiH<TEX>$_2$</TEX>Cl<TEX>$_2$</TEX> was used as the source of Si SEG(Selective Epitaxial Growth) and GeH<TEX>$_4$</TEX> was added to grow SiGe SEG. The addition of HCl into the gas mixture allows increasing an incubation time even low growth temperature of 675∼725<TEX>$^{\circ}C$</TEX>. In addition, the selectivity is enhanced for the SiGe alloy and it was proposed that the incubation time for the polycrystalline deposit on the oxide is increased probably due to GeO formation. On the other hand, when only SiGe SEG(Selective Epitaxial Growth) layer is used for extrinsic base, it shows a higher sheet resistance with Ti-silicide because of Ge segregation to the interface, but in case of Si or Si/SiGe SEG layer, the sheet resistance is decreased up to 70 %.

Si1−xGex selective epitaxial growth for ultra-high-speed self-aligned HBTs

Si1−xGex low temperature selective epitaxial growth was investigated by using a UHV/CVD system with high pressure H2 pre-cleaning of the substrate and SiGe HBTs were fabricated. The selective epitaxial growth was achieved by using different incubation times for Si(100) substrate and mask layers. Device performances show the good crystallinity of selectively grown Si1−xGex layer: an extremely high current gain of 45 000 and a high cutoff frequency of 154 GHz were achieved in the HBT with a maximum Ge content of 25%. Furthermore, the comparison of AC performance between self-aligned and non-self-aligned transistors demonstrates the advantage of the self-aligned structure formed by the Si1−xGex low-temperature selective epitaxial growth.

Plasma etch effects on low-temperature selective epitaxial growth of silicon

The quality of epitaxial silicon grown on regions exposed to plasma etching using He, CHF3, and CF4 etching gases has been studied. Plasma-etch-induced surface damage leads to defects in the epilayers. Dislocation loops and precipitates at the epi/substrate interface are always observed. High-temperature prebake can further lead to microtwins and threading dislocations. The formation of defects in epilayers is attributed to the ion bombardment induced surface/subsurface defects and the reactive-ion-induced contaminants on exposed Si areas. A 900 °C grown sacrificial oxide film can efficiently remove both near-surface defects and contaminants to get a clean SiO2/Si interface, resulting in high quality Si epilayers. A 5-nm sacrificial oxide is adequate. An air exposure between several plasma etch cycles is also important in suppressing polymer accumulation on substrates.

Silicon wafer preparation for low-temperature selective epitaxial growth : Carl Galewski, Jen-Chung Lou and William G. Oldham. IEEE Trans. Semicond. Mfg3(3), 93 (1990)

Silicon wafer preparation for low-temperature selective epitaxial growth : Carl Galewski, Jen-Chung Lou and William G. Oldham. IEEE Trans. Semicond. Mfg3(3), 93 (1990)

Silicon wafer preparation for low-temperature selective epitaxial growth

Many potential selective silicon epitaxy applications demand low-temperature processing. However, the hydrogen baking that is commonly used to remove the native oxide before epitaxial deposition becomes less effective as the temperature is reduced. Therefore, making selective epitaxy manufacturable requires alternative oxide removal techniques that are reliable and noncontaminating. Exposure to the vapor over an aqueous solution of HF is investigated as a means of providing oxide-free and passivated-wafer surfaces prior to reactor loading. The dilution of the H/sub 2/O:HF mixture is found to be important in determining the oxide removal rate. An oxygen peak at the substrate interface during SIMS (secondary ion mass spectrometry) profiling is an indicator of the presence of oxide patches that can cause defects at the initiation of epitaxial deposition. Defect-free films without an interface peak of oxygen are grown at 850 degrees C after using a 5-s exposure to the vapor over a 1:2 H/sub 2/O/sub :/49% HF mixture followed by a 900 degrees C hydrogen bake. A hydrogen-bake temperature of 1050 degrees C is needed in the reactor to avoid an interfacial oxygen peak for samples not exposed to the HF vapor. >

Low-temperature selective epitaxial growth of silicon at atmospheric pressure

Epitaxial Si has been grown selectively on oxide-patterned substrates from 850 down to 600 °C for the first time in the Si-Cl-H system at atmospheric pressure. Si deposition was achieved by hydrogen reduction of dichlorosilane in an ultraclean system using a load lock. Epitaxy was achieved at low temperatures only when the hydrogen was purified to remove traces of H2O and O2 implying that an oxygen-free environment is the most important factor controlling epitaxy at low temperatures. Cross-sectional transmission electron micrographs reveal perfect crystallinity in the epitaxial layer and a totally clean and featureless interface between epitaxy and substrate.

Low-temperature (250 °C) selective epitaxy of GaAs films and p-n junction by laser-assisted metalorganic chemical vapor deposition

Low-temperature selective epitaxial growth of device quality GaAs has been achieved by laser-assisted chemical vapor deposition (LCVD). GaAs substrates thermally biased to temperatures in the range 250–500 °C were irradiated by an Ar ion laser to induce localized deposition of GaAs. Carefully selected growth conditions resulted in growth rates as low as a monolayer per second at 250 °C. This is the lowest substrate temperature for epitaxial GaAs with optical and structural quality comparable to those achieved in conventionally metalorganic chemical vapor deposition grown GaAs. Also reported is the first p-n junction by LCVD technique using zinc as the p-type dopant. This new low-temperature selective deposition process can lead to maskless fabrication of multicomponent devices on the same wafer.