Low Temperature Dopant Activation Research Articles

Integration Challenges of Flash Lamp Annealed LTPS for High Performance CMOS TFTs

This work demonstrates a method of producing polycrystalline silicon TFTs using Flash Lamp Annealing (FLA) as a potential industrial counterpart to excimer laser annealing. Material uniformity and low-temperature dopant activation are explored within an investigation on solid-phase epitaxial regrowth for PMOS TFTs. Silicon self-implantation is used to partially amorphize select regions of FLA LTPS material, allowing epitaxial regrowth to incorporate boron into the resulting lattice. This regime is compared with total amorphization, in which epitaxial regrowth cannot occur. The effects of these different methods of recrystallization are demonstrated through transfer characteristics of fabricated transistors. Devices utilizing a partial pre-amorphization of FLA LTPS demonstrated effective hole channel mobilities of 40 - 50 cm2/(Vs) in low drain bias operation. Additionally, self-aligned TFTs using FLA are presented for the first time, with effective hole channel mobilities of 30 - 60 cm2/(Vs) in low drain bias operation using the same treatment.

Elevated thermoelectric figure of merit of n-type amorphous silicon by efficient electrical doping process

The currently dominant thermoelectric (TE) materials used in low to medium temperature range contain Tellurium that is rare and mild-toxic. Silicon is earth abundant and environment friendly, but it is characterized by a poor TE efficiency with a low figure of merit, ZT. In this work, we report that ZT of amorphous silicon (a-Si) thin films can be enhanced by 7 orders of magnitude, reaching ∼0.64 ± 0.13 at room temperature, by means of arsenic ion implantation followed by low-temperature dopant activation. The dopant introduction employed represents a highly controllable doping technique used in standard silicon technology. It is found that the significant enhancement of ZT achieved is primarily due to a significant improvement of electrical conductivity by doping without crystallization so as to maintain the thermal conductivity and Seebeck coefficient at the level determined by the amorphous state of the silicon films. Our results open up a new route towards enabling a-Si as a prominent TE material for cost-efficient and environment-friendly TE applications at room temperature.

Dopant-dependence of one-step metal-induced dopant activation process in silicon

We investigate dopant-dependence of low temperature dopant activation technique in α-Si featuring one-step metal-induced crystallization (MIC) to decrease resistivity of p+ and n+ Si films by forming NixSiy. Ni not only crystallizes p-type α-Si film but also facilitates activation of boron atoms in the α-Si during the crystallization at 500 °C. However, phosphorus atoms are poorly activated because of the suppressed Ni-MIC rate in n-type α-Si. Finally, p+/n and n+/p junction diodes are demonstrated on single crystalline Si substrates by the low temperature dopant activation technique promising for high performance TFTs as well as transistors with an elevated S/D.

High performance n+/p and p+/n germanium diodes at low-temperature activation annealing

In this work we demonstrate the fabrication and characterization of high performance junction diodes using annealing temperatures within the temperature range of 300–350°C. The low temperature dopant activation was assisted by a 50nm platinum layer which transforms into platinum germanide during annealing. The fabricated diodes exhibited high forward currents, in excess of 400A/cm2 at ∼|0.7|V for both p+/n and n+/p diodes, with forward to reverse ratio IF/IR greater than 104. Best results for the n+/p junctions were obtained at the lower annealing temperature of 300°C. These characteristics compare favorably with the results of either conventional or with Ni or Co assisted dopant activation annealing. The low-temperature annealing in combination with the high forward currents at low bias makes this method suitable for high performance/low operating power applications, utilizing thus high mobility germanium substrates.

Low Temperature Dopant Activation Using Variable Frequency Microwave Annealing

AbstractVariable frequency microwaves (VFM) and rapid thermal annealing (RTA) were used to activate ion implanted dopants and re-grow implant-damaged silicon. Four-point-probe measurements were used to determine the extent of dopant activation and revealed comparable resistivities for 30 seconds of RTA annealing at 900 °C and 6-9 minutes of VFM annealing at 540 °C. Ion channeling analysis spectra revealed that microwave heating removes the Si damage that results from arsenic ion implantation to an extent comparable to RTA. Cross-section transmission electron microscopy demonstrates that the silicon lattice regains nearly all of its crystallinity after microwave processing of arsenic implanted silicon. Secondary ion mass spectroscopy reveals limited diffusion of dopants in VFM processed samples when compared to rapid thermal annealing. Our results establish that VFM is an effective means of low-temperature dopant activation in ion-implanted Si.

Characterization of the low temperature dopant activation behavior at NiSi/silicon interface formed by implant into silicide method

Process temperature and thermal budget control are very important for high- k dielectric device manufacturing. This work focuses on the characteristics of low temperature activated nickel silicide/silicon (M/S) interface formed by implant into silicide (IIS) method. By combining SIMS, C– V, I– V, and AFM measurements in this work, it provides a clear picture that the high dopant activation ratio can be achieved at low temperature (below 600 °C) by IIS method. From SIMS and C– V measurements, high dopant activation behavior is exhibited, and from I– V measurement, the ohmic contact behavior at the M/S junction is showed. AFM inspection displays that under 2nd RTA 700 °C 30 s no agglomeration occurs. These results suggest that IIS method has the potential to integrate with high- k dielectric due to its low process temperature. It gives an alternate for future device integration.

Low-temperature dopant activation technology using elevated Ge-S/D structure

Dopant activation annealing of an elevated Ge-S/D structure formed on Si was investigated for application in advanced CMOSFET fabrication. Due to the low melting point of Ge, dopant activation was observed below 600 °C. However, the low temperature annealing process resulted in high reverse-bias p–n junction leakage. A thermal process budget of 900 °C, 60 s was found to be the minimum necessary for achieving low junction leakage. The location of the junction after the 900 °C annealing can be as shallow as ∼20 nm beneath the original Si interface for both p+/n and n+/p diodes.

Low-temperature dopant activation and its application to polycrystalline silicon thin film transistors

Low-temperature activation of dopants in amorphous silicon films was achieved by a new method and high-performance polycrystalline silicon thin film transistors were fabricated through its application. It was found that the dopants implanted into amorphous silicon were activated simultaneously with the crystallization of amorphous silicon. With the help of a thin nickel layer, the thermal budget for dopant activation and crystallization was considerably reduced, from 600 °C (30 h) to 500 °C (5 h). Even without plasma hydrogenation, the n-channel polycrystalline silicon thin film transistors fabricated at temperatures below 500 °C showed a mobility of 120 cm2/V s, which is much higher than that of conventional devices fabricated at 600 °C.