Low-temperature Amorphous Silicon Research Articles

Hybrid External Cavity Laser with an Amorphous Silicon-Based Photonic Crystal Cavity Mirror

The authors present results on the performance of a hybrid external cavity photonic crystal laser-comprising semiconductor optical amplifier, and a 2D photonic crystal cavity fabricated in low-temperature amorphous silicon. The authors demonstrate that lithographic control over amorphous silicon photonic crystal cavity-resonant wavelengths is possible, and that single-mode lasing at optical telecommunications wavelengths is possible on an amorphous silicon platform.

Heterogeneous growth of continuous ZIF-8 films on low-temperature amorphous silicon

Thin amorphous silicon films, deposited at low temperature by Inductively Coupled Plasma Chemical Vapor Deposition, have, for the first time, been employed as substrate for ZIF-8 growth. In order to investigate the role of the surface chemistry on the nucleation process, films have also been grown on other silicon-based substrates such as H-terminated Si(1 0 0), SiO2 and quartz. Film preparation was carried out at room temperature using a mixed Zn nitrate and imidazole solution in methanol or ethanol. Using methanol, continuous ZIF-8 films were obtained on amorphous Si and H-terminated Si(1 0 0), while less homogeneous films were formed on the other surfaces. In ethanol, slower growth rates occurred and thinner films, compared to the ones in methanol, were obtained. These slower rates highlight the different effects of the four surfaces on the growth process. These differences have been related to the silanol density of the surfaces and to the Lewis basic strength which affect imidazole moiety deprotonation. H-terminated Si(1 0 0) and amorphous Si turned out to be the most reactive surfaces, whereas on quartz and, especially, on SiO2 reactivity was much lower. Experimental results have been validated by the DFT modelling of the proton exchange, which takes place between the imidazole group and the surface. Finally, the VOCs adsorption capability of ZIF-8 films grown on amorphous silicon has been evaluated through temperature desorption experiments.

Sub-micron gap in-plane micromechanical resonators based on low-temperature amorphous silicon thin-films on glass substrates

In this work, high-frequency bulk mode resonators made from low stress hydrogenated amorphous silicon (a–Si:H) thin-films are demonstrated. The microelectromechanical structures are fabricated using surface micromachining techniques at a maximum processing temperature of 175 °C on glass substrates. The silicon thin-film based resonators presented here are temperature compatible with post processing on standard CMOS. The resonators are capacitively driven and sensed across 400 nm air gaps. A proof of concept design consisting of a 200 µm side length square has been selectively excited in the Lamé-mode at a characteristic vibration frequency of 13.64 MHz. The quality factor of the resonators is in the 103 range and the motional resistance was measured to be approximately 21.8 MΩ at a DC bias voltage of 40 V.

Thermal noise reduction and absorption optimization via multimaterial coatings

Future gravitational wave detectors (GWDs) such as Advanced LIGO upgrades and the Einstein Telescope are planned to operate at cryogenic temperatures using crystalline silicon (cSi) test-mass mirrors at an operation wavelength of 1550 nm. The reduction in temperature in principle provides a direct reduction in coating thermal noise, but the presently used coating stacks which are composed of silica (${\mathrm{SiO}}_{2}$) and tantala (${\mathrm{Ta}}_{2}{\mathrm{O}}_{5}$) show cryogenic loss peaks which results in less thermal noise improvement than might be expected. Due to low mechanical loss at low temperature amorphous silicon (aSi) is a very promising candidate material for dielectric mirror coatings and could replace ${\mathrm{Ta}}_{2}{\mathrm{O}}_{5}$. Unfortunately, such an $\mathrm{aSi}/{\mathrm{SiO}}_{2}$ coating is not suitable for use in GWDs due to high optical absorption in aSi coatings. We explore the use of a three material based coating stack. In this multimaterial design the low absorbing ${\mathrm{Ta}}_{2}{\mathrm{O}}_{5}$ in the outermost coating layers significantly reduces the incident light power, while aSi is used only in the lower bilayers to maintain low optical absorption. Such a coating design would enable a reduction of Brownian thermal noise by 25%. We show experimentally that an optical absorption of only $(5.3\ifmmode\pm\else\textpm\fi{}0.4)\text{ }\text{ }\mathrm{ppm}$ at 1550 nm should be achievable.

A Low Temperature Photonic Crystal Technology for Integration with Modern CMOS Technologies

ABSTRACTIn this paper, low temperature amorphous silicon oxynitride (a-SixOyNz:H) thin film technology is proposed for implementation of CMOS compatible photonic crystal (PC) based optical integrated circuits (OICs). The a-SixOyNz films of different refractive indices were developed by plasma enhanced chemical vapor deposition (PECVD) technique using silane, nitrous oxide, and ammonia as gas phase precursors at 300°C. The films with refractive index between 1.43 − 1.75 were obtained by changing gas flow ratios. Such thin films can be used as cladding and core layers in photonic crystal structure.The bandgap and guiding properties of the a-SixOyNz based PCs were simulated and was shown that the a-SixOyNz:H based PC technology offers larger feature sizes than a conventional silicon based photonic crystals.

Dual-Gate SiO2/P3HT/SiNx OTFT

AbstractThis paper reports on a new organic thin-film transistor (OTFT) based on a dual-gate configuration. This dual-gate OTFT is useful in circuit applications from the standpoint of providing control over selected device parameters for enhanced circuit reliability. Moreover, the dual-gate structure can shield parasitic effects in vertically integrated electronics, making it particularly promising for active matrix display and imaging applications. The dual-gate OTFT also lends itself as a highly functional test structure for characterization of interface integrity of the active organic and dielectric layers. In this work, the dual-gate OTFT is fabricated using regioregular poly(3-hexylthiophene) (P3HT) as the organic semiconductor layer. The bottom-gate employs silicon dioxide (SiO2) as the gate dielectric, whereas the top-gate employs a low-temperature amorphous silicon nitride (SiNx) as the passivation dielectric. The voltage on the bottom-gate has a distinct influence on the threshold voltage, subthreshold slope, on-current, and leakage current of the top-gate TFT. Similar dependence of the bottom-gate TFT characteristics on the top-gate voltage is observed. This design provides a means of characterizing the density of states of the bottom P3HT/SiO2 and top P3HT/SiNx interfaces, and conveys insight into the underlying transport mechanisms. The ability to control selected TFT parameters (e.g., threshold voltage) using the dual-gate OTFT structure is attractive for circuit integration applications in active matrix displays and imagers.

Low temperature amorphous silicon channel material for polysilicon thin film transistors

In this work we have investigated the use of low temperature amorphous silicon as the channel material for laser crystallized polysilicon thin film transistors (TFTs). The 50 nm films were deposited by plasma enhanced chemical vapor deposition (PECVD) at 225°C or by sputtering at room temperature and then laser crystallized to produce the active channel region. n-channel and p-channel devices were then produced with the same low temperature (less than 600°C) top-gate process. For plasma-deposited material an anneal step at 450°C for 1 h was required before crystallization to avoid bubbling and ablation due to hydrogen evolution, but no such anneal was required for the sputtered material due to its hydrogen content <1 at.% and Ar content <1 at.%. For 50 nm films, laser energy densities were typically in the range of 300–400 mJ/cm 2. Excellent device results were obtained for the plasma-deposited material with n-channel field effect mobilities greater than 100 cm 2/V s and on/off ratios greater than 10 8 at 5 V drain bias. Transistors using sputtered silicon channels had smaller mobilities and on/off ratios at 5 V drain bias. In moving toward lower temperature polysilicon processing (less than 230°C) both channel films appear to be viable candidates.

Stability of low-temperature amorphous silicon thin film transistors formed on glass and transparent plastic substrates

This article describes the formation of amorphous silicon thin film transistors (TFTs) on glass and flexible transparent plastic substrates using rf plasma enhanced chemical vapor deposition and a maximum processing temperature of 110 °C. Silane diluted with hydrogen was used for the preparation of the amorphous silicon, and SiH4/NH3/N2 or SiH4/NH3/N2/H2 mixtures were used for the deposition of the silicon nitride gate dielectric. The amorphous silicon nitride layers were characterized by transmission infrared spectroscopy and current-voltage measurements; the plastic substrates were 10 mil thick (0.25 mm) polyethylene terephthalate sheets. Transistors formed using the same process on glass and plastic showed linear mobilities ranging from 0.1 to 0.5 cm2/V s with ION/IOFF ratios⩾107. To characterize the stability of the transistors on glass, n- and p-channel transconductances were measured before and after bias stressing. Devices formed at 110 °C show evidence of charge trapping near the a-Si/SiNx interface and the creation of dangling-bond defects. The defect dynamics are consistent with the defect pool model. Under +10 and +25 V bias stress, the rates of creation of low energy defects are only moderately larger than those for high temperature devices; the devices show markedly higher rates of defect creation under higher positive bias. Current-voltage analysis of low temperature dielectrics shows very low leakage, but positive bias stress shows a significantly higher electron trapping rate near the a-Si:H/SiNx interface, indicating problems with low temperature dielectric formation. The magnitude of the rates of defect creation and trapping in these nonoptimized devices suggests that amorphous silicon TFTs with stability approaching that of typical large area active matrix electronic devices could be formed at low temperatures compatible with transparent flexible polymeric substrates.

Water‐Resistant Coating on Low Temperature Amorphous Silicon Nitride Films by a Thin Layer of Amorphous Silicon Hydrogen Alloy

Hydrogenated amorphous silicon nitride films fabricated by plasma‐enhanced chemical vapor deposition at low temperatures (<150°C) tend to oxidize within 1 month because of their porous structure. Therefore, these low temperature films are not suitable for application in the passivation of microelectronic devices. It is found, however, that low temperature amorphous silicon (a‐Si:H) films prepared by plasma‐enhanced chemical vapor deposition resist oxidation indicating a relatively less porous structure capable of resisting the percolation of molecules. Therefore, if a thin layer (6.4 nm) a‐Si:H film is deposited at 100°C on a 100°C deposited film, the double film structure resists oxidation for more than 14 months of air exposure. This indicates that the composite film structure has the potential to be utilized for device passivation of thin film transistors when a low temperature (<150°C) process is required.