Low Subthreshold Swing Research Articles

Ultralow-Power Circuit and Sensing Applications Based on Subthermionic Threshold Switching Transistors.

The most recent breakthrough in state-of-the-art electronics and optoelectronics involves the adoption of steep-slope field-effect transistors (FETs), promoting sub-60 mV/dec subthreshold swing (SS) at ambient temperature, effectively overcoming "Boltzmann limit" to minimize power consumption. Here, a series integration of nanoscale copper-based resistive-filamentary threshold switch (TS) with the IGZO channel-based FET is used to develop a TS-FET, in which the turn-on characteristics exhibit an abrupt transition over five decades, with an extremely low SS of 7 mV/dec, a high on/off ratio (>109), and ultralow leakage current (40-fold decrease), ensuring excellent repeatability and device yield. Unlike previous device-centric studies, this work highlights potential circuit applications (logic-inverter, pulse-sensor amplification, and photodetector) based on TS-FET. The sharp transition behavior of TS-FET enables the establishment of logic inverters with a high voltage gain of ≈800, with a circuit-level demonstration achieving a bias-independent record-high intrinsic gain (>1000). A wearable pulse sensor integrated with an amplifier circuit ensured the precise amplification of electrophysical signals by 450 times. In addition, the application of a TS-FET-based photodetector features high responsivity (1.08 × 104 mA/W) and detectivity (1.03 × 1020 Jones). The low-power strategy of TS-FETs is promising for the development of energy-efficient integrated circuits alongside sensor-interconnected biomedical applications in wearable technology.

Stabilization of Tetragonal Phase in Hafnium Zirconium Oxide by Cation Doping for High-K Dielectric Insulators.

As electronic circuit integration intensifies, there is a rising demand for dielectric insulators that provide both superior insulation and high dielectric constants. This study focuses on developing high-k dielectric insulators by controlling the phase of the Hf0.5Zr0.5O2 (HZO) film with additional doping, utilizing yttrium (Y), tantalum (Ta), gallium (Ga), silicon (Si), and aluminum (Al) as dopants. Doping changes the ratio of tetragonal to monoclinic phases in doped HZO films, and Y-doped HZO (Y:HZO) films specifically exhibit a high tetragonal phase ratio and a dielectric constant of 40.9, indicating superior insulating properties compared to undoped HZO films. To clarify the fundamental mechanism driving the enhancement in dielectric properties, we have carried out various analyses combined with density functional theory (DFT) calculations. Through the optimization of the post-deposition annealing (PDA) process and the heterojunction structure with Al2O3, an Al2O3/Y:HZO heterojunction with a high dielectric constant and even lower leakage current compared to a single layer was developed. The thin-film transistor (TFT) with the Au/Ti/amorphous InGaZnO4 (a-IGZO)/Al2O3/YHZO/TiN heterojunction structure exhibits low subthreshold swing (SS) values within a narrow gate-source voltage (Vsg) range. This study advances knowledge on how the controlled-phase doped HZO films affect the dielectric constant and leakage current and will contribute to semiconductor technology advancements by overcoming the limitations of conventional high-k dielectric insulators.

Improving the photoswitching performance of a transistor with amorphous metal oxide semiconductor thin film by a gradient annealing approach

Metal oxides are attracting attention as electronic mate rials in research and industry. Thin films of amorphous indium gallium zinc oxide (a-IGZO) exhibit low absorbance in the visible spectrum, making them ideal components in transparent electronics. To widen the scope of use for thin film transistor (TFT) devices based on a-IGZO in on-chip sensing applications, photoresponsive behavior has been achieved by proper engineering of the active layers by either introducing a photosensitive top layer or using a method to generate localized states inside the band gap. In this paper, we propose a bilayer structured with the use of thermal annealing of a-IGZO film at different temperatures. Thermal annealing has been shown to improve the electrical performance of the TFT devices because of the improved film quality but negatively affects the photoresponsivity by removing tarp sites that play an important role in both charge generation and photomultiplication via the photogating effect. Therefore, here we propose an a-IGZO film with a high temperature-annealed bottom layer and pristine top layer. The bottom layer plays a vital role in the charge transport behavior, resulting in a low threshold voltage and subthreshold swing similar to the device with a fully annealed film, while the photoresponse of the device is driven by the higher density of gap states in the pristine top layer. This proposed method is advantageous to previously published procedures due to the simplicity of using no additional materials and complex steps to introduce trap sites into the photoactive layer, but only differential annealing temperature.

Two-Dimensional Vertical Transistor with One-Dimensional van der Waals Contact.

Two-dimensional (2D) materials enable vertical field effect transistors (VFETs), which provide an alternative path for scaling down the channels of transistors. The challenge is the short channel effect when the thickness of the 2D channel decreases to ∼10 nm. Here, we show that a VFET with an ultrashort channel can be accomplished by employing a semimetal carbon nanotube (CNT) as a 1D van der Waals (vdW) contact. The CNT-VFETs with 5-10 nm MoS2 channels exhibit high on/off ratios exceeding 105, low subthreshold swing values of 160-120 mV/dec, and high current densities over 104 A/cm2. Such a switch even works with an ∼ 3.4 nm thick channel. The excellent comprehensive performance can be ascribed to the reduced short channel effect as the sub-2 nm CNT contact has weaker electrostatic screening to the gate, a reduced Fermi level pinning effect, and a highly tunable barrier. The VFETs with 1D vdW contacts hold great promise for ultrascaled transistors and are prospective in future nanoelectronics and nano-optoelectronics.

Amorphous In–Al–Sn–O Thin Film Transistors and Their Application in Optoelectronic Artificial Synapses

AbstractIn‐Al‐Sn‐O (IATO) is a very promising novel amorphous oxide as the active layer of thin film transistors (TFTs). Herein, IATO TFTs are first fabricated with the effects of annealing on IATO films and TFTs being studied. The IATO films possessed amorphous structure, flat surface morphology, high visible light transmittance, and wide optical bandgap ≈4.20 eV before and after annealing even at 400 °C. The minimal surface roughness and internal defects are obtained for the 300 °C annealed IATO film. Correspondingly, the 300 °C annealed TFTs demonstrated the best overall performance including high saturation mobility (8.55 ± 0.62 cm2 V−1 s−1), low subthreshold swing (0.40 ± 0.07 V dec−1), ideal on/off current ratio (1.25 ± 0.09 × 108), and negligible hysteresis (0.23 ± 0.03 V) values. The 300 °C annealed TFTs are then applied in optoelectronic artificial synapses and exhibit typical synaptic properties, including excitatory postsynaptic current, paired‐pulse facilitation, and short‐term plasticity to long‐term plasticity conversion in response to light stimulation. The international Morse code and repetitive learning‐forgetting behavior of the human brain are also successfully simulated. In particular, an emotion‐memory efficiency model is proposed and the emotion effect on human memory efficiency is successfully imitated via the regulation of gate voltage.

Characterization and modeling of the mobility, threshold voltage, and subthreshold swing in p-GaN gate HEMTs at cryogenic temperatures

This study presents a comprehensive investigation of the electrical properties of p-GaN gate HEMT devices under cryogenic operations, spanning a temperature range from 300 K all the way down to 10 K. We report achievement of a low sub-60 mV/dec sub-threshold swing (SS) (33.2 mV/dec at 10 K), a high ION/IOFF ratio (∼3.5 × 1010 at 10 K), and a remarkable ID,max (∼358 mA/mm at 10 K) in p-GaN gate HEMTs operating under cryogenic conditions. Furthermore, the mobility, threshold voltage shifts, and SS characteristics at cryogenic temperatures are modeled in p-GaN HEMTs. In summary, p-GaN gate HEMTs are promising for cryogenic applications due to their low SS, high gm,max, impressive ION/IOFF ratio, and substantial ID,max. Furthermore, the modeling achieved in this work can pave the way for future characteristic prediction in p-GaN HEMTs at cryogenic temperatures.

Conjugated Polymer-Based Photo-Crosslinker for Efficient Photo-Patterning of Polymer Semiconductors.

Photo-patterning of polymer semiconductors using photo-crosslinkers has shown potential for organic circuit fabrication via solution processing techniques. However, the performance of patterning, including resolution (R), UV light exposure dose, sensitivity (S), and contrast (γ), remains unsatisfactory. In this study, a novel conjugated polymer based photo-crosslinker (PN3, Figure 1a) is reported for the first time, which entails phenyl-substituted azide groups in its side chains. Due to the potential π-π interactions between the conjugated backbone of PN3 and those of polymer semiconductors, PN3 exhibits superior miscibility with polymer semiconductors compared to the commonly used small molecule photo-crosslinker 4Bx (Figure 1a). Consequently, photo-patterning of polymer semiconductors with PN3 demonstrates improved performance with much lower UV light exposure dose, higher S and higher γ compared to 4Bx. By utilizing electron beam lithography, patterned arrays of polymer semiconductors with resolutions down to 500nm and clearer edges are successfully fabricated using PN3. Furthermore, patterned arrays of PDPP4T, the p-type semiconductor (Figure 1b), after being doped, can function as source-drain electrodes for fabricating field-effect transistors (FETs) with comparable charge mobility and significantly lower sub-threshold swing value compared to those with gold electrodes.

Heterogeneous monolithic 3D integration for hybrid vertical CMOS inverter using n-type IGTO TFT on p-type Si FET

In this work, a complementary metal oxide semiconductor (CMOS) vertical inverter using heterogeneous monolithic 3D (M3D) integration with p-type Si field-effect transistor (FET) and n-type indium-gallium-tin-oxide (IGTO) thin film transistor (TFT) was implemented and characterized. This CMOS inverter was attained by vertical stacking n-type IGTO TFT on p-type Si FET. Oxide semiconductor materials such as indium-gallium-zinc-oxide (IGZO), indium-tungsten-oxide (IWO), indium oxide (In2O3) and IGTO are being considered as potential options for channel materials in M3D integration technology due to high electrical characteristics and low temperature process. Among them, IGTO was employed as a channel material to achieve high mobility. We fabricated a n-type IGTO TFT using HfO2 and tungsten as a gate dielectric and electrode, respectively. The post-annealing process was conducted at 200–500 °C with 50 °C intervals. The IGTO TFT exhibits a high field-effect mobility (32.9 cm2/Vs), low sub-threshold swing (0.070 V/dec) and stable reliability behaviour (ΔVth < 0.4 V) against various external gate bias temperature stress tests in a low temperature (<500 °C). The stable heterogeneous vertical inverter performance such as voltage-transfer curve (VM = 1.66 V), voltage gain (30.1 V at VDD = 3 V), and noise margin (NMH = 1.22 V, NML = 1.34 V) were well behaved. This M3D integration-based hybrid CMOS inverter can be an alternative knob toward various device applications.

Demonstration of normally-off p-channel GaN transistor with high threshold voltage and low subthreshold swing based on single p-GaN

Demonstration of normally-off p-channel GaN transistor with high threshold voltage and low subthreshold swing based on single p-GaN

Ohmic Contact Formation to β-Ga2O3 Nanosheet Transistors with Ar-Containing Plasma Treatment

Effective Ohmic contact between metals and their conductive channels is a crucial step in developing high-performance Ga2O3-based transistors. Distinct from bulk materials, excess thermal energy of the annealing process can destroy the low-dimensional material itself. Given the thermal budget concern, a feasible and moderate solution (i.e., Ar-containing plasma treatment) is proposed to achieve effective Ohmic junctions with (100) β-Ga2O3 nanosheets. The impact of four kinds of plasma treatments (i.e., gas mixtures SF6/Ar, SF6/O2/Ar, SF6/O2, and Ar) on (100) β-Ga2O3 crystals is comparatively studied by X-ray photoemission spectroscopy for the first time. With the optimal plasma pre-treatment (i.e., Ar plasma, 100 W, 60 s), the resulting β-Ga2O3 nanosheet field-effect transistors (FETs) show effective Ohmic contact (i.e., contact resistance RC of 104 Ω·mm) without any post-annealing, which leads to competitive device performance such as a high current on/off ratio (&gt;107), a low subthreshold swing (SS, 249 mV/dec), and acceptable field-effect mobility (μeff, ~21.73 cm2 V−1 s−1). By using heavily doped β-Ga2O3 crystals (Ne, ~1020 cm−3) for Ar plasma treatments, the contact resistance RC can be further decreased to 5.2 Ω·mm. This work opens up new opportunities to enhance the Ohmic contact performance of low-dimensional Ga2O3-based transistors and can further benefit other oxide-based nanodevices.

Sputtered AlOx interlayer for improving performance of a-InGaZnO TFTs: A study on hydrogen diffusion mitigation and electron modulation

In this study, we developed an a-InGaZnO (a-IGZO) thin film transistor (TFT) structure that inserts a sputtered AlOx intermediate layer (IL) within the active layer. The IL not only effectively blocks hydrogen (H) diffusion from the gate insulation (GI) layer to the upper region of a-IGZO but also modifies the energy band structure of the bottom channel region and creates a locally low electron concentration that counteracts the excess electron donated by diffused H. Compared to conventional TFTs, the TFT with the IL exhibits impressive electrical characteristics, including a high saturation mobility (μsat) of 14.5 cm2 V−1 s−1, an on/off current ratio (Ion/Ioff) of 6.2 × 108, and a low subthreshold swing (SS) of 0.16 V/dec. Furthermore, this structure exhibits remarkable stability under negative bias stress and negative bias illumination stress, with ΔVth values of 1.1 and 1.5 V, respectively. The integration of the IL provides a promising approach for enhancing the performance of a-IGZO TFTs, paving the way for next-generation display technologies.

Inkjet-Printed, High-Performance MoS2 Transistors and Unipolar Logic Electronics.

Two-dimensional (2D) semiconductor field-effect film transistors combine large carrier mobility with mechanical flexibility and therefore can be ideally suitable for wearable electronics or at the sensor interfaces of smart sensor systems. However, such applications require large-area solution processing as opposed to single-flake devices, where the critical challenge to overcome is the high interflake resistance values. In this report, using a narrow-channel, near-vertical transport device architecture, we have fabricated inkjet-printed sub-20 nm channel electrolyte-gated transistors with predominantly intraflake carrier transport. Therefore, the electronics transport in these transistors is not dominated by the high interflake resistance, and the intraflake material properties including doping density, defect concentration, contact resistance, and threshold voltage modulation can be examined and optimized independently to achieve a current density as high as 280 μA·μm-1. In addition, through the passivation of the sulfur vacancies with a tailored surface treatment, we demonstrate an impressive On-Off current ratio exceeding 1 × 107, complemented by a low subthreshold swing of 100 mV·decade-1. Next, exploiting these high-performance transistors, unipolar depletion-load-type inverters have been fabricated that show a maximum gain of 31. Furthermore, we have realized NAND, NOR, and OR gates, demonstrating their seamless operation at a frequency of 1 kHz. Therefore, this work represents an important step forward to realize electronic circuits based on printed 2D thin film transistors.

Influence of Doping Engineering in 1 μm Drift Layer Quasi‐Vertical Fin Field‐Effect Transistor for Achieving &gt;139 V Breakdown Voltage

A quasi‐vertical gallium nitride (GaN) fin field effect transistor (FinFET) is designed and analyzed to assess the performance of electrical parameters. The device is deployed on a silicon carbide (SiC) substrate and analyzed using technology computer‐aided design (TCAD). The donor concentration in the critical regions is identified as a significant limiting factor for FinFET electrical properties. Hence, the influence of channel and drift layer doping concentrations (Nd) on performance characteristics is investigated in this work. The electrical characteristics such as threshold voltage, ION/IOFF ratio, subthreshold swing (SS), specific ON‐resistance, and breakdown voltage (VBV) are evaluated for various doping profiles. The doping profile with channel and drift layer concentration of 4 × 1015 cm−3 for a 300 nm fin width and 1 μm thick drift layer exhibits normally OFF behavior with a threshold voltage (Vt) of 1.5 V. It also demonstrates a VBV of 139 V. The corresponding doping profile reveals a low SS of 61 mV dec−1, which is comparable to other similar power devices. This demonstrates the significant potential of the device for medium‐power switching applications.

Eco‐Friendly Approach to Ultra‐Thin Metal Oxides‐ Solution Sheared Aluminum Oxide for Half‐Volt Operation of Organic Field‐Effect Transistors

AbstractSol–gel‐based solution‐processed metal oxides have emerged as a key fabrication method for applications in thin film transistors both as a semiconducting and a dielectric layer. Here, a low‐temperature, green solvent‐based, non‐toxic, and cost‐effective solution shearing approach for the fabrication of thin aluminum oxide (AlOx) dielectrics is reported. Optimization of sustainability aspects like energy demand, and selection of chemicals used allows to reduce the environmental impact of the life cycle of the resulting product already in the design phase. Using this approach, ultra‐thin, device‐grade AlOx films of 7 nm are coated—the thinnest films to be reported for any solution‐fabrication method. The metal oxide formation is achieved by both thermal annealing and deep ultra‐violet (UV) light exposure techniques, resulting in capacitances of 750 and 600 nF cm−2, respectively. The structural analysis using microscopy and x‐ray spectroscopy techniques confirmed the formation of smooth, ultra‐thin AlOx films. These thin films are employed in organic field‐effect transistors (OFETs) resulting in stable, low hysteresis devices leading to high mobilities (6.1 ± 0.9 cm2 V−1 s−1), near zero threshold voltage (−0.14 ± 0.07 V) and a low subthreshold swing (96 ± 16 mV dec−1), enabling device operation at only ±0.5 V with a good Ion/Ioff ratio (3.7 × 105).

Nanosheet integration of induced tunnel field-effect transistor with lower cost and lower power

Nanosheet transistors are poised to become the preferred choice for the next generation of smaller-sized devices in the future. To address the future demand for high-performance and low-power computing applications, this study proposes a nanosheet structure with a vertically stacked design, featuring a high ION/IOFF ratio. This Nanosheet design is combined with an induced tunnel field-effect transistor. By utilizing SiGe with a carrier mobility three times that of Si and employing a line tunneling mechanism, the research successfully achieves superior Band to Band characteristics, resulting in improved switching behavior and a lower Subthreshold Swing (SS). Comparative studies were conducted on three TFET types: Nanosheet PIN TFET, Nanosheet Schottky iTFET, and Fin iTFET. Results show that the Nanosheet PIN TFET has a higher ION/IOFF ratio but poorer SSavg values at 47.63 mV/dec compared to the others. However, with a SiGe Body thickness of 3 nm, both Nanosheet iTFET and Fin iTFET exhibit higher ION/IOFF ratios and superior SSavg values at 17.64 mV/dec. These findings suggest the potential of Nanosheet iTFET and Fin iTFET for low-power, lower thermal budgets, and fast-switching applications.

Performance assessment of InGaAs–SOI–FinFET for enhancing switching capability using high-k dielectric

In this work, a high-k In0.53Ga0.47As silicon-on-insulator FinFET (InGaAs–SOI–FinFET) is presented for high-switching and ultra-low power applications at 7 nm gate length. Indium Gallium Arsenide (InGaAs) is a compound semiconductor that has gained attention in the field of semiconductor devices, including FinFETs. The incorporation of InGaAs in proposed FinFETs introduces several advantages, making it an attractive material for certain applications. InGaAs–SOI–FinFET performance has been observed and found high electron mobility, improved On-Current performance (ION), drain current (IDS), transconductance (gm), energy bands, lower subthreshold swing (SS), electric field, surface potential, and better short-channel behaviour. All the results of InGaAs–SOI–FinFET have been simultaneously compared with SOI-FinFET and conventional FinFET (C-FinFET). Incorporating InGaAs in the channel with high-k gate material enhances the drain current by ⁓75% and ⁓77% in the proposed device compared to the other two counterparts. Owing to the higher drain current in the InGaAs–SOI–FinFET, other parameters have also been improved, which leads to higher performance applications.

Efficient gradient heating-up approach for rapid growth of high-quality amorphous ZrO2 dielectric films

High-k oxide dielectric films are indispensable for low-power-consumption oxide thin-film transistors (TFTs) applied in advanced and portable electronics. However, high-quality oxide dielectric films prepared by solution process typically require sophisticated processes and long thermal annealing time, severely limiting both the throughput manufacturing and cost-effectiveness. In this study, the influence of different heating-up methods on the surface morphology and dielectric properties was systematically investigated. Gradient heating-up method could not only substantially improve the surface morphology and quality of high-k ZrO2 films but also efficiently shorten the annealing time. The gradient heating-up process was further designed on the basis of thermal behavior of the xerogel-like precursor, which successfully realize the preparation of high-quality ZrO2 films with an annealing time of 5 min (i.e. the efficiency of thermal treatment increased by about 89%). The ZrO2 film presented excellent dielectric properties, including a low leakage current density of ∼10−8 A cm−2 (at 2 MV cm−1 ), a large areal capacitance of 169 nF cm−2 and a high dielectric constant of 20.41 (1 MHz). Furthermore, InSnZnO TFT based on the ZrO2 gate dielectrics shows an acceptable device performances, such as a high carrier mobility of 2.82 cm2 V−1 s, a high on/off current ratio of ∼105 and a low subthreshold swing of 0.19 V decade −1 at a low operation voltage of 5 V. This work provide a highly promising approach to fabricate high-quality solution-processed high-k oxide dielectric films employed for large-scale and low-power-consumption electronics.

P‐21: Post‐Annealing Optimization for Top‐Gate Amorphous In‐Ga‐Zn‐O Thin‐Film Transistors with Atomic‐Layer‐Deposited Ultrathin AlOx Dielectric

The effects of post‐annealing on amorphous InGaZnO (a‐IGZO) TFTs with ultrathin atomic layer deposited (ALD) AlOxgate insulator (GI) were investigated. The non‐annealed devices exhibited uncontrollable gate leakage current while postannealing in either oxygen (O2) or nitrogen (N2) exhibited noticeable improvements. Optimizing O2‐annealed devices demonstrated the most optimal performance, including a low subthreshold swing of 61.6 mV/dec and a high on/off current ratio over 109. Capacitance‐voltage and X‐ray photoelectron spectroscopy analyses further revealed the underlying mechanism of defect elimination at the AlOx/a‐IGZO interface.

Binarized Neural Network Comprising Quasi‐Nonvolatile Memory Devices for Neuromorphic Computing

AbstractThis study presents a binarized neural network (BNN) comprising quasi‐nonvolatile memory (QNVM) devices that operate in a positive feedback loop mechanism and exhibit an extremely low subthreshold swing (≤ 5 mV dec−1) and a high on/off ratio (≥ 107). A pair of QNVM devices are used for a single synaptic cell in a cell array, in which its memory state represents the synaptic weight, and the voltages applied to the pair act as input in a complementary fashion. The array of synaptic cells performs matrix multiply‐accumulate (MAC) operations between the weight matrix and input vector using XNOR and current summation. All the results of the MAC operations and vector‐matrix multiplications are equivalent. Moreover, the BNN features a high accuracy of 93.32% in the MNIST image recognition simulation owing to high device uniformity (1.35%), which demonstrates the feasibility of compact and high‐performance neuromorphic computing.

Substrate temperature effects on PEALD HfAlO dielectric films for IGZO-TFT applications

Aluminum incorporated hafnium oxide (HfAlO) has garnered significant attention due to its high dielectric constant. The present study employs supercycle plasma-enhanced atomic layer deposition (PEALD) to prepare HfAlO films, switching between HfO2 and Al2O3 deposition. The effects of substate temperature on the HfAlO films are systematically investigated. The experimental results indicate that increased substrate temperatures favor Al2O3 growth on HfO2, but excessively high temperatures result in deviated PEALD growth and deteriorated film properties. The PEALD window can be reached at substrate temperatures of 300 to 350 °C. The Al content is substantially affected by the substrate temperature, despite a constant Al2O3 PEALD cycle ratio used. The film deposited at 350 °C exhibits the highest Al content, density, and (111) crystalline orientation ratio, leading to a high breakdown field of 6 MV/cm and a considerable dielectric constant of 27. The HfAlO films are applied to indium gallium zinc oxide transistor as the dielectric layer, and the 350 °C-deposited HfAlO leads to the best device performance with a remarkably high on/off current ratio of 3.5 × 109, low threshold voltage of −0.1 V, saturated mobility of 6.1 cm2 V−1 s−1, and a low subthreshold swing of 76 mV/dec.