Low-pressure Chemical Deposition Research Articles

Study of Inner Spacer Module Process for Gate All Around Field Effect Transsistors

Gate-All-Around(GAA) transistor is the most competitive device for the replacement of Fin Field-Effect Transistor (FinFET). Integrating the inner spacer module into process flow of manufacturing GAA devices still faces significant challenges.In this study, dummy gates were included and the most critical processes for inner spacer, such as cavity etching, dielectric material conformal filling and precise etching back process were studied.The inner spacer cavity with a depth of 10.10 nm was achieved using isotropic etching, and dielectric filling was completed by low pressure chemical deposition (LPCVD). Finally, an inner spacer with 9.35 nm thickness is formed after precise etching the dielectric material. Furthermore,to verify the physical isolation of the inner spacer, a selective epitaxy was developed on the Source/Drain region, achieving better process results. This research will provide important references for the industry to manufacture GAA devices, especially inner spacers.

Formation of Si nanocrystals in LP CVD semi-insulating polycrystalline silicon films

Influence of oxygen on silicon nanocrystals formation peculiarities and size in semi-insulating polycrystalline silicon thin films has been demonstrated by the means of local atomic surrounding sensitive electronic structure experimental studies. Low-pressure chemical deposition from the gas phase at a relatively low temperature leads to formation of semi-insulating polycrystalline silicon film containing nanocrystals with the grain size of 20–40 nm. At the same time, films oxygen doping result in formation of silicon nanocrystals arrays with the mean particle size less than 10 nm. Possibility of size-controlled Si nanocrystals formation followed by electronic structure reconstruction of amorphous films with nanocrystalline inclusions is discussed and can be found prospective for a range of possible applications.

4H-SiC JFET Multilayer Integrated Circuit Technologies Tested up to 1000 K

Testing of semiconductor electronics at temperatures above their designed operating envelope is recognized as vital to qualification and lifetime prediction of circuits prior to deployment in beneficial applications. This work describes the high temperature electrical testing of prototype 4H silicon carbide (SiC) junction field effect transistor (JFET) integrated circuit technology implemented with multilayer interconnects intended for prolonged operation in applications at temperatures up to 773K (500 °C). A 50mm diameter sapphire wafer was used in place of the standard NASA packaging for this experiment. Testing was carried out between 300K (27 °C) and 1150K (877 °C) with successful electrical operation of all devices observed up to 1000K (727 °C). We tested each of the following devices: Transmission Line Method (TLM) test structure, discrete JFET with a gate length of 6 µm and width of 12 µm, discrete on-chip capacitor of area about 0.5mm2, 3-stage ring oscillator comprising of 12 JFET transistors and 30 resistors, and one open-circuit trace on the sapphire wafer to test leakage of everything up to the die. These devices resided on a single 3mm x 3mm SiC die that was bonded via die-attach paste to a 50mm sapphire wafer “package” with patterned 1µm thick gold traces. The lateral spacing of gold traces on sapphire was 3.175mm. The die attach paste is conductive, providing backside electrical contact necessary for stable device operation. 25µm diameter gold ball/wedge bonds connected chip pads to gold traces on the sapphire wafer, and 250 µm diameter gold wires with glass fiber insulation connected the sapphire wafer to a terminal strip outside an oven. The die remained uncovered for the duration of the test. The thermal profile started with a ramp at 3K/minute from 300K to 773K. Then the sample remained at 773K for 22 hours. The 22-hour “burn-in” at 773K was performed because significant reductions in leakage have been observed during previous testing at this temperature. The final ramp from 773K to 1150K was at 9K/minute. The JFET and TLM were measured with a digitizing curve tracer, while the capacitor and sapphire wafer leakages were measured with source-measure units. Ring oscillator output was measured with a 10M-Ohm probe AC-coupled to digitizing oscilloscope. The devices were continuously biased, but only measured every 90 seconds during the thermal ramps and every 2 hours during the 773K “burn in.” The 3-stage ring oscillator frequency decreased from ~850 kHz at 773K to ~660 kHz at 1000K with output amplitude that decreased from 130mV to 20 mV. The JFET exhibited saturation current of 280 µA at 300K that decreased to 50 µA at 1000K. The n-type TLM exhibited specific contact resistance of less than 4 x 10-4 µÙ cm2 throughout the test, and a sheet resistance of 5 kµÙ/square at 300K that increased to 38 kµÙ/square at 1000K with approximately T2power law behavior. No leakage above open-circuit noise floor was observed from the capacitor at 20V bias until 600K. The leakage increased with temperature until 686K at 378 µA at which point the 20V leakage began to drop even while the temperature was increasing. By the time the capacitor had reached the start of the 773K burn in period the leakage had dropped to ~100 µA. The capacitor had measurable leakage again when heated to above 990K and then the max leakage remained below 100 µA. The sapphire did not have measurable 20V leakage until 850K, which increased to 68 nA at 1000K. Above 1000K all devices started to demonstrate behavior consistent with loss of the backside bias connection. Upon cooling and inspection it was found that the backside contact metal on the die and the gold trace area on the sapphire became transparent where there was die attach paste. There were cracks in the on-chip SiO2dielectric formed from low pressure chemical deposition (LPCVD) using tetraethyl orthosilicate (TEOS) precursor at the corners of some metal traces. Some of the gold ball bonds wires had melted. The peak oven temperature reached 1150K before the oven was turned off so a clear sequence of causality is hard to determine; therefore, electrical data reported is only to 1000K corresponding to apparent loss of backside bias.

Electrical transport in Ni-catalysed multi-walled carbon nanotubes

Low pressure chemical deposition method (LPCVD) is used to synthesise the Ni-catalysed carbon nanotubes (CNTs). These CNTs are grown on supported catalyst film of Ni nanoparticles by the catalytic decomposition of acetylene at 700°C and at a chamber pressure of 10 Torr. We have used field emission scanning electron microscopy (FESEM) and transmission electron microscopy (TEM) to study the morphology of the catalyst film of Ni as well as the CNTs. The standard four probe method is used for electrical transport measurements of these multi-walled carbon nanotubes (MWNTs) over the temperature range of 200-4.2 K. From these results, it is found that the variable range hopping (VRH) is responsible for the transport of carriers over the entire temperature range of 200-4.2 K. For the temperature range (200-100 K), three-dimensional VRH is suggested, while two-dimensional VRH is observed for the temperature range (100-4.2 K).

The Influence of B2H6 on the Growth of Silicon Nanowire

The un-doped and boron-doped silicon nanowires (SiNWs) were grown via vapor–liquid–solid (VLS) mechanism by low pressure chemical deposition (LPCVD). The diameters of un-doped and boron-doped SiNWs varied from 18.5 to 75.3 nm and 26.6 to 66.1 nm, respectively. The critical growth temperature of boron-doped SiNWs is 10°C lower than that of un-doped ones and the diameters of the boron-doped SiNWs is always larger than that of the un-doped ones under different growth temperatures. This is because that the introduction of diborane enhanced the dissociation of SiH4 which determines the growth process of SiNW. A growth process of silicon nanowire is proposed to describe the influence of B2H6.

The effects of post-deposition processes on polysilicon Young's modulus

Polysilicon films deposited by low pressure chemical deposition (LPCVD) are the most widely used structural material for microelectromechanical systems (MEMS). However, the properties of LPCVD polysilicon are known to vary significantly, depending on deposition conditions as well as post-deposition processes. This paper presents extensive experimental results, investigating the effects of phosphorus doping and texture on Young's modulus of polysilicon films. Polysilicon films are deposited at 585, 605 and 625 to a thickness of 2 m. Specimens with varying phosphorus doping levels are prepared by diffusion doping at various temperatures and times using both and phosphosilicate glass (PSG) as the source. Young's modulus is calculated by taking the average of the values calculated from the resonant frequencies of four different-size lateral resonators. Our results show that Young's modulus decreases with increasing doping concentration, and increases with increasing texture. The polysilicon grain size and grain boundaries could also have an influence on Young's modulus, which remains to be further investigated.

The Effects of Texture and Doping on The Young's Modulus of Polysilicon

AbstractPolysilicon films deposited by low pressure chemical deposition (LPCVD) are the most widely used structural material for microelectromechanical systems (MEMS). However, the structural properties of LPCVD polysilicon films are known to vary significantly, depending on deposition conditions as well as post-deposition processes. This paper investigates the effects of phosphorus doping and texture on Young's modulus of polysilicon films. Polysilicon films are depostied at 585°C, 605"C, and 625°C to a thickness of 2µm. Specimens with varying phosphorus doping levels are prepared by diffusion doping at various temperatures and times using both POCl3 and phosphorsilicate glass (PSG) as the source. Texture is measured using an X-ray diffractometer. Young's modulus is calculated by taking the average of the values calculated from the resonant frequencies of four-different size lateral resonators. Our results show that Young's modulus of diffusion doped polysilicon films decreases with increasing doping concentration, and increases with increasing <111> texture.

Quality Assurance in Polysilicon Deposition Using Statistics

Keywords: Polysilicon depositionIntegrated circuitsLow-pressure chemical vapor deposition (LPCVD)Taguchi techniquesOrthogonal arraysVariance analysis (ANOVA)Variability reductionControl chartsMoving-range charts

Characterization of chemically vapor deposited tungsten on low-pressure chemically deposited and reactively sputtered titanium nitride films

The growth of low-pressure chemical vapor deposition (LPCVD) tungsten on LPCVD-grown and reactively sputtered titanium nitride (TiN) films has been studied employing the x-ray photoelectron spectroscopy depth profiling technique. Two types of gas ambients were used to grow tungsten (W) films at a deposition temperature of 400 °C. In one case, a very thin overlayer of W was formed on both types of TiN films by exposing the samples to WF6. The W thus deposited diffuses deep into the bulk of the reactively sputtered TiN film whereas it is confined to the W/TiN interface for the LPCVD-grown TiN film. In the second case, both types of TiN films were exposed to the WF6, SiH4, and H2 ambient. No diffusion of W into any of the TiN films was observed.

Si/SiGe/Si heterostructure growth without interface roughness at high germanium mole fractions by low temperature low pressure chemical vapour deposition

A new low temperature low pressure chemical deposition process for Si/SiGe/Si heterostructures containing high germanium mole fractions has been developed. The silicon surface and the SiSiGe interface roughness strongly depend on the deposition temperature and the germanium concentration. For germanium concentrations around 20%, flat surfaces can be realized at 550 °C. High concentrations of more than 50% Ge require much lower growth temperatures, namely 450 °C for SiGe and 525 °C for the silicon capping layer. A new optimized process sequence is given to grow Si/SiGe/Si heterostructures with atomically flat surfaces and interfaces containing more than 50% Ge.

The growth of polycrystalline silicon films by low pressure chemical vapour deposition at relatively low temperatures

Low pressure chemical deposition at relatively low temperatures carried out by using silane pressures below 100 mTorr leads to structurally well-defined films. Below 10 mTorr the films are characterized as resulting from local epitaxial processes. Deposition on amorphous substrates leads to columnar growth with a (100) preferred orientation with the grains misaligned, thus forming grain boundaries, while with natural seeding the films grow epitaxially. The effective mobility and the threshold voltage of thin film transistors fabricated from these films indicate that they are advantageous over amorphous films.

Erratum: Low-temperature epitaxial growth of silicon by low-pressure chemical vapor deposition [Appl. Phys. Lett. 5 2, 1053 (1988)

Low-pressure chemical deposition of silicon by the pyrolysis of pure silane at relatively low temperatures and pressures below 100 mTorr can lead to structurally well-defined films. Below 10 mTorr the films exhibit evidence of local epitaxial growth, which can be particularly well defined on Si(100) wafers chemically treated prior to deposition outside the deposition chamber. Even so, the interface was found to be highly strained, and high-resolution electron microscopy observations were used to analyze the defect structures in the epitaxial layer as initiated at the interface.

Low-temperature epitaxial growth of silicon by low-pressure chemical vapor deposition

Low-pressure chemical deposition of silicon by the pyrolysis of pure silane at relatively low temperatures and pressures below 100 mTorr can lead to structurally well-defined films. Below 10 mTorr the films exhibit evidence of local epitaxial growth, which can be particularly well defined on Si(100) wafers chemically treated prior to deposition outside the deposition chamber. Even so, the interface was found to be highly strained, and high-resolution electron microscopy observations were used to analyze the defect structures in the epitaxial layer as initiated at the interface.