Low Power VLSI Design Research Articles

Gate all around carbon nanotube field effect transistor espoused discrepancy cascode pass transistor adiabatic logic for ultra-low power application

Advances in wearable technology, IoT, and mobile applications have increased the demand for ultra-low-power electronic devices. Adiabatic Logic Circuit (ALC) is a design technique utilized in digital circuits to decrease the power consumption by decreasing the dynamic power dissipation. Current technologies face challenges in achieving both high performance and ultra-low power consumption. This research work introduces a novel approach in digital circuit design, specifically the Gate All-around Carbon Nanotube Field Effect Transistor with Discrepancy Cascode Pass Transistor Adiabatic Logic (GAA-CNTFET-DCPTAL), tailored for ultra-low power applications. This design operates efficiently with a four-phase Power Clock (PC) and demonstrates remarkable performance by achieving operation frequencies of up to 1 GHz while minimizing energy dissipation. GAA-CNTFET provides superior electrostatic control and high carrier mobility, reducing leakage currents and enhancing switching speeds. Simultaneously, Discrepancy Cascode Pass Transistor Adiabatic Logic (DCPTAL) uses adiabatic logic principles and a cascode structure to minimize energy dissipation during switching events. The technology node of proposed model is 10 nm. The software used for assessment is HSPICE is used for the simulation and validation of the proposed design. The proposed GAA-design attains 25.36 %, 14.28 %, and 16.06 % lower average power analyzed with existing techniques, such as Design with Evaluation of Clocked Differential Adiabatic Logic Families for the applications of low Power (DE-CDAL-LPA), Adiabatic logic-base strong ARM comparator for ultra-low power applications (AL-SARM-ULPA) and Analysis of 2PADCL Energy Recovery Logic for Ultra Low Power VLSI Design for SOC with Embedded Applications (2PADCL-ULP-VLSI) respectively.

DESIGN AND ANALYSIS OF NOVEL PARALLEL PREFIX ADDERS FOR VLSI CIRCUITS

Arithmetic Logic Unit is the brain of all processors, is composed of an Adder circuit. The main component of multiplier circuits is the adder, which performs subtraction (by 2’s complement arithmetic). Since the most fundamental operation in mathematics is addition, and the adder is the most essential part of the processor, the study of VLSI arithmetic has required many digital VLSI researchers. When designing digital systems employing the VLSI approach, the digital adder plays a major role. Low power VLSI based adder designs perform poorly because of the propagation delay issue. With the aid of the PPA design, an assessment of adders’ availability for low power VLSI designs with minimal propagation delay is conducted. Using these performance measures, this study compares and evaluates the performance of several parallel prefix adders, allowing readers to select the optimum adder architecture for their application Specific Integrated Circuits implementations. The three adder topologies taken into considered in this Article include the Han carlson adder, Brent kung, Kogge stone adders. Xilinx ZYNQ XC7Z020 (7000 series) SoC is used to implement the adders using the Vivado Design Suite 2014 and Verilog.

Design and Implementation of CMOS and Transmission Gate Based Full Adder Using 45nm Technology

Abstract: In electronic industry the level of integration is an important aspect as it makes the electronic device simpler and more reliable. The device density increases with the better level of integration. Power dissipation, Area occupied, and Propagation delay are some of the important factors that need to be considered. These parameters play a vital role in manufacturing portable electronic gadgets. Many binary adders are formed using full adders. Hence, if any enhancements have to be made to improve the performance, it can be made at the root level i.e., adders circuits itself. This in turn helps in bettering the performance of the electronics circuits which follow adder circuits. The low power VLSI design is of great importance due to portable electronic products. Full adder is a type of adder circuit that adds three inputs and gives two outputs. Out of three, two will be the present inputs and the third input will be the carry from the previous stage. ‘A’ and ‘B’ are the actual inputs, ‘C’ is the carry from the previous operation. SUM and CARRY OUT are the two outputs. In this work, Design and Implementation of full adder using conventional CMOS design and Transmission gate based Full adder circuits are carried out. At last comparison is made between the two designs with respect to power dissipation, delay and area (number of transistors). Cadence Virtuoso Tool is used in design and simulation conventional CMOS design and Transmission gate based Full adder circuits. The entire circuit is simulated in Cadence Tools at 45nm CMOS process.

Implementation and Analysis of CMOS and Pass Transistor Logic Based Full Adder Circuits

Abstract: In electronic industry the level of integration is an important aspect as it makes the electronic device simpler and more reliable. The device density increases with the better level of integration. Power dissipation, Area occupied and Propagation delay are some of the important factors that need to be considered. These parameters play a vital role in manufacturing portable electronic gadgets. Many binary adders are formed using full adders. Hence, if any enhancements have to be made to improve the performance, it can be made at the root level i.e., adders circuits itself. This in turn helps in bettering the performance of the electronics circuits which follow adder circuits. The low power VLSI design is of great importance due to portable electronic products. Full adder is a type of adder circuit that adds three inputs and gives two outputs. Out of three, two will be the present inputs and the third input will be the carry from the previous stage. ‘A’ and ‘B’ are the actual inputs, ‘C’ is the carry from the previous operation. SUM and CARRY OUT are the two outputs. In this work, Design and Implementation of full adder using conventional CMOS design and Pass Transistor Logic based Full adder circuits are carried out. At last comparison is made between the two designs with respect to power dissipation, delay and area (number of transistors). Cadence Virtuoso Tool is used in design and simulation conventional CMOS design and Pass Transistor Logic based Full adder circuits. The entire work is simulated in 180nm CMOS technology.

Review on Reversible Logic Gates

Abstract: Reversible logic gates have emerged as a pivotal area of research in the field of digital circuit design, offering the promise of ultra-low power consumption. This survey paper comprehensively explores the foundations and practical applications of reversible logic gates. Beginning with an introduction to the fundamental principles of reversibility, it delves into the design of reversible gates, covering CNOT, Feynman, Toffoli, Peres, Fredkin gates, and beyond. The paper offers a systematic review of state-of-the-art research in the field, discussing various optimization techniques and quantum-inspired reversible circuits. It also investigates real-world applications, ranging from low-power VLSI design to quantum computing. By summarizing the key findings, challenges, and potential future directions in reversible logic gate design, this survey paper provides a valuable resource for researchers, engineers, and enthusiasts seeking a comprehensive understanding of this transformative technology

A novel approach for design energy efficient inexact reverse carry select adders for IoT applications

Low cost, low form factor and highly energy efficient VLSI design is the key for the success of internet of things (IoT) paradigm. Approximate computing is one of the major techniques used to achieve high performance and energy efficiency in error resistant computationally intense applications. Low power VLSI design is one of the important factors in the designing of new IoT system or reconstructing the existed IoT system. An inexact reverse carry select adder (IRCSLA) with back carry propagation is presented in this work. Three different types of adder implementations were presented in IRCSLA. The method of back carry propagation is applied to the design of both 16-bit ripple carry adder (RCA) & 16-bit carry select adders. These adders were designed in CADENCE schematic tool and simulations were done in Analog Design Environment with 45 nm CMOS technology. The design parameters such as delay and power of the three IRCSLA designs were compared with the existed back carry propagate full adders. IRCSLA-III gives 34.84% reduction in power and 56.91% improvement in delay compared to conventional CSLA adder and also improves the energy at the rate of 86.77% and 71.92% compared to the conventional RCA and a CSLA adder respectively.

A Low Power High Speed Accuracy Controllable Approximate Multiplier Design

Abstract: For energy effective and high performance design, the low power VLSI circuit is used. Multiplier is an essential part of low power VLSI design, since the effectiveness of the digital signal processor depends upon the multiplier. In multiplier circuit, utmost of the power is dissipated across in full adder circuits. Multiplication is one of the important process in microprocessor and there will be a lot of delay because of array multiplier, which can be compressed with the help of the column compressor approach. It uses a selection of half adders, full adders and compressors to sum the partial products in stages until two numbers are left. An 8 * 8 and 16 * 16 bit multiplier design is executed by assigning the adder and compressor. Partial product totality is the speed limiting operation in multiplication due to the propagation detention in adder networks. In order to reduce the propagation detention, compressors are introduced. Compressors calculate the sum and carry at each position concurrently. The attendant carry is added with a advanced significant sum bit in the coming stage. This is continued until the final product is generated. The partial product tree of the multiplier is estimated by the proposed tree compressor ( High Speed Compressor, Dual Stage Compressor, Exact Compressor). Keywords: Partial Products, Half Adder, Full Adder, High Speed Compressor, Dual Stage Compressor, Exact Compressor.

Enhanced Clock Gating Technique for Power Optimization in SRAM and Sequential Circuit

Low power VLSI designs are having wide variety of application usage in real-time. VLSI circuits are analyzed with various power reduction strategies. Existing approaches are used the clock frequency control, switching activity and scaling factor for power reduction. The glitching problem and clock triggering issues are higher therefore; the proposed work utilized the improved circuit of clock gating technique. In this proposed work, the enhanced clock gating with D-latch model is constructed to obtain the less power consumption. The traditional clock gating technique is improved by adding clock triggering on LATCH circuit and adding buffer circuit between the source and load circuitry to reduce the clock switching issues like gitching and clocking activity. Here the SRAM and sequential counter circuits are designed to utilize the power reduction strategy for improving the performance. This is applicable for various applications in real world and utilizing the FPGA and DSP application specific circuits. Experimental results are analyzed to obtain the power reduction result of SRAM and sequential circuit. Area, power, and delay are obtained the better results as compared with the previous work. Overall, design is performed using Xilinx 14.2 ISE suit.

Low Power VLSI Design Techniques: A Review

Since CMOS technology consumes less power it is a key technology for VLSI circuit design. With technologies reaching the scale of 10 nm, static and dynamic power dissipation in CMOS VLSI circuits are major issues. Dynamic power dissipation is increased due to requirement of high speed and static power dissipation is at much higher side now a days even compared to dynamic power dissipation due to very high gate leakage current and subthreshold leakage. Low power consumption is equally important as speed in many applications since it leads to a reduction in the package cost and extended battery life. This paper surveys contemporary optimization techniques that aims low power dissipation in VLSI circuits.

A Survey on Low Power Design Approaches in Nanoscale Regime

Background: The increased demand for battery operated portable systems boost up the field of low power VLSI design. Integrated circuits are enhancing the performance of the systems in terms of lesser area requirement, higher functionality, and faster response at lower technology nodes. The applied power supply and the threshold voltage of the individual device are scaled down at lower technology node. Scaling of the threshold voltage of the devices raises the issue of leakage current. Objective: Leakage current should be made recessive with the continuous scaling of technology nodes. Methods: Various leakage current mitigation methods had been employed to reduce the leakage current at different abstraction levels. This review paper demonstrates the survey of systematic arrangement of device scaling, leakage power, its causes, and various methods to overcome the leakage current at circuit level design. Results: 3 input NAND (NAND3) gate is designed and simulated at 22 nm technology node on HSPICE tool and analyzed for comparison of different leakage reduction techniques. Conclusion: INDEP approach is the most effective approach to reduce the leakage current and to improve the reliability of the circuits followed by DTCMOS technique as compared to other available techniques.

New Carry Maskable Adder using Modified Full Swing GDI

Addition is an essential arithmetic operation that is used extensively in processing of digital information. Now a days approximate computing is emerging methodology in area of low power VLSI design that trades off accuracy for faster and power efficient designs. Accuracy Configurable Approximate Adders is an attractive option that provides a flexibility to user to configure adder as accurate or approximate. This paper presents a new Carry Maskable Adder realization based on Full Swing-Modified Gate Diffusion Input (GDI) technique. Proposed design is functionally verified through simulations in LTspice XVII. The performance comparison of proposed design with CMOS based counterpart show that the percentage reduction in delay is 32% while power consumption is reduced by 45%.

An elegance of novel digital filter using majority logic on pipelined architecture for SNR improvement in signal processing

VLSI is an enduring technology which is used to change the entire digital element into autonomy, some real-time opportunities are characterized under Very Large Scale Integration such as low power application, testing, MOS technology etc. This research focused on signal processing in low power VLSI design, in existing system the backend IC fabrication process illustrates system-level design by using digital logic elecment. An existing digital element consist of different functions of adders such as carry select, ripple carry adder, carry skip adder, carry look ahead adder, which has consume more area, delay, and power. To improve the efficiency of digital design a novel majority carry save adder is proposed and incorporate with a structured tree multiplier, this research produce an optimized carry save adder design in digital filter for improve the signal to noise ratio. The proposed innovative carry save adder is constructed by using majority logic and implemented into a digital FIR filter, this new technique consumes low power, delay-free carry circuit and less number of gate counts. The proposed adder has achieved 96 % efficiency in terms of gate count, delay, and power compared with existing analysis. Digital system design produces 83.5 % efficiencyin an existing system and it required the maximum number of gate count and an increasing number of delays when compared with recent research. The design summary is analyzed by using XILINX 14.7 ISE synthesis and the implementation process is highly reached with the help of MATLAB 2018a. The proposed design is implemented into Biomedical Application for reducing noise and improving signal to noise ratio.

Design and vlsi implementation of a decimation filter for hearing aid applications

Roughly 10% of the total common people experience some kind of hearing misfortune, yet just little level of this measurement utilize the portable amplifier. The shame related with wearing a portable amplifier, client disappointment with listening device execution, the expense and the battery life. Using computerized signal handling the advanced portable amplifier currently offers what the simple listening device can't offer. As of now low power VLSI design is more preferable in digital designs. More and more individuals around the globe experience the ill effects of hearing misfortunes. The expanding normal age and the developing populace are the principle explanations behind this. The pulverization channel utilized for portable amplifier is planned and executed both in MATLAB and Very High Speed Integrated Circuit Hardware Description Language. The obliteration channel is structured utilizing the circulated number-crunching multiplier in Very High Speed Integrated Circuit Hardware Description Language. Each computerized channel structure is reproduced utilizing Matlab and its total engineering is caught utilizing Simulink. The subsequent engineering is equipment productive and expends less force contrasted with traditional decoding channels. Contrasted with the decoding FIR-FIR engineering, the structured decoding channel design utilizing Comb-half band FIR-FIR adds to an equipment sparing and decreases the force scattering.

The power-delay product and its implication to CMOS Inverter

Due to power dissipation has always been a significant standard for low power VLSI design, as a parameter that could reflect both circuit power consumption and delay, Power-Delay Product is of great research value. This paper mainly explores the working principle of CMOS inverter, and the definition, and formation causes of PDP. Two experiments were designed based on LTspice for investigating the effect of width to length ratio of the channel of transistors and the stack approach on the propagation delay and dynamic dissipation of CMOS inverter. It is verified that the propagation delay of the inverter is just related to the ratio of the width of the channel between NMOS and PMOS transistors. It is also verified that the range of ratios of the width of the channel between two transistors which makes the propagation delay and PDP minimum is 2∼4, and the stack approach could reduce the PDP in the CMOS inverter effectively.

A power efficient delta-sigma ADC with series-bilinear switch capacitor voltage-controlled oscillator

In low-power VLSI design applications non-linearity and harmonics are a major dominant factor which affects the performance of the ADC. To avoid this, the new architecture of voltage-controlled oscillator (VCO) was required to solve the non-linearity issues and harmonic distortion. In this work, a 12-bit, 200MS/s low power delta-sigma analog to digital converter (ADC) VCO based quantizer was designed using switched capacitor technique. The proposed technique uses frequency to current conversion technique as a linearization method to reduce the non-linearity issue. Simulation result show that the proposed 12-bit delta-sigma ADC consumes the power of 2.68 mW and a total area of 0.09 mm² in 90 nm CMOS process.

Effects analysis of bias and excitation conditions on power output of an environmental vibration energy harvesting device using Fe-Ga slice

With the advent of low power VLSI designs and the mass manufacture of CMOS, the power consumption of wireless sensor nodes has been significantly reduced from mW to μW. This opens up a new and interesting research field, that is, the possibility of converting environmental vibration energy to electrical energy for supplying power to the sensors. In this paper, using magnetostrictive materials slice, that is Fe-Ga alloy, a device for harvesting environmental vibration energy is designed and tested. Compared with piezoelectric materials and Terfenal-D alloy, Fe-Ga alloy offers excellent properties for surviving in tough ambient vibration conditions, including higher energy conversion efficiency, longer life cycles, excellent toughness, reduced depolarization and higher flexibility, etc. The designing of vibration energy harvesting process is based on the coupling characteristics of magnetostrictive inverse effect and Faraday electromagnetic induction. The device consists of a Fe-Ga alloy cantilever beam with a magnetostrictive direction throughout the length. It has magnetostrictive inverse effect during vibration and the internal magnetization state will change. A cantilever beam is surrounded by a pickup coil and voltage is induced due to the magnetic field according to Faraday's law. The energy conversion principle among mechanical, magnetic and electric energy is described through a dynamic equation of motion and in conjunction with an electromagnetic conversion equation. The influence law of bias and excitation conditions on output voltage, power and other characteristics of device are investigated in comprehensive experiments. By knowing these influence laws, it is possible to choose an appropriate number of pick up coil for a definite load resistance, to set an appropriate working frequency range, pre-tightening force and pre-magnetized magnetic field such that a maximum power can be harvested. The results derived here can be used as a design guideline for future studies in optimal design and the modeling of vibration energy harvester and force sensor.

Encoding Schemes for Reducing Transition Activity and Power Consumption in VLSI Interconnects-A Review

Low power design is a foremost challenging issue in recent applications like mobile phones and portable devices. Advances in VLSI technology have enabled the realization of complicated circuits in single chip, reducing system size and power utilization. In low power VLSI design energy dissipation has to be more significant. So to minimize the power consumption of circuits various power components and their effects must be identified. Dynamic power is the major energy dissipation in micro power circuits. Bus transition activity is the major source of dynamic power consumption in low power VLSI circuits. The dynamic power of any complex circuits cannot be estimated by the simple calculations. Therefore this paper review different encoding schemes for reduction of transition activity and power dissipation.

A Review on Architecture of Low Power VLSI Design

A Review on Architecture of Low Power VLSI Design

Optimized designs of reversible arithmetic logic unit

Reversible logic has emerged as a promising paradigm in various domains, such as low power VLSI design, quantum cellular automata, and nanotechnology-based systems. The arithmetic logic unit (ALU) is one of the main components of any central processing unit. In this paper we propose two new reversible ALUs using elementary quantum gates, with more functions compared to the existing designs. The results show that the proposed designs are better than the existing counterparts in terms of cost-metrics and the number of functions generated. The proposed reversible ALUs can be used in the implementation of quantum computers. All the designs are with nanometric scales.

Optimised reversible divider circuit

Reversible logic has received a great deal of attention from many researchers over recent years for its enormous potential for application in quantum computing and nanotechnology due to its ability to reduce power consumption, which is the main requirement in low power VLSI design. In this study, first, we have presented new reversible blocks. These circuits can be used for the design of a large and complex combinational circuit. Then, we presented optimised designs for the various reversible components: multiplexers, registers, and shift registers. We will put forward the design and evaluation of optimised reversible division hardware to submit an application of reversible logic design. The comparative results show that the proposed designs individually have less hardware complexity, garbage outputs, constant inputs, quantum cost and significantly better scalability than the existing works. We have presented some lower bounds on the cost-metrics for designing the reversible components of the divider circuit.