Low Power Test Pattern Generator Research Articles

An Efficient Implementation of Built in Self Diagnosis for Low Power Test Pattern Generator

A New architecture of Built-In Self-Diagnosis is presented in this project. The logic Built-In-Self-Test architecture method is extreme response compaction architecture. This architecture first time enables an autonomous on-chip evaluation of test responses with negligible hardware overhead. Architecture advantage is all data, which is relevant for a subsequent diagnosis, is gathered during just one test session. Due to some reasons, the existing method Built-In Self-Test is less often applied to random logic than to embedded memories. The generation of deterministic test patterns can become prohibitively high due to hardware overhead. The diagnostic resolution of compacted test responses is in many cases poor and the overhead required for an acceptable resolution may become too high. Modifications in Linear Feedback Shift Register to generate test pattern with security for modified Built-In-Self-Test applications with reduced power requirement. The modified Built-In-Self-Test circuit incorporates a fault syndrome compression scheme and improves the circuit speed with reduction of time.

Implementation of Low Power TPG using LFSR and single input changing generator (SICG) for BIST Application: A Review

3, 4 Abstract: A novel test pattern generator which is more suitable for built in self test (BIST) structures used for testing of VLSI circuits. The objective of the BIST is to reduce power dissipation without affecting the fault coverage. A new low power test pattern generator using linear feedback shift register (LFSR), called LP-TPG, and is presented to reduce the average power and peak power of the circuit by reducing the switching activities during test. In this approach, the single input change patterns generated by a counter and a gray code generator are Exclusive-ORed with the seed generated by the low power linear feedback shift register (LP-LFSR). The proposed scheme is evaluated by using, a synchronous pipelined 4x4 and 8x8 Braun array multipliers. The system-on chip (SoC) approach is adopted for implementation on Xilinx Field Programmable Gate Arrays (FPGAs). From the implementation results, it is verified that the testing power for the proposed method is reduced by a significant percentage.

Design of BIST with Low Power Test Pattern Generator

Design of BIST with Low Power Test Pattern Generator

Design of Low Power Test Pattern Generator using Low Transition LFSR for high Fault Coverage Analysis

A low power Test Pattern Generator (TPG) designed by modifying Linear Feedback Shift Reg ister is proposed to produce low power test vectors that are deployed on Circuit under Test (CUT) to slenderize the dynamic power consumption by CUT. The technique involved in generating low power test patterns is performed by increasing the correlativ ity between the successive vectors; the amb iguity in increasing the similarity between consecutive vectors is resolved by reducing the number of bit flips between successive test patterns. Upon deploying the low power test patterns at the inputs of CUT, slenderizes the switching activities inside CUT that in turn reduces its dynamic power consumption. The resulted low power test vectors are deployed on CUT to obtain fault coverage. The experimental results demonstrate significant power reduction by low power TPG than co mpared to standard LFSR.

LPTest: a Flexible Low-Power Test Pattern Generator

This paper presents a low power test pattern generator, LPTest, that minimizes the peak power consumption during the shift and capture cycles for scan-based stuck-at and transition fault testing. LPTest incorporates both power-aware ATPG and low-power X-filling techniques to achieve higher power reduction. Its enabling technique is a power estimation method which assesses the lower-bounds of the shift-in, shift-out, and capture powers of a partially specified test pattern. The lower-bound estimation method is utilized in LPTest's ATPG engine, dynamic compaction, and X-filling. LPTest has been validated using ISCAS89 benchmark circuits. When considering all cycles, LPTest achieves better than 22% peak WSA (weighted switching activity) reduction for stuck-at and transition faults compared to a commercial ATPG with high merge ratio and random-fill options. Meanwhile, the average power reduction is better than 43%. When only capture power is of concern, LPTest attains more than 46% WSA reduction for stuck-at and transitions.

Low-Power BIST With a Smoother and Scan-Chain Reorder Under Optimal Cluster Size

The authors propose a low-power testing methodology for the scan-based built-in self-test. This approach combines a low-power test pattern generator (TPG) with scan-chain reordering to achieve low-power testing without losing fault coverage. Three main issues are addressed. First, a smoother is included in the TPG to reduce the average power consumption. However, the fault coverage may be adversely affected by the smoother; hence, a cluster-based scan-chain reordering is employed to remedy this problem. If a very-large power reduction is necessary, the fault-coverage drop can become significant. This can be addressed by reseeding. The second topic of this paper is to give a detailed analysis on the optimal cluster size to minimize the scan-chain length. Finally, a fast and efficient algorithm is developed for scan-chain reorder in order to improve the fault coverage. The reordering algorithm is very efficient in terms of computation time, and the routing length of the reordered scan chain is comparable to or smaller than the result given by commercial tools. Experimental results show that the proposed method provides a significant and consistent reduction in the average test power, and the fault coverage is similar to previous methods with the same test lengths

A New Low Power Test Pattern Generator for BIST Architecture

A new low power test pattern generator (TPG) which can effectively reduce the average power consumption during test application is developed. The new TPG reduces the weighted switching activity (WSA) of the circuit under test (CUT) by suppressing transitions at some primary inputs which make many transitions. Moreover, the new TPG does not lose fault coverage. Experimental results on the ISCAS benchmark circuits show that average power reduction can be achieved up to 33.8% while achieving high fault coverage.