Low-power Multimedia Applications Research Articles

A low leakage TG‐CNTFET–based inexact full adder for low power image processing applications

SummaryThis paper presents a highly stable, low leakage inexact full adder (FA) which is based on top gate carbon nanotube field effect transistors (TG‐CNTFET) for motion detector applications. Inexact arithmetic circuits are highly accepted in low power multimedia applications. Circuit level metrics, ie, average power, propagation delay, power‐delay product (PDP), and leakage power dissipation as well as application level metric such as peak signal to noise ratio (PSNR) are considered to compare the performance of proposed inexact FA. All the simulations are performed using HSPICE tool with Stanford 32‐nm TG‐CNTFET model. The operating frequency used for simulation is 1‐Ghz with 0.9‐V supply voltage. Proposed inexact FA successfully achieve manifold reduction in leakage power as well as consume 89.2% lesser energy as compared with latest existing inexact FA while having other parameters in acceptable range. Simulations using MATLAB show satisfactory image quality and PSNR value for motion detection applications. The effect of variations in voltage and temperature on leakage power is also presented which confirms stability of the proposed circuit.

Dynamic Approximation of JPEG Hardware

JPEG compression based on the discrete cosine transform is a key building block in low-power multimedia applications. Approximate computation techniques are used to exploit the error tolerance of JPEG. An image-dependent framework is proposed in this paper to design optimized approximate hardware with variable approximate bit-widths for a user-specified error budget. The proposed method can dynamically adjust the extent of approximation in the system depending on the pixel values of the input image, thus leveraging the inherent sparsity of certain images. This novel technique not only improves the power-delay product by $3.4{\times }$ over the base case, i.e., where the JPEG hardware is accurate but also significantly outperforms the image-independent approximation case, which is solely based on the error tolerance of the JPEG algorithm.

Fast reference frame selection based on content similarity for low complexity HEVC encoder

The high efficiency video coding (HEVC) is the state-of-the-art video coding standard, which achieves about 50% bit rate saving while maintaining the same visual quality as compared to the H.264/AVC. This achieved coding efficiency benefits from a set of advanced coding tools, such as the multiple reference frames (MRF) based interframe prediction, which efficiently improves the coding efficiency of the HEVC encoder, while it also increases heavy computation into the HEVC encoder. The high encoding complexity becomes a bottleneck for the high definition videos and HEVC encoder to be widely used in real-time and low power multimedia applications. In this paper, we propose a content similarity based fast reference frame selection algorithm for reducing the computational complexity of the multiple reference frames based interframe prediction. Based the large content similarity between the parent prediction unit (Inter_2N×2N) and the children prediction units (Inter_2N×N, Inter_N×2N, Inter_N×N, Inter_2N×nU, Inter_2N×nD, Inter_nL×2N, and Inter_nR×2N), the reference frame selection information of the children prediction units are obtained by learning the results of their parent prediction unit. Experimental results show that the proposed algorithm can reduce about 54.29% and 43.46% MRF encoding time saving for the low-delay-main and random-access-main coding structures, respectively, while the rate distortion performance degradation is negligible.

Embedded network camera processor system on a chip for various low-power multimedia applications

In this paper we present an embedded network camera processor (NCP) system on a chip (SoC) for various low-power multimedia applications. The NCP SoC comprises a digital camera processor optimized for a CCD sensor, a motion JPEG encoder to compress the data, an Ethernet controller to transmit the data, ARM processor and many peripherals. Using the NCP SoC allows the raw image from a CCD sensor to be filtered, compressed and transmitted anywhere through various Ethernet protocols, with no additional hardware. The NCP SoC is designed with Verilog-HDL. Also, we followed a strict ASIC flow including functional behavior verification and a scan test. The NCP SoC is fabricated with 0.25 $${\upmu }{\text {m}}$$μm CMOS technology. The total chip size, including embedded memory, is $$7800\times 7800\,{\upmu }{\text {m}}^{2}$$7800×7800μm2 and the gate count is 1.2 million. The NCP SoC runs at up to 48 MHz, and supports various slower clock frequencies for low-power applications requiring additional power saving modes: 6 MHs, 12 and 24 MHz at 2.5 V.

An optimal speed control scheme supported by media servers for low-power multimedia applications

In this paper, we present a new concept of dynamic voltage scaling (DVS) for low-power multimedia decoding in battery-powered mobile devices. Most existing DVS techniques are suboptimal in achieving energy efficiency while providing the guaranteed playback quality of service, which is mainly due to the inherent limitations of client-only approaches. To address this problem, in this paper, we investigate the possibility of media server supported DVS techniques with smoothing mechanisms. Towards this new direction, we propose a generic offline bitstream analysis framework and an optimal speed control algorithm which achieves the maximal energy savings among all feasible speed profiles for the given buffers. The proposed scheme enables us to compute the buffer sizes of feasibility condition, which are the theoretical lower bound of buffer size requirement for a given media clip. More importantly, our scheme facilitates practical applications from four aspects. First, it does not require feedback information on clients’ configuration. This renders our scheme particularly suitable for broadcast or multicast applications. Second, the speed profile based on buffer sizes of feasibility condition can provide satisfactory energy efficiency. Third, the required buffer sizes are so small that they can be met by most mobile devices. Fourth, additional side information (i.e., speed profile) of the proposed scheme is negligible compared to the size of media content. These properties solve the diversity issue and feasibility issue of media server supported DVS schemes. Experimental results show that, in comparison with the representative existing techniques, our scheme improves the performance of DVS significantly.

A 10b 100 MS/s 1.4 mm256 mW 0.18 m CMOS A/D Converter with 3-D Fully Symmetrical Capacitors

This work proposes a 10b 100 MS/s 1.4 mm 2 CMOS ADC for low-power multimedia applications. The proposed two-step pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The wide-band SHA employs a gate-bootstrapping circuit to handle both single-ended and differential inputs of 1.2 Vp-p at lOb accuracy while the second-stage flash ADC employs open-loop offset sampling techniques to achieve 6b resolution. A 3-D fully symmetrical layout reduces the capacitor and device mismatch of the first-stage MDAC. The low-noise references are integrated on chip with optional off-chip voltage references. The prototype 10b ADC implemented in a 0.18 μm CMOS shows the maximum measured DNL and INL of 0.59LSB and 0.77LSB, respectively. The ADC demonstrates an SNDR of 53.7 dB, an SFDR of 61.5 dB, and the power dissipation of 56 mW at 100 MS/s.

Dynamic voltage scheduling with buffers in low-power multimedia applications

Power-efficient design of multimedia applications becomes more important as they are used increasingly in many embedded systems. We propose a simple dynamic voltage scheduling (DVS) technique, which suits multimedia applications well and, in case of soft real-time applications, allows all idle intervals of the processor to be fully exploited by using buffers. Our main theme is to determine the minimum buffer size to maximize energy saving in three cases: (i) single task, (ii) multiple subtask, and (iii) multitask. We also present a technique of adjusting task deadlines for further reducing energy consumption in the multiple-subtask and multitask cases. Unlike other DVS techniques using buffers, we guarantee to meet the real-time latency constraint. Experimental results show that the proposed technique does indeed achieve significant power reduction in real-world multimedia applications.

ENERGY-CONSTRAINED VDD HOPPING SCHEME WITH RUN-TIME POWER ESTIMATION FOR LOW-POWER REAL-TIME VLSI SYSTEMS

In this paper, we propose a novel dynamic voltage scaling algorithm on a variable-voltage processor. It determines the supply voltage on timeslot-by-timeslot basis within the task boundary, and significantly reduces the power consumption by fully exploiting the slack time. Also, we modify this algorithm and propose an energy-constrained dynamic voltage scaling algorithm for low-power multimedia applications. In the multimedia applications, there are usually several alternative algorithms with different performance and power. Considering the trade-off between performance and power, the proposed algorithm adaptively determines the optimal alternative to achieve optimal performance under given energy constraint. Compared with the conventional algorithms, the power consumption is reduced to 1/14.4 ~ 1/5.6 without performance degradation.