Low-Power High-Speed Multiplier Research Articles

DESIGN AND ANALYSIS OF LOW-POWER, HIGH-SPEED BAUGH WOOLEY MULTIPLIER

The fundamental operations of the communication are the multiplication and division. The multiplier usually consumes a larger area and power and poses a very high latency. As all the above mentioned characteristics of the multiplier depends on the techniques utilized for the multiplication. It becomes necessary to put into effect a proper multiplier that reduces both the latency and the power consumption. So the paper analysis the performance of the various multipliers and scopes to develop a low power high speed multiplier based on the Baugh Wooley algorithm. The Performance analysis of the Baugh Wooley multiplier and the other existing multipliers is done and was found that the performance of the Baugh Wooley in terms of the latency and the power consumption was convincing compared to the other existing methods.

Low Power High Speed Multiplier Design based on MTCMOS Technique

Low Power High Speed Multiplier Design based on MTCMOS Technique