Low Power Full Adder Circuit Research Articles

DESIGN SPACE EXPLORATION OF LOW POWER FULL ADDER ACROSS MULTIPLE LOGIC STYLES AND PROCESS

The signal processing in digital domain becoming ubiquitous, a full adder circuit module has gained prominence for its optimization in terms of its speed, power dissipation, noise margin and area. Further, with the advent of mobile applications on electronic devices, low power has emerged as an overriding design criterion. The proposed work aims to explore the design space of a low power full adder circuit and the implications of logic styles on power-delay trade-offs. Further, the issues impacting the selection of process for design for a given application are addressed. A 1-bit full adder circuit in static CMOS logic style and hybrid logic style is designed and optimized for low-power by carrying out exhaustive simulations using the LT spice simulator in 65 nm and 45 nm standard process to explore their power envelope, before low power process becomes necessary for design. Low power designs are demonstrated and the trade-offs with speed and area are explored.

CNFET Based Low Power Full Adder Circuit for VLSI Applications

Background: The Adder is one of the most prominent building blocks in VLSI circuits and systems. Performance of such systems depends mostly on the performance of the adder cell. The scaling down of devices has been the driving force in technological advances. However, in CMOS technology performance of adder cell decreases as technology node scaled down to deep micron regime. Objective: With the growth of research, new device model has been proposed based on carbon nano tube field effect transistor (CNFET). Therefore, there is a need of full adder cell, which performs sufficiently well in CNFET as well as different CMOS technology nodes. Method: A new low power full adder cell has been proposed with a hybrid XOR/XNOR module by using CNFET, which is also compatible for the CMOS technology nodes. The performance of the adder cell is validated with HSPICE simulation in terms of power, delay and power delay product. It is observed that the proposed adder cell performs better than the CMOS, CPL, TGA, 10 T, 14 T, 24 T, HSPC and Hybrid_FA adder cells. The CNFET full adder is designed in 32 nm CNFET model and to appraise its compatibility with Bulk-Si CMOS technology, 90 nm and 32 nm CMOS technology node is used. Conclusion: The proposed adder is very much suitable for both CMOS and CNFET technology based circuits and systems. To validate the result, simulation has been carried out with Synopsis tool. This full adder will definitely dominate other full adder cells at various technology nodes for VLSI applications.

A novel energy-efficient and high speed full adder using CNTFET

In the present paper, we will present two high speed, energy efficient and low power full adder circuits using gate diffusion input (GDI) cell, semi XOR/XNOR modules and carbon nanotube field effect transistors (CNTFET). Due to unique electrical and mechanical features of CNTFET, it can be chosen as an appropriate alternative to replace the metal oxide field effect transistors (MOSFET). In order to evaluate several figures of metric (FOM) including power consumption, energy consumption, propagation delay and energy delay product (EDP) using different voltage supplies, load capacitances, temperatures, frequencies and tubes, extensive experiments of proposed designs and previous works will be presented. Comparing to the previous works, simulation results of HSPICE illustrate the superiority of proposed designs regarding propagation delay and EDP.

Performance Analysis of Full Adder Circuit using Double Gate MOSFET

paper presents a design of a one bit full adder cell based on stack effect using Double Gate MOSFET. This design has been compared with existing one-bit full adder which is designed using power gating technique. In this paper, the proposed circuit has been analyzed for parameters like- power consumption and power delay product. The simulations of the proposed Full Adder have been performed using Tanner EDA Tool version 13.0. All the proposed design simulations are carried out at 45nm technology for various inputs like supply voltage and input voltage. The decrease of 99.5% in power utilization has observed in proposed circuit. The results show a legality of double gate MOSFETs for designing for low power full adder circuit. KeywordsAdder; Stack effect; Double Gate; Low Power; PDP ; power gating

Design of high-performance low-power full adder

Full adder is an essential component for the design and development of all types of processor. This project introduces the design of high-performance low-power full adder which acquires least area with the lowest transistor count. The high-performance low-power full adder is designed and the implementation of a 32-bit ripple carry adder based on high-performance low-power full adder circuit is described, and comparison is made with other previously designed full adders. The high-performance low-power full adder circuit is designed and the simulation has been carried out on Tanner EDA tool. The result shows that the proposed high-performance low-power full adder is an efficient full adder cell with least MOS transistor count that reduces the high power consumption and considerably increases the speed.