Low Power Finite Impulse Response Research Articles

Power Minimization by Designing Novel Architecture for Multimodal Biometric System

Abstract: The reduction of power, area, and delay parameters are increasing as the range of sophistication of applications in VLSI circuit designs. Adders and multipliers play a vital role in VLSI circuit designs to minimize the power consumed by the circuit. The Finite Impulse Response Filter is widely used in Digital Signal Processing Applications, such as speech processing, loudspeaker equalization, echo cancellation, noise cancellation, arithmetic computations and, image-processing applications. In FIR filter, the adders and multipliers are the important components to reduce the power, delay and area. Therefore, this proposed method faced with more constraints: as minimal power as possible. This work proposes a design of low power Finite Impulse Response Filter using Carry Skip Adder.The recent electronics industry uses digital filters for various real time applications. A novel VLSI architecture is designed by using ALU based FIR filters for biometric system. Where in ALU includes adders and multipliers, comparing different adders for there better performance with respect to power and identifying carry skip adder will consume less power compared to other adders. power consumption of overall architecture by including carry skip adder is very less and we can use this same adder for multimodal architecture also.

Energy Efficient FIR Filter for Biomedical Application using FPGA

This research work proposes a low power Finite Impulse Response (FIR) digital filter system using Field Programmable Gate Array (FPGA) to filter biomedical signals. A major issue regarding such implementations is associated with computational complexity that may hinder its practical application. Several researches that aim to overcome this problem have been found by using various designs like booth multiplier, distributive arithmetic design, reduce adder graph (RAG), common sub-expression elimination method etc. This work has achieved the target of power line frequency of 50Hz noise cancellation. It is shown that the proposed design using RAG can give faster speed and require less hardware resources than that for the Direct Structure-I design. The performance of the proposed method is also compared with several existing research works to study its efficacy and it is shown that proposed design can achieve nearly 2% area delay product and 43% less power consumptions in implementation of an FIR low-pass filter. The designed filter is also tested on ECG waves as example of biomedical signal from samples of the MIT-BIH Arrhythmia database corrupted with power frequency noise. The entire system has been implemented on the ALTERA DE-II FPGA education board by synthesizing Verilog HDL using Quartus II tool.

A 750-nW 1-MHz 9-tap analog finite impulse response filter for wireless senor network chip

This paper presents a low power Finite Impulse Response (FIR) filter based on discrete-time analog computing. The analog FIR filter is first presented to deal with analog signal. To improve linearity, two-double boost technique is introduced in the sample and hold cells which are used to achieve delay-time function. Meanwhile, the four-quadrant voltage-mode multiplier consists of PMOS substract cell and combiner cell, which is independent of device parameters. To realize the shift registers function, the rotating switch matrix circuit is adopted controlled by phase shift clocks. All MOS transistors implemented in this architecture are biased in subthreshold region with a supply voltage of 0.6 V to reduce the power consumption. Simulation results show that the analog FIR filter dissipates 750 nW at 1 MHz sample frequency and the effective number of bits of the proposed analog FIR filter is more than 7 bits. Compared to the conventional digital FIR filter, power consumption is reduced by 72.22% at 1 MHz in a 0.18μm CMOS process.

Design of Optimized Low Power and Area Efficient Digital FIR Filter using Modified Group Structures based Square Root Carry Select Adder

In Digital Signal Processing, Finite Impulse Response (FIR) filter is mostly used for communications and radar applications. The Performance of FIR filter depends on Multiplier and adder circuits used in filter. To reduce the dynamic power consumption and chip size, different multiplier and adder combinations are used in order to improve the overall performance of FIR filter. The Low Power Modified Square Root Carry Select Adder (M-SQRT CSLA) is presented in this study by introducing half adders instead of full adders. The proposed M-SQRT CSLA has been designed to reduce dynamic power consumption. Hence the modified SQRT CSLA is applied into Wallace multiplier for addition process after the partial product generation stage. MAC unit of the Digital FIR filter is designed by using modified Wallace multipliers and M-SQRT CSLA. Further the Group 2, Group 3; Group 4 and Group5 structures of SQRT CSLA were constructed using half adders only. Comparison between proposed SQRT CSLA and Modified Carry Save Adder (MCSA) has been done with reference to the Area, Power and Delay. It is proved that the proposed SQRT CSLA consumes less area and power than all other methods. Simulation is performed by Modelsim6.3c and Synthesis process is done by Xilinx 10.1. The simulation result shows that digital filter with proposed SQRT CSLA occupies less area and consumes low power.

Low Power Realization and Synthesis of Higher-Order FIR Filters Using an Improved Common Subexpression Elimination Method

The complexity of Finite Impulse Response (FIR) filters is mainly dominated by the number of adders (subtractors) used to implement the coefficient multipliers. It is well known that Common Subexpression Elimination (CSE) method based on Canonic Signed Digit (CSD) representation considerably reduces the number of adders in coefficient multipliers. Recently, a binary-based CSE (BSE) technique was proposed, which produced better reduction of adders compared to the CSD-based CSE. In this paper, we propose a new 4-bit binary representation-based CSE (BCSE-4) method which employs 4-bit Common Subexpressions (CSs) for implementing higher order low-power FIR filters. The proposed BCSE-4 offers better reduction of adders by eliminating the redundant 4-bit CSs that exist in the binary representation of filter coefficients. The reduction of adders is achieved with a small increase in critical path length of filter coefficient multipliers. Design examples show that our BCSE-4 gives an average power consumption reduction of 5.2% and 6.1% over the best known CSE method (BSE, NR-SCSE) respectively, when synthesized with TSMC-0.18 μm technology. We show that our BCSE-4 offers an overall adder reduction of 6.5% compared to BSE without any increase in critical path length of filter coefficient multipliers.

New Distributed Arithmetic Algorithm for Low-Power FIR Filter Implementation

This letter proposes a new distributed arithmetic (DA) algorithm for low-power finite-impulse response (FIR) filter implementation. The characteristic of the proposed algorithm is that the FIR filters using the proposed algorithm do not need to employ two's complement representation in lookup tables as well as multiply-and-accumulation blocks. Thus, the proposed algorithm can minimize the dynamic power consumption of the FIR filters. The experimental results show that the lowpass FIR filter using the proposed algorithm achieves 29% and 26% power consumption reduction compared to that using the conventional algorithm for zero-mean random inputs and speech inputs, respectively.