Low-power Field-effect Transistors Research Articles

Boltzmann Switching MoS2 Metal-Semiconductor Field-Effect Transistors Enabled by Monolithic-Oxide-Gapped Metal Gates at the Schottky-Mott Limit.

A gate stack that facilitates a high-quality interface and tight electrostatic control is crucial for realizing high-performance and low-power field-effect transistors (FETs). However, when constructing conventional metal-oxide-semiconductor structures with two-dimensional (2D) transition metal dichalcogenide channels, achieving these requirements becomes challenging due to inherent difficulties in obtaining high-quality gate dielectrics through native oxidation or film deposition. Here, a gate-dielectric-less device architecture of van der Waals Schottky gated metal-semiconductor FETs (vdW-SG MESFETs) using a molybdenum disulfide (MoS2) channel and surface-oxidized metal gates such as nickel and copper is reported. Benefiting from the strong SG coupling, these MESFETs operate at remarkably low gate voltages, <0.5V. Notably, they also exhibit Boltzmann-limited switching behavior featured by a subthreshold swing of ≈60mVdec-1 and negligible hysteresis. These ideal FET characteristics are attributed to the formation of a Fermi-level (EF) pinning-free gate stack at the Schottky-Mott limit. Furthermore, authors experimentally and theoretically confirm that EF depinning can be achieved by suppressing both metal-induced and disorder-induced gap states at the interface between the monolithic-oxide-gapped metal gate and the MoS2 channel. This work paves a new route for designing high-performance and energy-efficient 2D electronics.

Evolution Application of Two-Dimensional MoS2-Based Field-Effect Transistors

High-performance and low-power field-effect transistors (FETs) are the basis of integrated circuit fields, which undoubtedly require researchers to find better film channel layer materials and improve device structure technology. MoS2 has recently shown a special two-dimensional (2D) structure and superior photoelectric performance, and it has shown new potential for next-generation electronics. However, the natural atomic layer thickness and large specific surface area of MoS2 make the contact interface and dielectric interface have a great influence on the performance of MoS2 FET. Thus, we focus on its main performance improvement strategies, including optimizing the contact behavior, regulating the conductive channel, and rationalizing the dielectric layer. On this basis, we summarize the applications of 2D MoS2 FETs in key and emerging fields, specifically involving logic, RF circuits, optoelectronic devices, biosensors, piezoelectric devices, and synaptic transistors. As a whole, we discuss the state-of-the-art, key merits, and limitations of each of these 2D MoS2-based FET systems, and prospects in the future.

Performance tunability of field-effect transistors using MoS2(1−x)Se2x alloys

Ultra-thin channel materials with excellent tunability of their electronic properties are necessary for the scaling of electronic devices. Two-dimensional materials such as transition metal dichalcogenides (TMDs) are ideal candidates for this due to their layered nature and great electrostatic control. Ternary alloys of these TMDs show composition-dependent electronic structure, promising excellent tunability of their properties. Here, we systematically compare molybdenum sulphoselenide (MoS2( 1−x )Se2x ) alloys, MoS1Se1 and MoS0.4Se1.6. We observe variations in strain and carrier concentration with their composition. Using them, we demonstrate n-channel field-effect transistors (FETs) with SiO2 and high-k HfO2 as gate dielectrics, and show tunability in threshold voltage, subthreshold slope (SS), drain current, and mobility. MoS1Se1 shows better promise for low-power FETs with a minimum SS of 70 mV dec−1, whereas MoS0.4Se1.6, with its higher mobility, is suitable for faster operations. Using HfO2 as gate dielectric, there is an order of magnitude reduction in interface traps and 2× improvement in mobility and drain current, compared to SiO2. In contrast to MoS2, the FETs on HfO2 also display enhancement-mode operation, making them better suited for CMOS applications.

Determination of Hafnium Zirconium Oxide Interfacial Band Alignments Using Internal Photoemission Spectroscopy and X-ray Photoelectron Spectroscopy.

Doped ferroelectric HfO2 is highly promising for integration into complementary metal-oxide semiconductor (CMOS) technology for devices such as ferroelectric nonvolatile memory and low-power field-effect transistors (FETs). We report the direct measurement of the energy barriers between various metal electrodes (Pt, Au, Ta, TaN, Ti/Pt, Ni, Al) and hafnium zirconium oxide (Hf0.58Zr0.42O2, HZO) using internal photoemission (IPE) spectroscopy. Results are compared with valence band offsets determined using the three-sample X-ray photoelectron spectroscopy (XPS) as well as the two-sample hard X-ray photoelectron spectroscopy (HAXPES) techniques. Both XPS and IPE indicate roughly the same dependence of the HZO barrier on metal work function with a slope of 0.8 ± 0.5. XPS and HAXPES-derived barrier heights are on average about 1.1 eV smaller than barrier heights determined by IPE, suggesting the presence of negative charge in the HZO.

Integration of Indium Arsenide/Indium Phosphide Core-Shell Nanowire Vertical Gate-All-Around Field-Effect Transistors on Si

Among the III-V semiconductor materials, indium arsenide (InAs) nanowire (NWs) with high carrier mobility are expected to be alternative channels for high-performance and low-power field-effect transistors (FETs). However, there is a challenge in enhancing the on-state current for the InAs NW-channel vertical gate-all-around (VGAA) structures on Si. We investigated vertical InAs/InP core-shell (CS) NW-channels to enhance the current and demonstrated InAs/InP CS NW VGAA FETs. The InAs/InP CS NW-channel enhanced the on-state current while maintaining a small off-leakage current. The devices showed an on-state current of 40 $\mu \text{A}/\mu \text{m}$ , off-leakage current of 1 pA/ $\mu \text{m}$ , and subthreshold slope of 111 mV/dec at $\text{V}_{\text {DS}} =0.50$ V. The origin of the current enhancement suggests that there is a formation of two-dimensional electron gas (2DEG) in the InAs/InP CS NW-channel, and the characteristics of the InAs/InP CS NW VGAA FET revealed that the InP interlayer at draian edge and low source resistivity are important parameters to take advantage of 2DEG for CS NW VGAA FET.

Current modulation in graphene p–n junctions with external fields

In this work we describe a proposal for a graphene-based nanostructure that modulates electric current even in the absence of a gap in the band structure. The device consists of a graphene p–n junction that acts as a Veselago lens that focuses ballistic electrons on the output lead. Applying external (electric and magnetic) fields changes the position of the output focus, reducing the transmission. Such device can be applied to low power field effect transistors, which can benefit from graphene’s high electronic mobility.

Enhanced performance of In2O3 nanowire field effect transistors with controllable surface functionalization of Ag nanoparticles

Indium oxide (In2O3) nanowire field effect transistors (FETs) have great potential in electronic and sensor applications owing to their suitable band width and high electron mobility. However, the In2O3 nanowire FETs reported previously were operated in a depletion-mode, not suitable to the integrated circuits result of the high-power consumption. Therefore, tuning the electrical properties of In2O3 nanowire FETs into enhancement-mode is critical for the successful application in the fields of high-performance electronics, optoelectronics and detectors. In the work, a simple but effective strategy was carried out by preparing Ag nanoparticle functionalized In2O3 NWs to regulate the threshold voltage (Vth) of In2O3 NW FETs, successfully achieving enhanced-mode devices. The threshold voltage can be regulated from −6.9 V to +7 V by controlling Ag density via deposition time. In addition, the devices exhibited high performance: huge Ion/Ioff ratio > 108, large maximum saturation current ≈ 800 mA and excellent carrier mobility ≈ 129 cm2 Vċs−1. The enhanced performance is attributed to the surface passivation by Ag nanoparticles to reduce the density of traps and the charge transfer between traps and the nanowires to regulate the Vth. The result indicates the application of metal nanoparticles significantly improve oxide NW for low-power FETs.

(Invited) 2D Semiconductors in Large-Area Flexible Opto/Electronics

Successful implementation of two-dimensional layered materials (2DLMs) in opto/electronic applications of the future would require not only the production of high quality materials in large volumes, but also the design of innovative, low power devices that can be implemented onto arbitrary substrate materials, ideally using high-throughput manufacturing paradigms. In this presentation I will discuss the development of low operating voltage 2DLMs-based opto/electronic devices using a combination of self-assembly and top-down manufacturing techniques. Particular emphasis will be placed on the use of adhesion lithography (a-Lith) for the patterning of arbitrary width sub-20 nm nanogaps formed between various dissimilar electrode materials and its combination with 2DLMs for the development of prototype large-area, nano-gap devices including co-planar Schottky diodes, photodetectors, and low-power field-effect transistors.

退火温度对MoS2纳米薄膜特性影响研究

本文主要采用化学气相沉积法，以MoS2饱和溶液为原料，利用氩气为输运气体，携带MoS2蒸汽进入反应室，在Si衬底上制备大面积均匀的MoS2超薄薄膜，并分析了不同的退火温度对于薄膜表面形貌、吸收特性以及电学特性的影响。研究发现，经过850℃退火的二硫化钼薄膜平整，厚度和晶粒尺寸也逐渐均匀。另外，随退火温度升高，MoS2超薄膜反射率降低，可显著提高器件光伏效应和光电转换效率，制备高效率的MoS2/Si异质结太阳能电池。退火还可以改善薄膜的电学特性，经过850℃退火的薄膜，其导电率达到了2.848 × 10-4，霍尔迁移率高达6.42 × 102 cm 2V-1s-1，可用于制造超低待机功率的场效应管。通过分析不同退火温度对纳米MoS2薄膜光电特性的影响，得出纳米MoS2薄膜的最佳退火温度为850℃，这促进了MoS2纳米电子器件的发展，推进了MoS2在光电子领域以及信息技术方面的广泛应用。 Molybdenum disulfide (MoS2) thin films were deposited on Si substrates with MoS2 saturated solution as a raw material carried by argon (Ar) gas by means of chemical vapor deposition. We have analyzed the influence of different annealing temperatures on surface morphology of films, absorption characteristics and electrical properties. We found that MoS2 thin film annealled at 850C was characteristic of more smooth and symmetrical as compared to that of the unannealed sample. At the same time, the optical reflectivity apparently reduced, which indicated that annealing can effectively improve photovoltaic effect and photoelectric conversion efficiency, and can be used for fabricating solar cell. In addition, we found that the electrical properties of MoS2 thin films had also been enhanced after annealing. We noted that the conductivity and the carrier mobility were up to 2.848 × 10-4 and 6.42 × 102 cm 2V-1s-1, when annealing at 850C, which shows promising potential for low power field effect transistor. Analyzing the influence of different an- nealing temperatures on photoelectric properties of MoS2 nanometer thin films, we demonstrated that the best annealing temperature was 850C, which enhanced the applications of MoS2 in the field of photoelectron and information techno- logy.

Valley-based field-effect transistors in graphene

An analog of the Datta-Das spin field-effect transistor (FET) is investigated, which is all graphene and based on the valley degree of freedom of electrons/holes. The ``valley FET'' envisioned consists of a quantum wire of gapped graphene (channel) sandwiched between two armchair graphene nanoribbons (source and drain), with the following correspondence to the spin FET: valley (K and ${K}^{\ensuremath{'}}$) \ensuremath{\leftrightarrow} spin (up and down), armchair graphene nanoribbons \ensuremath{\leftrightarrow} ferromagnetic leads, graphene quantum wire \ensuremath{\leftrightarrow} semiconductor quantum wire, valley-orbit interaction \ensuremath{\leftrightarrow} Rashba spin-orbit interaction. The device works as follows. The source (drain) injects (detects) carriers in a specific valley polarization. A side gate electric field is applied to the channel and modulates the valley polarization of carriers due to the valley-orbit interaction, thus controlling the amount of current collected at the drain. The valley FET is characterized by (i) smooth interfaces between leads and the channel, (ii) strong valley-orbit interaction for electrical control of drain current, and (iii) vanishing interband valley-flip scattering. By its analogy to the spin FET, the valley FET provides a potential framework to develop low-power FETs for graphene-based nanoelectronics.