Design Of Low-power Devices Research Articles

Complex Multipliers:Implementation using Efficient Algorithms for Signal Processing Application

The research efforts in low power electronic devices and the cellular networks has been strengthened with the continuous growth in mobile and portable systems . In the modern era there are various portable applications that needs low power(smaller & efficient battery) and higher mili ampere hour then before. Due to this, design of low power devices has now become a significant Performance criteria. While considering the elementary structure of Finite impulse Response Filter, that is the arrangement of multipliers(which is a systematic arrangements of adders) and dely. This manuscript represents the simulation , implementation & analysis report for performance evaluation to minimize delay & RAM consumption during calculation procedure. In this manuscript, we have coded , simulated & implemented selected multipliers such as Vedic, Wallace, Dadda, Booth, Array & Sequential multiplier. Comparative analysis has been done using Xylinx 14.4 with family Spartan6, device as xc6slx45, package csg324 with speed grade of -3 for bit length 2,4,8,16 & 32 using Wallace, dada, Sequential, array, Vedic & Booth Algorithm respectively.

Low power device design application by magnetic tunnel junctions in Magnetoresistive Random Access Memory (MRAM)

The spintronics techniques combines the spin degree and charge which gives rise to state of the art devices like magnetic tunnel junctions which are ultra-low power devices. It is proposed in the paper to evaluate magnetic tunnel junctions (MTJ) at the device level. The paper present an overview of fabrication process, while considering different aspects of the characteristics of MTJs, performance, challenges and a wide range of applications which are different from conventional CMOS technology. The MTJ devices are CMOS compatible for non-volatility, high stability and reliability. The MTJ device is a promising candidate for building non-volatile circuits for ultra- low power operation and fast switching speeds. The current approaches to design logic functionalities and memory devices with MTJs w include hybrid CMOS and MTJ circuits are also discussed in the paper. The results on the most robust magnetic tunnel junction with Resistance Area = 8 Ω-µm2 demonstrates that it satisfies the statistical requirements in parallel with high magnetic tunnel resistance greater than 15σ(Rp), breakdown-of voltage to edge more than 0.5 V, read-induced rate beneath 10−9, and with adequate write endurance, free of undesirable write endurance magnetic inversion. Also this paper demonstrates on the most vigorous MTJ with Resistance Area = 8 Ω-µm2 that satisfies the statistical requirements in parallel with high magnetic tunnel resistance greater than 15σ(Rp),breakdown-of voltage to edge more than 0.5 V, read-induced rate less than 10−9, and with adequate write endurance, and is free of undesirable write endurance magnetic inversion.

Implementation and Designing of Low Power SR Flip-Flop Using 45NM CMOS Technology

The design of low-power devices is currently an important area of research due to an increase in demand for portable devices.Since the MOS device is widespread, there is a great need for circuits to consume less power, especially for portable and handheld devices. A memory element consumes 70 percent of the total power in an integrated circuit. As flip-flop is the primary place of memory elements to use on any portable device, a wide attention to reduce energy consumption flip-flop will help reducing energy consumption in a large IC. In this paper, we designed a flip-flop with CMOS logic; It consumes less energy than conventional gates designed. Switching transistors occurs when applied input clock is applied. Proposed SR flip-flop synchronization, 0.7V power dissipation transient analysis, and SR flip-flop different applications. This flip-flop is implemented using 45 nm in virtuoso cadence.

Multilevel characteristics for bipolar resistive random access memory based on hafnium doped SiO2 switching layer

We fabricated TiN/Hf:SiO2/Pt memory cell with the small size of 1×1um2 by lithography and sputtering technology, which demonstrated excellent bipolar resistive switching (RS) characteristics. The device presents good endurance and outstanding uniformity. The coefficient of variation of Vset, Vreset, Ron and Roff were found to be 5.05%, 4.78%, 4.18%, and 15.78%, respectively. For the device with hafnium doped SiO2 switching layer, multilevel storage capability can be successfully obtained by varying either the stop voltage or the compliance current in the SET process. In addition, the impact of forming current on the RS properties was studied. We found that the ratio of On/Off current for the device increased with the decrease of the forming current, which would be beneficial for the design of low power device. Possible RS mechanisms aiming to explain the impact of forming current on the RS characteristics and multilevel storage were also deduced.

(Invited) Promise of 2D Materials Beyond Graphene

Two dimensional systems, by the virtue of their unique material properties and excellent electrostatic integrity, provide immense opportunities not only to explore fundamental physics but also to solve critical technological problems. Graphene, Phosphorene, h-BN, MoS2, WSe2 and many others belong to this class of material which we are exploring. The fact that this class of materials contains metals, semiconductors, insulators and even superconductors at cryogenic temperature makes them extremely appealing across all scientific and engineering disciplines. In my talk I will demonstrate how “Contact Engineering” can be implemented to enhance the electrical performance of the 2D materials. Then I will talk about “Doping Constraints” and various “Scaling Aspects” of 2D materials. Finally I will discuss “Integration and Application” of 2D materials for flexible and transparent electronics as well as low power device design.

A Novel Latch design for Low Power Applications

Low power device design is now a vital field of research due to increase in demand of portable devices. This research paper proposes novel design of 8-transistor latch. Design comparison with the conventional design is performed at 65nm and 45nm to show technology independence. Comparative simulation results show that area and power efficient latch design is better choice for portable applications.

Analytical Modeling for Short Channel SOI-MOSFET and to Study its Performance

With the emergence of mobile computing and communication, low power device design and implementation have got a significant role to play in VLSI circuit design. Conventional silicon (bulk CMOS) technology couldn‘t overcome the fundamental physical limitations belonging to sub-micro or nanometer region which leads to alternative device technology like Silicon-on-Insulator (SOI) technology. In a fully-depleted FDSOI structure the electrostatic coupling of channel with source/drain and substrate through the buried layer (BL) is reduced. This allows in turn to reduce the minimal channel length of transistors or to relax the requirements on Si film thickness. A generalized compact threshold voltage model for SOI-MOSFET is developed by solving 2-D Poisson‘s equation in the channel region and analytical expressions are also developed for the same. The performance of the device is evaluated after incorporating the short channel effects. It is observed that in SOI, presence of the oxide layer resists the short channel effects and reduces device anomalies such as substrate leakage by a great factor than bulk-MOS. The threshold voltage and current drive make SOI the ultimate candidate for low power application. Thus SOI-MOSFET technology could very well be the solution for further ultra scale integration of devices and improvised performance.

User Interaction Based Design of Low Power Devices for Ad-hoc Networks

The design methodology presented in this paper proposes alternative strategies for increasing the battery life of devices in ad-hoc networks. It considers the operation of the device from the user's perspective in terms of the expected response from the device and how this can be achieved for minimum power consumption. This information is used to specify the operation of the radio network and shutdown procedures for the device so that it still maintains the required response for the user. Application of these strategies gives a very long battery life as demonstrated in an example design.